技术领域technical field
本申请涉及通信技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。The present application relates to the field of communication technology, and in particular to a thin film transistor and a manufacturing method thereof, an array substrate, and a display device.
背景技术Background technique
目前高分辨率显示产品成为市场主流趋势，实现液晶显示面板的高分辨率显示，对其像素开口率的要求越来越高，因此缩小薄膜晶体管(Thin Film Transistor，TFT)的尺寸变得尤为关键。现有技术中，存在一种垂直型TFT结构，可以大大减小TFT的尺寸，如图1所示，该垂直型TFT结构包括：玻璃基板1、缓冲层2、像素层3、源极金属层4、第一绝缘层5、漏极金属层6、氧化物(IGZO)层7、第二绝缘层8以及栅极金属层9，其中氧化物(IGZO)7属于有源层。虽然图1所示的垂直型TFT结构可以大大减小TFT的尺寸，但是该垂直型TFT结构目前仅适用于氧化物TFT，而非晶硅型TFT中非晶硅作为有源层，由于有源层与源极金属层及漏极金属层直接接触，因此非晶硅型TFT的欧姆接触较差，导致非晶硅型TFT的稳定性较差。At present, high-resolution display products have become the mainstream trend in the market. To achieve high-resolution display of liquid crystal display panels, the requirements for pixel aperture ratio are getting higher and higher. Therefore, reducing the size of thin film transistors (Thin Film Transistor, TFT) has become particularly critical. . In the prior art, there is a vertical TFT structure that can greatly reduce the size of the TFT. As shown in Figure 1, the vertical TFT structure includes: a glass substrate 1, a buffer layer 2, a pixel layer 3, and a source metal layer 4. The first insulating layer 5, the drain metal layer 6, the oxide (IGZO) layer 7, the second insulating layer 8 and the gate metal layer 9, wherein the oxide (IGZO) 7 belongs to the active layer. Although the vertical TFT structure shown in Figure 1 can greatly reduce the size of the TFT, the vertical TFT structure is currently only applicable to oxide TFTs, and amorphous silicon is used as the active layer in amorphous silicon TFTs. layer is in direct contact with the source metal layer and the drain metal layer, so the ohmic contact of the amorphous silicon TFT is poor, resulting in poor stability of the amorphous silicon TFT.
发明内容Contents of the invention
本申请实施例提供了一种薄膜晶体管及其制备方法、阵列基板、显示装置，用以使得有源层与薄膜晶体管中的源极金属层和漏极金属层通过欧姆接触层连接，从而降低有源层与源极金属层和漏极金属层之间的欧姆接触电阻，从而提高薄膜晶体管中有源层与源极金属层和漏极金属层之间的欧姆接触效果，进而可以提高薄膜晶体管的工作稳定性。The embodiment of the present application provides a thin film transistor and its preparation method, an array substrate, and a display device, so that the active layer is connected to the source metal layer and the drain metal layer in the thin film transistor through an ohmic contact layer, thereby reducing the active layer. The ohmic contact resistance between the source layer and the source metal layer and the drain metal layer, thereby improving the ohmic contact effect between the active layer and the source metal layer and the drain metal layer in the thin film transistor, thereby improving the thin film transistor. job stability.
本申请实施例提供的一种薄膜晶体管，包括：源极金属层，在所述源极金属层之上的第一绝缘层，在所述第一绝缘层之上的漏极金属层；所述薄膜晶体管还包括：有源层和欧姆接触层，所述有源层通过所述欧姆接触层与所述源极金属层和所述漏极金属层相连；其中，所述欧姆接触层包括第一欧姆接触层和第二欧姆接触层，所述第一欧姆接触层包括位于所述第一绝缘层两侧第一部分区域和第二部分区域。A thin film transistor provided in an embodiment of the present application includes: a source metal layer, a first insulating layer on the source metal layer, and a drain metal layer on the first insulating layer; the The thin film transistor further includes: an active layer and an ohmic contact layer, the active layer is connected to the source metal layer and the drain metal layer through the ohmic contact layer; wherein, the ohmic contact layer includes a first An ohmic contact layer and a second ohmic contact layer, the first ohmic contact layer includes a first partial area and a second partial area located on both sides of the first insulating layer.
本申请实施例提供的薄膜晶体管，通过设置欧姆接触层，使得源极层通过欧姆接触层与所述源极金属层和所述漏极金属层连接，即所述有源层不与所述源极金属层和所述漏极金属层直接接触，从而降低有源层与薄膜晶体管中的源极金属层和漏极金属层之间的欧姆接触电阻，提高有源层与所述源极金属层和所述漏极金属层之间的欧姆接触效果，进而可以提高垂直型非晶硅薄膜晶体管的工作稳定性。In the thin film transistor provided in the embodiment of the present application, by setting an ohmic contact layer, the source layer is connected to the source metal layer and the drain metal layer through the ohmic contact layer, that is, the active layer is not connected to the source The electrode metal layer is in direct contact with the drain metal layer, thereby reducing the ohmic contact resistance between the active layer and the source metal layer and the drain metal layer in the thin film transistor, and improving the active layer and the source metal layer. The ohmic contact effect between the drain metal layer and the drain metal layer can further improve the working stability of the vertical amorphous silicon thin film transistor.
较佳地，所述第二欧姆接触层位于所述第一绝缘层与所述漏极金属层之间。Preferably, the second ohmic contact layer is located between the first insulating layer and the drain metal layer.
较佳地，所述有源层包括分别位于所述第一绝缘层两侧的第一部分有源层和第二部分有源层，第一部分有源层位于第一欧姆接触层的第一部分区域与第二欧姆接触层之间，第二部分有源层位于第一欧姆接触层的第二部分区域与第二欧姆接触层之间。Preferably, the active layer includes a first part of the active layer and a second part of the active layer respectively located on both sides of the first insulating layer, and the first part of the active layer is located between the first part of the first ohmic contact layer and the second part of the active layer. Between the second ohmic contact layer, the second partial active layer is located between the second partial region of the first ohmic contact layer and the second ohmic contact layer.
较佳地，所述有源层包括非晶硅，和/或所述第一欧姆接触层和所述第二欧姆接触层包括电子型掺杂非晶硅。Preferably, the active layer includes amorphous silicon, and/or the first ohmic contact layer and the second ohmic contact layer include electronically doped amorphous silicon.
较佳地，所述薄膜晶体管还包括：Preferably, the thin film transistor also includes:
位于所述有源层之上的第二绝缘层；a second insulating layer over the active layer;
位于所述第二绝缘层之上的栅极金属层。A gate metal layer located on the second insulating layer.
本申请实施例提供的一种阵列基板，包括本申请实施例提供的薄膜晶体管。An array substrate provided in an embodiment of the present application includes the thin film transistor provided in the embodiment of the present application.
本申请实施例提供的一种显示装置，包括本申请实施例提供的阵列基板。A display device provided in an embodiment of the present application includes the array substrate provided in the embodiment of the present application.
本申请实施例提供的一种薄膜晶体管的制备方法，包括：在源极金属层之上设置第一绝缘层；在所述第一绝缘层之上设置漏极金属层；该方法还包括：设置有源层和欧姆接触层，所述有源层通过欧姆接触层与所述源极金属层和所述漏极金属层相连；其中，所述欧姆接触层包括第一欧姆接触层和第二欧姆接触层，所述第一欧姆接触层包括位于所述第一绝缘层两侧第一部分区域和第二部分区域。A method for manufacturing a thin film transistor provided in an embodiment of the present application includes: disposing a first insulating layer on the source metal layer; disposing a drain metal layer on the first insulating layer; the method further includes: disposing an active layer and an ohmic contact layer, the active layer is connected to the source metal layer and the drain metal layer through the ohmic contact layer; wherein the ohmic contact layer includes a first ohmic contact layer and a second ohmic contact layer A contact layer, the first ohmic contact layer includes a first partial area and a second partial area located on both sides of the first insulating layer.
较佳地，所述第一欧姆接触层和所述第二欧姆接触层在同一工艺流程中形成。Preferably, the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow.
较佳地，所述有源层在形成所述欧姆接触层和漏极金属层之后形成的。Preferably, the active layer is formed after the ohmic contact layer and the drain metal layer are formed.
附图说明Description of drawings
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.
图1为现有技术中垂直型氧化物TFT的结构示意图；FIG. 1 is a schematic structural diagram of a vertical oxide TFT in the prior art;
图2为本申请实施例提供的第一种薄膜晶体管的结构示意图；FIG. 2 is a schematic structural diagram of the first thin film transistor provided in the embodiment of the present application;
图3为本申请实施例提供的第二种薄膜晶体管的结构示意图；FIG. 3 is a schematic structural diagram of a second thin film transistor provided in an embodiment of the present application;
图4为本申请实施例提供的第三种薄膜晶体管的结构示意图；FIG. 4 is a schematic structural diagram of a third thin film transistor provided in an embodiment of the present application;
图5为本申请实施例提供的一种薄膜晶体管制备方法的流程示意图；FIG. 5 is a schematic flow diagram of a thin film transistor manufacturing method provided in an embodiment of the present application;
图6为本申请实施例提供的制备如图4所示的薄膜晶体管的第一种方法的流程示意图；FIG. 6 is a schematic flow chart of the first method for preparing the thin film transistor shown in FIG. 4 provided in the embodiment of the present application;
图7为本申请实施例提供的制备如图4所示的薄膜晶体管的第二种方法的流程示意图。FIG. 7 is a schematic flowchart of a second method for preparing the thin film transistor shown in FIG. 4 provided in the embodiment of the present application.
具体实施方式detailed description
本申请实施例提供了一种薄膜晶体管、阵列基板、显示面板、显示装置及制备方法，用以使得有源层与薄膜晶体管中的源极金属层和漏极金属层通过欧姆接触层连接，从而降低有源层与源极金属层和漏极金属层之间的欧姆接触电阻，从而提高薄膜晶体管中有源层与源极金属层和漏极金属层之间的欧姆接触效果，进而可以提高薄膜晶体管的工作稳定性。Embodiments of the present application provide a thin film transistor, an array substrate, a display panel, a display device, and a manufacturing method, so that the active layer is connected to the source metal layer and the drain metal layer in the thin film transistor through an ohmic contact layer, thereby Reduce the ohmic contact resistance between the active layer and the source metal layer and the drain metal layer, thereby improving the ohmic contact effect between the active layer and the source metal layer and the drain metal layer in the thin film transistor, thereby improving the thin film Transistor stability.
本申请实施例提供的一种薄膜晶体管，如图2所示，包括：源极金属层4，在所述源极金属层4之上的第一绝缘层5，位于第一绝缘层5之上的漏极金属层6；有源层12和欧姆接触层16，位于有源层12之上的第二绝缘层8，位于第二绝缘层8之上的栅极金属层9，所述有源层12通过欧姆接触层16与所述源极金属层4和所述漏极金属层6相连，所述欧姆接触层16包括第一欧姆接触层10和第二欧姆接触层11，所述第一欧姆接触层10包括位于所述第一绝缘层5两侧第一部分区域17和第二部分区域18。A thin film transistor provided in an embodiment of the present application, as shown in FIG. 2 , includes: a source metal layer 4, a first insulating layer 5 on the source metal layer 4, located on the first insulating layer 5 The drain metal layer 6; the active layer 12 and the ohmic contact layer 16, the second insulating layer 8 on the active layer 12, the gate metal layer 9 on the second insulating layer 8, the active Layer 12 is connected to the source metal layer 4 and the drain metal layer 6 through an ohmic contact layer 16, the ohmic contact layer 16 includes a first ohmic contact layer 10 and a second ohmic contact layer 11, the first The ohmic contact layer 10 includes a first partial region 17 and a second partial region 18 located on both sides of the first insulating layer 5 .
本申请实施例提供的薄膜晶体管，通过设置欧姆接触层，使得源极层通过欧姆接触层与所述源极金属层和所述漏极金属层连接，即所述有源层不与所述源极金属层和所述漏极金属层直接接触，从而降低有源层与源极金属层和漏极金属层之间的欧姆接触电阻，提高有源层与所述源极金属层和所述漏极金属层之间的欧姆接触效果，进而可以提高薄膜晶体管的工作稳定性。In the thin film transistor provided in the embodiment of the present application, by setting an ohmic contact layer, the source layer is connected to the source metal layer and the drain metal layer through the ohmic contact layer, that is, the active layer is not connected to the source The electrode metal layer is in direct contact with the drain metal layer, thereby reducing the ohmic contact resistance between the active layer and the source metal layer and the drain metal layer, and improving the active layer and the source metal layer and the drain metal layer. The ohmic contact effect between the pole metal layers can improve the working stability of the thin film transistor.
在如图2所示的薄膜晶体管中，所述第二欧姆接触层11位于所述第一绝缘层5与所述漏极金属层6之间，即第二欧姆接触层与第一绝缘层在垂直方向上的投影存在重叠部分，所述第二欧姆接触层可以是连续的一整层设置于第一绝缘层与漏极金属层之间，也可以不连续设置于第一绝缘层与漏极金属层之间，如图3所示，该薄膜晶体管中，第二欧姆接触层11分成两部分区域设置于第一绝缘层5和漏极金属层6之间。需要说明的是，第一绝缘层的截面可以是如图2、图3所示的梯形，也可以是矩形，本申请以第一绝缘层的截面为梯形为例进行说明，但实际生产中，可根据需要设置第一绝缘层的形状。In the thin film transistor shown in FIG. 2, the second ohmic contact layer 11 is located between the first insulating layer 5 and the drain metal layer 6, that is, the second ohmic contact layer and the first insulating layer are in the There are overlapping parts in the projection in the vertical direction, and the second ohmic contact layer can be a continuous whole layer arranged between the first insulating layer and the drain metal layer, or can be discontinuously arranged between the first insulating layer and the drain Between the metal layers, as shown in FIG. 3 , in the thin film transistor, the second ohmic contact layer 11 is divided into two regions and disposed between the first insulating layer 5 and the drain metal layer 6 . It should be noted that the cross section of the first insulating layer can be trapezoidal as shown in Figure 2 and Figure 3, or rectangular. This application uses the trapezoidal cross section of the first insulating layer as an example for illustration, but in actual production, The shape of the first insulating layer can be set as required.
在如图2所示的薄膜晶体管中，所述有源层包括分别位于所述第一绝缘层两侧的第一部分有源层19和第二部分有源层20，第一部分有源层19位于第一欧姆接触层10的第一部分区域17与第二欧姆接触层11之间，第二部分有源层20位于第一欧姆接触层10的第二部分区域18与第二欧姆接触层11之间。In the thin film transistor shown in FIG. 2 , the active layer includes a first part of the active layer 19 and a second part of the active layer 20 respectively located on both sides of the first insulating layer, and the first part of the active layer 19 is located on Between the first partial region 17 of the first ohmic contact layer 10 and the second ohmic contact layer 11, the second partial active layer 20 is located between the second partial region 18 of the first ohmic contact layer 10 and the second ohmic contact layer 11 .
较佳地，所述有源层包括非晶硅(a-Si)。Preferably, the active layer includes amorphous silicon (a-Si).
较佳地，所述第一欧姆接触层和所述第二欧姆接触层包括电子型掺杂非晶硅(n+a-Si)。Preferably, the first ohmic contact layer and the second ohmic contact layer include electronically doped amorphous silicon (n+a-Si).
以第一部分有源层19和第二部分有源层20全部为a-Si层15、第一欧姆接触层以及第二欧姆接触层为n+a-Si情况为例，本申请实施例提供的薄膜晶体管结构如图4所示，第二n+a-Si层14位于第一绝缘层5和漏极金属层6之间，a-Si层15在第一绝缘层5两侧与第一n+a-Si层13接触和第二n+a-Si层14接触。Taking the case where the first part of the active layer 19 and the second part of the active layer 20 are all a-Si layer 15, and the first ohmic contact layer and the second ohmic contact layer are n+a-Si, the embodiment of the present application provides The thin film transistor structure is shown in Figure 4, the second n+a-Si layer 14 is located between the first insulating layer 5 and the drain metal layer 6, the a-Si layer 15 is on both sides of the first insulating layer 5 and the first n+ The +a-Si layer 13 is in contact with the second n+a-Si layer 14 .
需要说明的是，本申请实施例提供的如图2、图3以及图4所示薄膜晶体管，有源层与源极金属层和漏极金属层均不接触，但只要在有源层通过欧姆接触层与源极金属层和漏极金属层接触的情况下，即可降低有源层与源极金属层和漏极金属层之间的欧姆接触电阻，提高有源层与源极金属层和漏极金属层之间的欧姆接触效果。因此，在实际情况中，在满足有源层通过欧姆接触层与源极金属层和漏极金属层接触的情况下，即在保证有源层与源极金属层和漏极金属层欧姆接触效果良好的情况下，有源层也可以与源极金属层和漏极金属层部分接触。It should be noted that, for the thin film transistors shown in FIG. 2 , FIG. 3 and FIG. 4 provided by the embodiment of the present application, the active layer does not contact the source metal layer and the drain metal layer, but as long as the active layer passes through the ohmic When the contact layer is in contact with the source metal layer and the drain metal layer, the ohmic contact resistance between the active layer and the source metal layer and the drain metal layer can be reduced, and the contact between the active layer and the source metal layer can be improved. Ohmic contact effect between drain metal layers. Therefore, in actual situations, under the condition that the active layer is in contact with the source metal layer and the drain metal layer through the ohmic contact layer, that is, the ohmic contact effect between the active layer and the source metal layer and the drain metal layer is ensured. Under good conditions, the active layer may also be in partial contact with the source metal layer and the drain metal layer.
本申请实施例提供的一种阵列基板，包括本申请实施例提供的薄膜晶体管。An array substrate provided in an embodiment of the present application includes the thin film transistor provided in the embodiment of the present application.
本申请实施例提供的一种显示装置，包括本申请实施例提供的阵列基板。A display device provided in an embodiment of the present application includes the array substrate provided in the embodiment of the present application.
例如，本申请实施例提供的显示装置，可以是液晶显示面板或有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板等，也可以是手机、电视、电脑等装置。For example, the display device provided in the embodiment of the present application may be a liquid crystal display panel or an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel, etc., or may be a mobile phone, a television, a computer, or other devices.
与本申请实施例提供的薄膜晶体管相对应，本申请实施例还提供了一种薄膜晶体管制备方法，如图5所示，该方法包括：Corresponding to the thin film transistor provided in the embodiment of the present application, the embodiment of the present application also provides a thin film transistor manufacturing method, as shown in FIG. 5 , the method includes:
S501、在源极金属层之上设置第一绝缘层；S501, disposing a first insulating layer on the source metal layer;
S502、在所述第一绝缘层之上设置漏极金属层；S502, disposing a drain metal layer on the first insulating layer;
S503、设置有源层和欧姆接触层，所述有源层通过欧姆接触层与所述源极金属层和所述漏极金属层相连；S503, providing an active layer and an ohmic contact layer, the active layer is connected to the source metal layer and the drain metal layer through the ohmic contact layer;
其中，所述欧姆接触层包括第一欧姆接触层和第二欧姆接触层，所述第一欧姆接触层包括位于所述第一绝缘层两侧第一部分区域和第二部分区域。Wherein, the ohmic contact layer includes a first ohmic contact layer and a second ohmic contact layer, and the first ohmic contact layer includes a first partial area and a second partial area located on both sides of the first insulating layer.
本申请实施例提供的薄膜晶体管制备方法，The thin film transistor preparation method provided in the embodiment of the present application,
较佳地，所述第一欧姆接触层和所述第二欧姆接触层在同一工艺流程中形成。Preferably, the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow.
本申请实施例提供的薄膜晶体管制备方法，所述第一欧姆接触层和所述第二欧姆接触层在同一工艺流程中形成，从而可以简化薄膜晶体管制备步骤，减少薄膜晶体管制备工艺流程。In the thin film transistor manufacturing method provided in the embodiment of the present application, the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow, thereby simplifying the thin film transistor manufacturing steps and reducing the thin film transistor manufacturing process flow.
较佳地，所述有源层在形成所述欧姆接触层和漏极金属层之后形成的。Preferably, the active layer is formed after the ohmic contact layer and the drain metal layer are formed.
需要说明的是，如果有源层在欧姆接触层和漏极金属层形成之前设置，之后对欧姆接触层以及漏极金属层进行刻蚀的过程中可能会刻蚀到有源层，造成对有源层过刻，影响薄膜晶体管工作稳定性。本申请实施例提供的薄膜晶体管制备方法，有源层是在第一欧姆接触层、第二欧姆接触层以及漏极金属层之后设置的，从而避免因有源层过刻引起的薄膜晶体管工作稳定性差。It should be noted that if the active layer is provided before the formation of the ohmic contact layer and the drain metal layer, the active layer may be etched during the subsequent etching of the ohmic contact layer and the drain metal layer, causing damage to the active layer. The overcut of the source layer affects the working stability of the thin film transistor. In the preparation method of the thin film transistor provided in the embodiment of the present application, the active layer is arranged after the first ohmic contact layer, the second ohmic contact layer and the drain metal layer, so as to avoid the stable operation of the thin film transistor caused by over-etching of the active layer Poor sex.
下面以制备如图4所示的薄膜晶体管结构为例，对本申请实施例提供的薄膜晶体管制备方法进行说明。Taking the preparation of the thin film transistor structure shown in FIG. 4 as an example, the method for preparing the thin film transistor provided in the embodiment of the present application will be described below.
较佳地，所述薄膜晶体管还包括玻璃基板。Preferably, the thin film transistor further includes a glass substrate.
方式一，如图6所示，制备薄膜晶体管具体包括如下步骤：Method 1, as shown in FIG. 6 , the preparation of a thin film transistor specifically includes the following steps:
S601、在玻璃基板1之上沉积源极金属层，曝光之后刻蚀形成源极金属层4；S601, depositing a source metal layer on the glass substrate 1, and etching to form a source metal layer 4 after exposure;
S602、在所述源极金属层4之上沉积第一绝缘层，曝光之后刻蚀形成第一绝缘层5；S602, depositing a first insulating layer on the source metal layer 4, and etching to form a first insulating layer 5 after exposure;
S603、沉积n+a-Si层，曝光之后刻蚀形成第一n+a-Si层13以及第二n+a-Si层14；第二n+a-Si层14位于第一绝缘层5之上，第一n+a-Si层13位于第一绝缘层5两侧且位于源极金属层4之上；S603, depositing an n+a-Si layer, etching to form a first n+a-Si layer 13 and a second n+a-Si layer 14 after exposure; the second n+a-Si layer 14 is located on the first insulating layer 5 Above, the first n+a-Si layer 13 is located on both sides of the first insulating layer 5 and above the source metal layer 4;
S604、在所述第二n+a-Si层14之上沉积漏极金属层，曝光之后刻蚀形成漏极金属层6；S604, depositing a drain metal layer on the second n+a-Si layer 14, and etching to form the drain metal layer 6 after exposure;
S605、在步骤S604之后沉积a-Si层，曝光之后刻蚀形成a-Si层15；a-Si层15在第一绝缘层5两侧与第一n+a-Si层13和第二n+a-Si层14接触；S605, depositing an a-Si layer after step S604, and etching to form an a-Si layer 15 after exposure; the a-Si layer 15 is connected to the first n+a-Si layer 13 and the second n + a-Si layer 14 contact;
S606、在所述a-Si层15之上设置第二绝缘层8，并在所述第二绝缘层上刻蚀过孔(图中未示出)；S606, disposing a second insulating layer 8 on the a-Si layer 15, and etching via holes (not shown in the figure) on the second insulating layer;
S607、在所述第二绝缘层8之上沉积栅极金属层，曝光之后刻蚀形成栅极金属层9。S607 , depositing a gate metal layer on the second insulating layer 8 , and etching to form a gate metal layer 9 after exposure.
方式二，如图7所示，制备薄膜晶体管具体包括如下步骤：Method 2, as shown in FIG. 7 , the preparation of a thin film transistor specifically includes the following steps:
S701、在玻璃基板1之上沉积源极金属层，曝光之后刻蚀形成源极金属层4；S701, depositing a source metal layer on the glass substrate 1, and etching to form a source metal layer 4 after exposure;
S702、在所述源极金属层4之上沉积第一绝缘层，曝光之后刻蚀形成第一绝缘层5；S702, depositing a first insulating layer on the source metal layer 4, and etching to form a first insulating layer 5 after exposure;
S703、沉积n+a-Si层，在所述n+a-Si层之上沉积漏极金属层，采用半透掩模(halftone mask，HTM)对金属层、n+a-Si层进行刻蚀，形成第一n+a-Si层13、第二n+a-Si层14，再采用光刻胶灰化进一步对金属层刻蚀，形成漏极金属层6；第二n+a-Si层14位于第一绝缘层5之上，漏极金属层6位于第二n+a-Si层14之上，第一n+a-Si层13位于第一绝缘层5两侧且位于源极金属层4之上；S703, deposit an n+a-Si layer, deposit a drain metal layer on the n+a-Si layer, and use a halftone mask (halftone mask, HTM) to etch the metal layer and the n+a-Si layer etch to form the first n+a-Si layer 13 and the second n+a-Si layer 14, and then use photoresist ashing to further etch the metal layer to form the drain metal layer 6; the second n+a- The Si layer 14 is located on the first insulating layer 5, the drain metal layer 6 is located on the second n+a-Si layer 14, and the first n+a-Si layer 13 is located on both sides of the first insulating layer 5 and on the source on the pole metal layer 4;
S704、沉积a-Si层，曝光之后刻蚀形成a-Si层15；a-Si层15在第一绝缘层5两侧与第一n+a-Si层13和第二n+a-Si层14接触；S704, deposit an a-Si layer, etch to form an a-Si layer 15 after exposure; layer 14 contacts;
S705、在所述a-Si层15之上设置第二绝缘层8，并在所述第二绝缘层上刻蚀过孔(图中未示出)；S705, disposing a second insulating layer 8 on the a-Si layer 15, and etching via holes (not shown in the figure) on the second insulating layer;
S706、在所述第二绝缘层8之上沉积栅极金属层，曝光之后刻蚀形成栅极金属层9。S706 , depositing a gate metal layer on the second insulating layer 8 , and etching to form a gate metal layer 9 after exposure.
采用本申请实施例提供的上述两种薄膜晶体管制备方式，通过在a-Si层与源极金属层和漏极金属层之间设置第一n+a-Si层和第二n+a-Si层，从而可以降低a-Si层与源极金属层和漏极金属层之间的欧姆接触电阻，提高a-Si层与源极金属层和漏极金属层之间的欧姆接触效果。同时，上述两种薄膜晶体管制备方式，第一n+a-Si层和第二n+a-Si层同层设置、在同一工艺流程中形成的，简化了薄膜晶体管制备的步骤。并且，由于a-Si层在n+a-Si层和漏极金属层刻蚀之后进行刻蚀，从而可以控制对a-Si层的刻蚀时间和刻蚀速率，不会产生因对a-Si层过刻引起的TFT工作稳定性变差。Using the above two thin film transistor preparation methods provided in the embodiments of the present application, by setting the first n+a-Si layer and the second n+a-Si layer between the a-Si layer and the source metal layer and the drain metal layer layer, so that the ohmic contact resistance between the a-Si layer and the source metal layer and the drain metal layer can be reduced, and the ohmic contact effect between the a-Si layer and the source metal layer and the drain metal layer can be improved. At the same time, in the above-mentioned two thin film transistor preparation methods, the first n+a-Si layer and the second n+a-Si layer are arranged in the same layer and formed in the same process flow, which simplifies the steps of thin film transistor preparation. Moreover, since the a-Si layer is etched after the n+a-Si layer and the drain metal layer are etched, the etching time and the etching rate of the a-Si layer can be controlled, and there will be no damage to the a-Si layer. The stability of the TFT caused by over-cutting of the Si layer deteriorates.
需要说明的是，本申请实施例提供的上述制备薄膜晶体管的两种方式，只是在制备薄膜晶体管过程中的对薄膜晶体管每层的刻蚀的顺序不同，但均可以形成如图4所示的薄膜晶体管，上述制备薄膜晶体管的两种不同方式，对薄膜晶体管的性能并无影响。此外，与方式一相比，方式二提供的薄膜晶体管制备方法，由于采用半透掩模工艺对漏极金属层和n+a-Si层进行刻蚀，从而可以减少一张光罩(mask)，不仅降低了生产成本，同时减少了一步曝光过程，从而减少了工艺时长，可以增加产能。It should be noted that the above two methods of preparing thin film transistors provided in the embodiments of the present application are only different in the order of etching each layer of the thin film transistor in the process of preparing the thin film transistor, but both can form the thin film transistor as shown in Figure 4. For thin film transistors, the above two different ways of preparing thin film transistors have no effect on the performance of thin film transistors. In addition, compared with method 1, the thin film transistor manufacturing method provided by method 2 can reduce a mask (mask) due to the use of a semi-transparent mask process to etch the drain metal layer and the n+a-Si layer. , not only reduces the production cost, but also reduces the one-step exposure process, thereby reducing the process time and increasing production capacity.
综上所述，本申请实施例提供的薄膜晶体管、阵列基板、显示面板、显示装置及薄膜晶体管的制备方法，通过设置欧姆接触层，使得源极层通过欧姆接触层与所述源极金属层和所述漏极金属层连接，即所述有源层不与所述源极金属层和所述漏极金属层完全直接接触，从而降低有源层与源极金属层和漏极金属层之间的欧姆接触电阻，提高有源层与所述源极金属层和所述漏极金属层之间的欧姆接触效果，进而可以提高薄膜晶体管的工作稳定性。此外，本申请实施例提供的薄膜晶体管制备方法，第一欧姆接触层和第二欧姆接触层是在同一工艺流程中形成的，简化了薄膜晶体管制备的步骤。并且，由于有源层在欧姆接触层和漏极金属层之后进行刻蚀，可以控制对有源层的刻蚀时间和刻蚀速率，从而不会产生因对有源层过刻引起的薄膜晶体管稳定性变差。To sum up, in the thin film transistor, array substrate, display panel, display device, and thin film transistor manufacturing method provided in the embodiments of the present application, an ohmic contact layer is provided so that the source layer is connected to the source metal layer through the ohmic contact layer. connected to the drain metal layer, that is, the active layer is not completely in direct contact with the source metal layer and the drain metal layer, thereby reducing the distance between the active layer and the source metal layer and the drain metal layer The ohmic contact resistance between them improves the ohmic contact effect between the active layer and the source metal layer and the drain metal layer, thereby improving the working stability of the thin film transistor. In addition, in the thin film transistor manufacturing method provided in the embodiment of the present application, the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow, which simplifies the manufacturing steps of the thin film transistor. Moreover, since the active layer is etched after the ohmic contact layer and the drain metal layer, the etching time and etching rate of the active layer can be controlled, so that the thin film transistor caused by over-etching the active layer will not be produced. Stability deteriorates.
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.
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| CN201710131890.3ACN106847892B (en) | 2017-03-07 | 2017-03-07 | Thin film transistor, preparation method thereof, array substrate and display device |
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| CN114373772A (en)* | 2021-12-29 | 2022-04-19 | 长沙惠科光电有限公司 | Array substrate, preparation method thereof and display panel |
| CN114975613A (en)* | 2022-06-22 | 2022-08-30 | 武汉华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
| WO2024119795A1 (en)* | 2022-12-08 | 2024-06-13 | 武汉华星光电技术有限公司 | Display panel and display device |
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| CN101097871A (en)* | 2007-07-05 | 2008-01-02 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
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| CN101097871A (en)* | 2007-07-05 | 2008-01-02 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
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| CN114373772A (en)* | 2021-12-29 | 2022-04-19 | 长沙惠科光电有限公司 | Array substrate, preparation method thereof and display panel |
| CN114373772B (en)* | 2021-12-29 | 2024-10-01 | 长沙惠科光电有限公司 | Array substrate, preparation method thereof and display panel |
| CN114975613A (en)* | 2022-06-22 | 2022-08-30 | 武汉华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
| WO2024119795A1 (en)* | 2022-12-08 | 2024-06-13 | 武汉华星光电技术有限公司 | Display panel and display device |
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