The content of the invention
In view of this, it is an object of the invention to provide a kind of small power consumption, the leadage circuit of efficiency high and its method and LEDControl circuit, is used to solve the technical problem of prior art presence.
Technical solution of the invention is to provide a kind of leadage circuit of following structure, including：
Release module, exchange input obtains input voltage load is supplied through drive circuit through controllable silicon dimmer and rectifier bridgeElectricity, the two ends of the module of releasing are connected with the cold end high of input voltage respectively；
Release control circuit, the control end with the module of releasing is connected；Input voltage zero crossing is directly or indirectly detected,After input voltage zero crossing the second time of time delay, the control module generation leakage current of releasing, the drive circuit it is defeatedEnter electric current to reach the predetermined value moment then to control leakage current be zero；Controllable silicon dimmer turn-on instant is defeated with the drive circuitIt is the very first time to enter the time that electric current reached between the predetermined value moment；
Wherein, when the described very first time reference time is more than, then extended for the second time；When the very first time is less than referenceDuring the time, then shortened for the second time so that the very first time levels off to the reference time.
Preferably, described control circuit of releasing includes input voltage detection circuit, drive circuit input electric cur- rent measureCircuit and logic circuit, described logic circuit are connected with the control end of module of releasing, and described input voltage detection circuit is adoptedSample input voltage, when input voltage sampled signal reaches threshold voltage, then after the time of time delay second, through logic circuit controlThe module of releasing produces leakage current；Described drive circuit input electric cur- rent measure electric circuit inspection drive circuit input current,When sample rate current reaches the threshold current for characterizing predetermined value, then it is zero to control leakage current through logic circuit；By described firstTime is compared with the reference time, and second time is correspondingly adjusted according to comparative result.
Preferably, described control circuit of releasing also includes time delay module and time comparison module, described time delay mouldBlock output end respectively with input voltage detection circuit, logic circuit and time comparison module are connected, and described time delay module existsEnter the time of line delay second when input voltage sampled signal reaches threshold voltage, after time delay terminates, by logic circuit controlLeakage current is produced, the comparing of the very first time and the reference time is carried out in the time comparison module, and knot will be comparedFruit feeds back to the time delay module to adjust second time.
Preferably, described logic circuit includes the first trigger and the second trigger, described time delay module outputThe status signal whether time delay terminates is characterized, the set end of first trigger receives the shape whether sign time delay terminatesState signal, the output end of input voltage detection circuit and the output end of time delay module are respectively connected to NAND gate, the NAND gateOutput end is connected with the replacement end of first trigger；The output end of first trigger is triggered after negating with described secondThe set end connection of device, the output end of drive circuit input electric cur- rent measure circuit negate after replacement end with second triggerThe output end of connection, the output end of second trigger and the drive circuit input electric cur- rent measure circuit is connected and door respectivelyTwo inputs, two inputs for being connected OR gate respectively with the output end of door and the output end of the first trigger, instituteState OR gate output and characterize the signal for whether enabling to the module of releasing, it is described to be exported for characterizing when first with door output endBetween timing signal.
Preferably, described control circuit of releasing includes that drive circuit input electric cur- rent measure circuit, leakage current are detectedCircuit and logic circuit, described logic circuit are connected with the control end of module of releasing, described drive circuit input current inspectionSlowdown monitoring circuit sampling drive circuit input current, and be compared with threshold current；Described vent discharge current detection circuit is in inputDuring voltage zero-cross is detected, module of being released described in the logic circuit control produces leakage current, the leakage current of sampling, andThreshold value is compared with releasing；When the drive circuit input current is less than the threshold current, start timing, let out until describedDischarge stream is reached when releasing threshold value, and timing terminates, and the timing time is used as the 3rd time.
When the drive circuit input current is less than the threshold current, judge that input voltage reaches after the 3rd timeTo zero crossing；And can timing or not timing the 3rd time of renewal.
Preferably, when judging that input voltage reaches zero crossing, it is described through logic circuit control after the time of time delay secondModule of releasing produces leakage current；Described drive circuit input electric cur- rent measure electric circuit inspection drive circuit input current, when adoptingWhen sample electric current reaches the threshold current for characterizing predetermined value, then it is zero to control leakage current through logic circuit；By the very first timeIt is compared with the reference time, second time is correspondingly adjusted according to comparative result.
Preferably, described control circuit of releasing also includes time delay module, time comparison module and zero passage judge module,Described time delay module output end respectively with zero passage judge module, logic circuit and time comparison module are connected, the zero passageJudge module is connected with the output end of vent discharge current detection circuit and the output end of drive circuit input electric cur- rent measure circuit respectively；Timing is carried out to the 3rd time by the zero passage judge module, and judge the zero crossing moment of input voltage, described time delay mouldBlock receives the signal at the sign zero crossing moment of the zero passage judge module output, and the time of time delay second, after time delay terminates, leads toCross logic circuit control and produce leakage current, the ratio of the very first time and the reference time is carried out in the time comparison moduleCompared with, and comparative result is fed back into the time delay module to adjust second time.
Preferably, described logic circuit includes the 3rd trigger and the 4th trigger, described time delay module outputThe status signal whether time delay terminates is characterized, the set end of the 3rd trigger receives the shape whether sign time delay terminatesState signal, the output end of zero passage judge module and the output end of time delay module are respectively connected to NAND gate, the output of the NAND gateEnd is connected with the replacement end of the 3rd trigger；The output end of the 3rd trigger negate after with the 4th triggerSet end is connected, and the output end of drive circuit input electric cur- rent measure circuit connects after negating with the replacement end of the 4th triggerConnect, the output end of the 4th trigger and the output end of the drive circuit input electric cur- rent measure circuit connect respectively first withTwo inputs of door, the output end of drive circuit input electric cur- rent measure circuit and characterize the letter whether zero passage judge module enablesNumber it is respectively connected to two inputs of second and door；Described first touches with the output end of door, second with the output end of door and the 3rdThe output end for sending out device connects three inputs of OR gate respectively, and whether the OR gate output characterizes the signal for enabling and released to describedModule, described first exports the timing signal for characterizing the very first time with the output end of door.
Another technical solution of the invention is to provide a kind of control method of the leadage circuit of following steps：
Exchange input obtains input voltage through drive circuit to load supplying through controllable silicon dimmer and rectifier bridge, mould of releasingThe two ends of block are connected with the cold end high of input voltage respectively；
Directly or indirectly detection input voltage zero crossing, after input voltage zero crossing the second time of time delay, controls describedModule of releasing produces leakage current, and the input current of the drive circuit reaches the predetermined value moment, and then to control leakage current be zero；When the time that the input current of controllable silicon dimmer turn-on instant and the drive circuit reaches between the predetermined value moment is firstBetween；
Wherein, when the described very first time reference time is more than, then extended for the second time；When the very first time is less than referenceDuring the time, then shortened for the second time so that the very first time levels off to the reference time.
Another technical solution of the invention is to provide a kind of LED control circuit of following structure, including：To take up an official postAnticipate a kind of leadage circuit and LED drive circuit, described LED drive circuit is linear drive circuit or on-off circuit.
Using circuit structure of the invention and method, compared with prior art, with advantages below：The present invention is applied to canThe LED control circuit of control silicon light modulation, directly or indirectly detects input voltage zero crossing, the time delay second at input voltage zero crossingAfter time, module of releasing works to produce leakage current, controllable silicon dimmer turn-on instant to be reached with drive circuit input currentTime of the predetermined value (the maintenance electric current of controllable silicon dimmer) between the moment is the very first time.Within very first time time, let outElectric discharge road produces loss, when the very first time predetermined value is more than, extends for the second time；When the very first time predetermined value is less than, contractingShort second time so that very first time time is close or equal to predetermined value.Using the present invention, can adaptively according to first whenBetween adjusted as second time of time delay with the size of predetermined value, reduce power consumption of releasing, and improve system effectRate.
Specific embodiment
The preferred embodiments of the present invention are described in detail below in conjunction with accompanying drawing, but the present invention is not restricted to theseEmbodiment.The present invention covers any replacement made in the spirit and scope of the present invention, modification, equivalent method and scheme.
In order that the public has to the present invention thoroughly understanding, it is described in detail in present invention below preferred embodiment specificDetails, and description without these details can also completely understand the present invention for a person skilled in the art.
The present invention is more specifically described by way of example referring to the drawings in the following passage.It should be noted that, accompanying drawing is adoptedNon- accurately ratio is used with the form for more simplifying and, is only used to convenience, lucidly aided in illustrating the embodiment of the present inventionPurpose.
With reference to shown in Fig. 3, the work wave of leadage circuit of the present invention is illustrated.Input voltage vin, input are illustrated in figureThe waveform of electric current iin and leakage current iblr.By directly or indirectly detection input voltage vin zero crossing, reached in input voltageTo then after the second time of time delay t2, control leadage circuit produces leakage current iblr, when controllable silicon dimmer is turned on during zero crossingCarve and drive circuit input current iin2 reach predetermined value (the generally maintenance electric current of controllable silicon dimmer) between the moment whenBetween be very first time t1.In very first time t1, leadage circuit produces loss, when t1 is more than predetermined value T, increases for the second timet2；When t1 is less than predetermined value T, reduce the second time t2 so that very first time time t1 is close or equal to predetermined value T.In figure,+ VF and-VF is equal to the conduction threshold of diode.
With reference to shown in Fig. 4, the FB(flow block) of leadage circuit of the present invention is illustrated.First judge input voltage vin whether zero passage,The threshold voltage being positioned proximate in zero is compared with sampled voltage, it is also possible to obtain input voltage vin indirectly by other amountsThe moment of zero passage.Described input voltage vin is exchange input through the input voltage vin obtained by controllable silicon dimmer.DefeatedAfter entering the second time of voltage over zero time delay t2, module of being released described in control is enabled to produce leakage current iblr.When input electricityAfter pressure Vin zero passages, start timing, the input current iin2 of the drive circuit reaches predetermined value (typically using controllable silicon light modulationThe maintenance size of current of device) moment, then leadage circuit do not enable, leakage current is zero, and now timing terminates；Above-mentioned timing timeThe input current of as controllable silicon dimmer turn-on instant and the drive circuit reaches the time between the predetermined value moment, isOne time t1.When described very first time t1 is more than reference time T, then extend the second time t2；When very first time t1 is less thanDuring reference time T, then shorten the second time t2 so that the very first time levels off to reference time T.The method is shortened when releasingBetween, reduce release power consumption, lifting system efficiency.
With reference to shown in Fig. 5, the circuit structure of leadage circuit embodiment one of the present invention is illustrated, be applied to controllable silicon light modulationIn LED control circuit.LED control circuit includes leadage circuit and LED drive circuit, and described leadage circuit includes module of releasingWith control circuit of releasing, described leadage circuit be used to solve being caused by input current is too small under the controllable silicon dimmerFlicker problem, and overcome the technological deficiency existing for prior art.Its input power is that exchange is input into, and the exchange input warp canThe input voltage vrec of direct current is exported after control silicon light modulator U02 and rectifier bridge U01, i.e., as the input voltage of LED load.ExchangeInput is connected to rectifier bridge U01 by controllable silicon dimmer U02, and the positive output end of rectifier bridge is connected with the anode of diode D00,LED drive circuit anode is connected with the negative electrode of the diode D00.Usual LED drive circuit can be presented certain capacitive, therefore,Diode D00 is added between vrec and LED drive circuit；When exchange input absolute value reduction when, LED drive circuit due toWith capacitive, its voltage can reduce relatively slow, and the sampling resistor for adding diode D00 and input voltage vrec detection circuits can be byThe absolute value of vrec voltage follows exchange input, so as to ensure the degree of accuracy to input voltage sampling.
Described leadage circuit includes releasing and module and releases control circuit, described module of releasing include adjustment pipe and withThe current source or resistance of the adjustment pipe series connection.Main improvement of the invention is release control circuit and corresponding controlling partyMethod.Described control circuit of releasing includes input voltage vrec detections circuit, drive circuit input electric cur- rent measure circuit and logicCircuit U 12, described logic circuit U12 is connected with the control end of the module U03 that releases, described input voltage vrec detection circuitsSampled input voltage, (is compared), then when input voltage sampled signal reaches threshold voltage VREF1 in comparator U10After the second time of time delay t2, through being released described in logic circuit U12 controls, module U03 produces leakage current iblr；Described driveDynamic circuit input electric cur- rent measure electric circuit inspection drive circuit input current iin2, when sample rate current reaches the threshold value for characterizing predetermined value(it is compared in comparator U40) during electric current VREF4, then it is zero to control leakage current iblr through logic circuit U12；Will be describedVery first time t1 is compared with the reference time T, and second time t2 is correspondingly adjusted according to comparative result.When describedDrive circuit be linear drive circuit when, the electric current of the adjustment pipe M30 of the linear drive circuit of sample streams, you can for characterizingThe input current in2 of the drive circuit.
Described control circuit of releasing also includes time delay module U13 and time comparison module U14, the time delay module U13For entering line delay to the input voltage crossover point signal ZVD that input voltage vrec detection circuits are produced, and after time delay terminates,Logic circuit U12 is given by signal transmission, to cause module U03 enables of releasing.When the time comparison module U14 is used for firstBetween the t1 and reference time T be compared, to realize the feedback regulation to the second time t2.Described time delay module U13 pointsOutput end, logic circuit U12 and time comparison module U13 not with input voltage vrec detection circuits are connected, described time delayModule U13 is entering the second time of line delay t2 when input voltage sampled signal reaches threshold voltage VREF1, after time delay terminates,Control to produce leakage current iblr by logic circuit U12, very first time t1 and institute are carried out in the time comparison module U14The comparing of reference time T is stated, and comparative result is fed back into the time delay module to adjust second time t2.
With reference to shown in Fig. 6, the FB(flow block) of the logic circuit U12 of leadage circuit embodiment of the present invention is illustrated.This accompanying drawingWith reference to Fig. 5, the specific implementation step for obtaining embodiment one is：The initial value of t2 is 0.AC power through controllable silicon dimmer U02,After rectifier bridge U01, the voltage vrec after rectification is obtained.Resistance R10, R11 carry out partial pressure to vrec, the voltage on resistance R11During less than reference voltage VREF1, the output ZVD upsets of comparator U10, the starting point as input voltage vrec zero crossings is believedNumber.The negative input end of comparator U10 is connected to R11, reference voltage is connected to as a example by the positive input terminal of comparator U10.When defeatedWhen entering voltage zero-cross, voltage is less than VREF1 on resistance R11, then the output ZVD of comparator U10 is changed into high level from low level.After delay circuit U13 time delays t2, delay circuit output signal ZVDLY overturns the high level signal of ZVD, and is input to logic electricityLeadage circuit enabler flags position EN is put 1 by road U12, logic circuit U12, and leadage circuit is enabled, and busbar voltage vrec is pulled down toClose to 0V.When the output ZVD of comparator U10 is low, i.e. at the t01 moment in Fig. 3, logic circuit U12 starts timing, timing signalBLT is uprised from low.Drive circuit input electric cur- rent measure electric circuit inspection iin2 electric currents, when voltage RS is low on current sampling resistor R40When reference voltage VREF4, i.e. between t01-t02, leadage circuit U03 continues to enable.When voltage RS is higher than reference voltage VREF4When, the output signal ZC upsets of comparator U40, logic circuit U12 timing terminates timing signal BLT by step-down high, while releasingCircuit U 03 is not enabled, i.e., leadage circuit does not produce leakage current.T01-t02 is the time t1 that leadage circuit produces power consumption, i.e.,BLT is output as height between t01-t02.Timing signal BLT is connected to the input of time comparison circuitry U14, when t1 is more than TWhen, time comparison circuitry U14 output time delay direction flags BLDIR is high level；Conversely, time delay direction flag BLDIR isLow level.When delay circuit U13 adjusts the time delay after input voltage crossover point signal ZVD according to time delay direction flag BLDIRBetween t2, t1 is adjusted to T or close to T.Wherein time delay t2 minimum values are 0, are half power frequency period or more to the maximum.
With reference to shown in Fig. 7, the circuit structure of logic circuit in leadage circuit embodiment one of the present invention is illustrated.Described patrolsCollecting circuit includes the first trigger U12_1 and the second trigger U12_5, and described time delay module output characterizes whether time delay terminatesStatus signal ZVDLY, the set end S of first trigger receives and described characterizes the status signal whether time delay terminatesZVDLY, the output end of input voltage detection circuit and the output end of time delay module U13 are respectively connected to NAND gate U12_2, it is described withThe output end of not gate U12_2 is connected with the replacement end R of the first trigger U12_1；The output of the first trigger U12_1End be connected after negating with the set end of second trigger, after the output end of drive circuit input electric cur- rent measure circuit is negated andThe replacement end R connections of the second trigger U12_5, the output end and the drive circuit of the second trigger U12_5 is defeatedThe output end for entering current detection circuit connects two inputs with door U12_4 respectively, the output end with door U12_4 and theThe output end of one trigger U12_1 connects two inputs of OR gate U12_3 respectively, and whether the OR gate U12_3 outputs signThe signal EN of enable to the module U03, the timing exported with door U12_4 output end for characterizing the very first time of releasingSignal BLT.Can be that it is replaced although giving a structure for specific logic circuit above, and be not limited toSaid structure.
With reference to shown in Fig. 8, the circuit structure of time comparison module in leadage circuit embodiment one of the present invention is illustrated.LogicEffective time signal B LT controlling switches S14_1, S14_2 of releasing that circuit U 12 is produced, S14_1 conductings, electric current when BLT is highSource I14 is charged to electric capacity C14, and high level signal, time delay plus-minus mark are exported when electric capacity C14 voltages are more than reference voltage V REF14Will signal BLDIR is height, while counter U14_6 is reset, illustrates that delay time needs to lengthen；When BLT is low, S14_2 leadsLogical C14 electric discharges.
T=C14*Vref14/I14；
When the BLT times T is shorter than, the duration, counter U14_6 added counting to produce carry, and U14_5 resets more than T5,BLDIR is low, illustrates that delay time needs to shorten.
T5=TCLK14*2N1
Wherein N1 is the digit of counter U14_6.
With reference to shown in Fig. 9, the circuit structure of time delay module in leadage circuit embodiment one of the present invention is illustrated.Time delay is added and subtractedFlag bit enables signal as the plus-minus counting of counter U13_1, U13_2；CLK13 as counter U13_2 clock signal,Its cycle is the minimum step of time delay；When input voltage zero passage, ZVD signals are high level, and R/S triggers U13-5 outputs are highLevel, until when drive circuit input current flag bit ZC sets to 0, R/S triggers U13-5 outputs reset, and produce ZVDC signals, makeIt is the clock signal of counter U13-1.When time delay plus-minus flag signal BLDDIR is 1, counter U13_1, U13_2 add meterNumber；When time delay plus-minus flag signal BLDDIR is 0, counter U13_1 subtracts counting, counter U13_2 and adds counting.Work as countingWhen device U13_1, U13_2 count value is identical, biconditional gate U13_3 output high level exports high level with door U13_4, and ZVDLY is defeatedGo out high level, as the zero cross signal after ZVD time delays, after through logic circuit U12 produce leadage circuit enable signal.
With reference to shown in Figure 10, the work wave of leadage circuit embodiment one of the present invention is illustrated.Illustrate input voltageVin, input current iin, leakage current iblr, the corresponding specific waveform of enable signal EN and sampled signal RS.By in figureAs can be seen that the leakage current iblr working times are more long in initial power-on, after delay process, the iblr times are shorter and shorter,Until maintain minimum releasing within time T, it is ensured that leadage circuit has relatively low power consumption.
With reference to shown in Figure 11, the circuit structure of leadage circuit embodiment two of the present invention is illustrated.This scheme can be without defeatedEnter voltage vrec detection circuits, can also reach the effect of above scheme, be used to simplify peripheral element, i.e., detect by other meansThe zero crossing of input voltage vrec, but need to increase leakage current iblr detection circuits.
In the present embodiment, described control circuit of releasing includes that drive circuit input electric cur- rent measure circuit, leakage current are examinedSlowdown monitoring circuit and logic circuit U11, described logic circuit U11 are connected with the control end of the module U03 that releases, described drive circuitInput electric cur- rent measure circuit sampling drive circuit input current, and be compared with threshold current, described leakage current detectionWhen input voltage zero passage detection is enabled, module of being released described in the logic circuit control produces leakage current to circuit, and samplesThe leakage current, is sampled by resistance R50, and is compared with threshold value of releasing (being characterized with VREF4)；The drive circuitWhen input current is less than the threshold current VREF4 (Low threshold for being close to zero that the reference signal is characterized), that is, drive electricityRoad input current starts timing, when the leakage current iblr reaches releases threshold value, timing knot close to zero or zero passageBeam, the timing time as the 3rd time T3, again through after the drive circuit input current reaches the threshold currentThe moment of three time T3 judges that input voltage reaches zero crossing.
When judging that input voltage reaches zero crossing, after the second time of time delay t2, released through described in logic circuit U11 controlsModule produces leakage current iblr；Described drive circuit input electric cur- rent measure electric circuit inspection drive circuit input current, when adoptingWhen sample electric current reaches the threshold current for characterizing predetermined value, then it is zero to control leakage current iblr through logic circuit U11；By describedOne time t1 is compared with the reference time T, and second time t2 is correspondingly adjusted according to comparative result.
Described control circuit of releasing also includes time delay module U13, time comparison module U14 and zero passage judge module U15,Described time delay module U13 output end, logic circuit U11 and time comparison module U14 companies respectively with zero passage judge module U15Connect, output ends and drive circuit input electric cur- rent measure of the zero passage judge module U15 respectively with vent discharge current detection circuit are electricThe output end connection on road；Timing is carried out to the 3rd time T3 by the zero passage judge module, and judges the zero crossing of input voltageMoment, described time delay module receives the signal at the sign zero crossing moment of the zero passage judge module output, and time delay secondTime t2, after time delay terminates, controls to produce leakage current iblr, in the time comparison module U14 by logic circuit U11The comparing of very first time t1 and the reference time T is carried out, and it is described to adjust that comparative result is fed back into the time delay moduleSecond time t2.
With reference to shown in Figure 12, the FB(flow block) of the logic circuit U11 of leadage circuit embodiment of the present invention two is illustrated.This accompanying drawingWith reference to Figure 11, the specific implementation step for obtaining embodiment two is：
The initial value of the second time t2 is 0.After AC power is through controllable silicon dimmer U02, rectifier bridge U01, rectification is obtainedVoltage vrec afterwards.Input voltage zero passage detection enables signal CTL is used for the detection of the time of input voltage zero-crossing timing the 3rd, andAnd in order to ensure that the accuracy of the 3rd time reduces power consumption of releasing simultaneously, CTL can be the square-wave signal far below work frequency.During first upper electricity, it is high level that input voltage zero passage detection enables signal CTL, as long as now drive circuit input current sampling electricityResistance R40 voltages RS is less than reference voltage Vref 4, and comparator U40 output ends are high level, and leadage circuit U03 is in and enables workState.When input voltage is higher, LED current is big, and drive circuit sampling resistor R40 voltages are higher than VREF4, comparator U40 outputsLow level, input voltage zero cross signal ZVD is now low level；When input voltage is reduced by height, drive circuit input current is adoptedThe reduction of sample resistance R40 voltages, when drive circuit input current sampling resistor R40 voltages RS is less than VREF4, comparator U40 is defeatedGo out upset, leadage circuit U03 is enabled, and input voltage zero-crossing detection circuit U15 starts timing；Leakage current iblr sampling resistorsR50 voltages are higher than reference voltage V REF5, comparator U50 output low levels；Input voltage continues to reduce, and when close to 0V, releasesElectric current iblr is decreased to close to 0, and leakage current iblr sampling resistor R50 voltages are less than reference voltage V REF5, and comparator U50 is defeatedGo out high level, input voltage crossover point signal ZVD is changed into high level, while input voltage zero-crossing detection circuit U15 counts knotBeam, timing time is T3, as between drive circuit input current iin2 trailing edges zero crossing and input voltage zero crossing whenBetween T3.
When it is low level that input voltage zero passage detection enables signal CTL, each power frequency period afterwards works as drive circuitInput current sampling resistor R40 voltages by becoming less than reference voltage VREF4 higher than reference voltage VREF4 when (on comparator U40Rise edge) time delay T3 generation input voltage crossover point signals ZVD.The high level signal of ZVD is passed through after time delay process U13 time delays t2Logic circuit U11 is crossed, leadage circuit working mark position EN is put 1 by logic circuit U11, and leadage circuit is enabled, busbar voltage vrecIt is pulled down to close to 0V.When the output ZCBLD of leakage current detection comparator U50 is low, i.e. t01 moment in Figure 15, timeComparison circuit U14 starts working.Drive circuit input electric cur- rent measure electric circuit inspection iin2 electric currents, when on current sampling resistor R40When voltage RS is less than reference voltage VREF4, i.e. between t01-t02, leadage circuit U03 continues to enable.When voltage RS is higher than referenceDuring voltage VREF4, the output signal ZC upsets of comparator U40, time comparison circuitry U14 end-of-jobs, while leadage circuit U03Do not enable, i.e., leadage circuit does not produce leakage current.The time t1 that leadage circuit produces power consumption is from t01-t02, when t1 is bigWhen T, time comparison circuitry output time delay direction flag BLDIR is high level；Conversely, time delay direction flag BLDIR isLow level.When delay circuit U13 adjusts the time delay after input voltage crossover point signal ZVD according to time delay direction flag BLDIRBetween t2, t1 is adjusted to T or close to T.Wherein time delay t2 minimum values are 0, are half power frequency period or more to the maximum.With reference to Figure 13It is shown, illustrate the circuit structure of logic circuit in leadage circuit embodiment two of the present invention.When input voltage zero-crossing examination makesWhen energy signal CTL is high level, as long as drive circuit input current iin2 is high level less than setting value, i.e. ZC, with doorU11_6 is output as high level, and three input OR gate U11_3 output high level, leadage circuit is enabled, input voltage zero-crossing examination electricityRoad U15 detects input voltage zero crossing, 0-t07 in such as Figure 15, and holding time T3.Believe when input voltage zero-crossing examination is enabledWhen number CTL is low level, low level is output as with door U11_6.When drive circuit input current iin2 detects circuit ZC by low electricityWhen flat upset is for high level (t03), delay time T3, ZVD signal is changed into high level from low level, even if now ZC is electricity highIt is flat, but R/S triggers U11_1 (the t01 moment resets), U11_5 (the t02 moment resets) output low level, it is output as with door U11_4Low level, leadage circuit is not enabled.When delay circuit U13 output signals ZVDLY puts 1, R/S triggers U11_1 is output asHigh level, it is high level that leadage circuit enables signal EN, and leadage circuit is enabled, and input voltage vrec is 0, until controllable silicon light modulationDevice is turned on, and ZVD is low, R/S triggers U11_1 output low levels, U11_5 output high level, if now ZC is height, with doorU11_4 exports high level, and leadage circuit enables signal EN and continues as high level, is used to maintain input current to ensure the steady of controllable siliconFixed conducting；Until when ZC is low, U11_4, U11_5 output reset, it is low, leadage circuit stopping work that leadage circuit enables signal ENMake.The time signal B LT (t01~t02) that leadage circuit produces power consumption is with door U11_4 outputs.
With reference to shown in Figure 14, the flow of zero passage judge module U15 work in leadage circuit embodiment two of the present invention is illustratedBlock diagram.Drive circuit input current iin2 zero crossings and leakage current iblr mistakes are detected and preserved by zero passage judge module U15Zero crossing time.In the case where zero passage judge module U15 is enabled, whether drive circuit input current is judged less than threshold current,When it is less than threshold current, then module of releasing is enabled and produces leakage current.When leakage current is less than respective threshold, then preserveThe moment, update the 3rd time T3.The 3rd time T3 be from ZC by step-down high to ZCBLD by step-down high time.
With reference to shown in Figure 15, the work wave of leadage circuit embodiment two of the present invention is illustrated.Illustrate input voltageVin, input current iin, leakage current iblr, the corresponding specific waveform of enable signal EN, CTL and sampled signal RS.ByAs can be seen that similar to embodiment one in figure, in initial power-on, the leakage current iblr working times are more long, through delay processAfterwards, the iblr times are shorter and shorter, until maintain minimum releasing within time T, it is ensured that leadage circuit has relatively low power consumption.
In addition, although embodiment is separately illustrated and illustrated above, but it is related to the common technology in part, in this areaThose of ordinary skill apparently, can between the embodiments be replaced and integrate, and be related to one of embodiment that record is not knownContent, then refer to another embodiment on the books.
Embodiments described above, does not constitute the restriction to the technical scheme protection domain.It is any in above-mentioned implementationModification, equivalent and improvement made within the spirit and principle of mode etc., should be included in the protection model of the technical schemeWithin enclosing.