技术领域technical field
本发明涉及半导体器件领域，尤其涉及一种绝缘栅双极型晶体管器件及其制造方法。The invention relates to the field of semiconductor devices, in particular to an insulated gate bipolar transistor device and a manufacturing method thereof.
背景技术Background technique
以IGBT、MOSFET为标志的MOS型半导体功率器件是当今电力电子领域器件的主流，其中最具代表性的器件IGBT(Insulated Gate Bipolar Transistor)，又称绝缘栅双极型晶体管，是由BJT(双极型三极管)和MOS(绝缘栅型场效应管)组成的复合全控型电压驱动式功率半导体器件，驱动功率小，兼有金属-氧化物半导体场效应晶体管MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)的高输入阻抗和电力晶体管(PowerBJT)的低导通压降两方面的优点，非常适合应用于直流电压为600V及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。其作为新型电力电子器件的典型代表，在中、高压应用领域中备受青睐。根据IGBT的技术分类，通常划分为PT-IGBT(穿通型)、NPT-IGBT(非穿通型)、FS-IGBT(场截止型)、RC-IGBT(逆导型)等结构，主要体现在耐压层的结构变化和器件集电极的结构和制造方法差异。MOS type semiconductor power devices marked by IGBT and MOSFET are the mainstream of devices in the field of power electronics today. Among them, the most representative device IGBT (Insulated Gate Bipolar Transistor), also known as insulated gate bipolar transistor, is made of BJT (bipolar Pole type triode) and MOS (insulated gate field effect transistor) composite fully-controlled voltage-driven power semiconductor device, the drive power is small, and it also has a metal-oxide semiconductor field-effect transistor MOSFET (Metal-Oxide-Semiconductor Field- The advantages of high input impedance of Effect Transistor and low conduction voltage drop of power transistor (PowerBJT) are very suitable for DC voltage conversion systems of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits , traction transmission and other fields. As a typical representative of new power electronic devices, it is favored in medium and high voltage applications. According to the technical classification of IGBT, it is usually divided into structures such as PT-IGBT (punch-through type), NPT-IGBT (non-punch-through type), FS-IGBT (field-stop type), RC-IGBT (reverse conduction type), etc. Structural variations of the laminate and differences in the structure and fabrication method of the device collector.
由于IGBT器件是从MOSFET功率器件的结构发展而来(在背面整合一个PNP晶体管)，所以其MOSFET部分的结构和制造方法基本类似于MOSFET器件。但由于受到制造工艺的影响，采用正常的光刻对准工艺，600V高压沟槽栅IGBT的元胞大小一般在3um以上，使器件单位面积的电流密度提升受到限制。Since the IGBT device is developed from the structure of the MOSFET power device (integrating a PNP transistor on the back), the structure and manufacturing method of the MOSFET part are basically similar to the MOSFET device. However, due to the influence of the manufacturing process, the cell size of the 600V high-voltage trench gate IGBT is generally above 3um by using the normal photolithographic alignment process, which limits the improvement of the current density per unit area of the device.
综上，需要提出一种能够缩小元胞尺寸，以提高单位面积电流密度的IGBT器件结构及制造方案。To sum up, it is necessary to propose an IGBT device structure and manufacturing scheme that can reduce the cell size to increase the current density per unit area.
发明内容Contents of the invention
有鉴于此，本发明提供一种绝缘栅双极型晶体管器件及其制造方法，能缩小元胞结构尺寸，提高单位面积的电流密度。In view of this, the present invention provides an insulated gate bipolar transistor device and a manufacturing method thereof, which can reduce the size of the cell structure and increase the current density per unit area.
根据本发明的第一方面，提供一种绝缘栅双极型晶体管器件，所述器件的正面结构包括：N型衬底正面的多个沟槽以及填充在所述多个沟槽内的多个沟槽多晶硅栅结构；所述多个沟槽多晶硅栅结构上方的氧化层介质膜层及其两侧的侧墙结构；分别位于所述多个沟槽多晶硅栅结构中、相邻的沟槽多晶硅栅结构之间的多个接触孔；位于所述多个接触孔两侧、且在所述侧墙结构下方的N型掺杂发射极区；所述多个接触孔底部的P型注入区；填充在所述多个接触孔中的钨塞填充结构；所述氧化层介质膜层及其两侧的侧墙结构上覆盖的正面金属层；以及所述正面金属层上方的表面钝化层。According to the first aspect of the present invention, there is provided an insulated gate bipolar transistor device, the front structure of the device includes: a plurality of trenches on the front side of an N-type substrate and a plurality of trenches filled in the plurality of trenches. Trench polysilicon gate structure; an oxide dielectric film layer above the plurality of trench polysilicon gate structures and sidewall structures on both sides; respectively located in the plurality of trench polysilicon gate structures, adjacent trench polysilicon A plurality of contact holes between the gate structures; an N-type doped emitter region located on both sides of the plurality of contact holes and below the sidewall structure; a P-type implantation region at the bottom of the plurality of contact holes; A tungsten plug filling structure filled in the plurality of contact holes; a front metal layer covered on the oxide dielectric film layer and side wall structures on both sides; and a surface passivation layer above the front metal layer.
进一步地，所述绝缘栅双极型晶体管器件为场截止型/穿通型/非穿通型/逆导型绝缘栅双极型晶体管器件。Further, the insulated gate bipolar transistor device is a field stop type/punch through type/non-punch through type/reverse conduction type insulated gate bipolar transistor device.
根据本发明第二方面，提供一种绝缘栅双极型晶体管器件的制造方法，包括：在N型衬底上热生长垫氧化层，作为沟槽刻蚀的掩蔽层的缓冲层；在所述垫氧化层上沉积一层氮化硅膜层，并利用沟槽光刻板刻蚀所述氮化硅膜层，形成沟槽刻蚀的掩蔽层；基于所述掩蔽层进行沟槽刻蚀，形成多个沟槽；在所述多个沟槽中生成多个沟槽多晶硅栅结构；沉积氧化层介质膜层，并对所述氧化层介质膜层和所述掩蔽层进行刻蚀，保留所述多个沟槽多晶硅栅结构上方的氧化层介质膜层，形成多个离子注入窗口；通过所述多个离子注入窗口进行离子注入，形成PN结和N型掺杂发射极区；在所述多个沟槽多晶硅栅结构上方的氧化层介质膜层两侧形成侧墙结构，以基于所述侧墙结构自对准地刻蚀形成多个接触孔；在所述多个接触孔处进行离子注入和退火激活，形成P型注入区；在所述多个接触孔中填充金属钨，形成钨塞填充结构；形成正面金属层，在金属层上生成表面钝化层，并刻蚀形成正面发射极封装窗口；进行背面结构的制作。According to the second aspect of the present invention, there is provided a method for manufacturing an insulated gate bipolar transistor device, comprising: thermally growing a pad oxide layer on an N-type substrate as a buffer layer for a trench etching masking layer; A layer of silicon nitride film is deposited on the pad oxide layer, and the silicon nitride film layer is etched with a trench photolithography plate to form a masking layer for trench etching; trench etching is performed based on the masking layer to form A plurality of trenches; generating a plurality of trench polysilicon gate structures in the plurality of trenches; depositing an oxide dielectric film layer, and etching the oxide dielectric film layer and the masking layer, and retaining the The dielectric film layer of the oxide layer above the plurality of trench polysilicon gate structures forms a plurality of ion implantation windows; ion implantation is performed through the plurality of ion implantation windows to form a PN junction and an N-type doped emitter region; in the plurality of ion implantation windows Form sidewall structures on both sides of the oxide layer dielectric film above the trench polysilicon gate structure, so as to form a plurality of contact holes by self-aligned etching based on the sidewall structures; perform ion implantation at the plurality of contact holes and annealing activation to form a P-type implant region; filling metal tungsten in the plurality of contact holes to form a tungsten plug filling structure; forming a front metal layer, generating a surface passivation layer on the metal layer, and etching to form a front emitter Encapsulate the window; make the back structure.
进一步地，在所述多个沟槽中生成多个沟槽多晶硅栅结构，包括：在所述多个沟槽表面热生长栅氧化介质层；在所述多个沟槽的栅氧化介质层上沉积多晶硅；对所述多晶硅进行刻蚀，形成沟槽多晶硅栅结构。Further, generating a plurality of trench polysilicon gate structures in the plurality of trenches includes: thermally growing a gate oxide dielectric layer on the surface of the plurality of trenches; Depositing polysilicon; etching the polysilicon to form a trench polysilicon gate structure.
进一步地，对所述氧化层介质膜层和所述掩蔽层进行刻蚀，保留所述多个沟槽多晶硅栅结构上方的氧化层介质膜层，形成多个离子注入窗口，包括：刻蚀去除所述掩蔽层上方的氧化层介质膜层，保留所述多个沟槽多晶硅栅结构上方的氧化层介质膜层；刻蚀去除所述掩蔽层，在保留的所述多个沟槽多晶硅栅结构上方的氧化层介质膜层之间形成多个离子注入窗口。Further, etching the dielectric film layer of the oxide layer and the masking layer, retaining the dielectric film layer of the oxide layer above the plurality of trench polysilicon gate structures, forming a plurality of ion implantation windows, including: etching and removing The dielectric film layer of the oxide layer above the masking layer, the dielectric film layer of the oxide layer above the plurality of trench polysilicon gate structures is retained; the masking layer is removed by etching, and the remaining plurality of trench polysilicon gate structures Multiple ion implantation windows are formed between the upper oxide dielectric film layers.
进一步地，在所述多个沟槽多晶硅栅结构上方的氧化层介质膜层两侧形成侧墙结构，以基于所述侧墙结构自对准地刻蚀形成多个接触孔，包括：沉积一层侧墙氧化层膜层；对所述侧墙氧化层膜层进行刻蚀，保留所述多个沟槽多晶硅栅结构上方的氧化层介质膜层两侧的侧墙氧化层，形成侧墙结构；基于相邻两个沟槽多晶硅栅结构上方的氧化层介质膜层的侧墙之间形成的接触孔窗口进行接触孔刻蚀，形成多个接触孔。Further, forming sidewall structures on both sides of the oxide layer dielectric film above the plurality of trench polysilicon gate structures, so as to form a plurality of contact holes by self-aligned etching based on the sidewall structures, including: depositing a A sidewall oxide film layer; etching the sidewall oxide film layer, retaining the sidewall oxide layers on both sides of the oxide layer dielectric film layer above the plurality of trench polysilicon gate structures, forming a sidewall structure ; Etching the contact holes based on the contact hole windows formed between the sidewalls of the oxide layer dielectric film layer above the two adjacent trench polysilicon gate structures to form a plurality of contact holes.
进一步地，所述绝缘栅双极型晶体管器件为场截止型/穿通型/非穿通型/逆导型绝缘栅双极型晶体管器件。Further, the insulated gate bipolar transistor device is a field stop type/punch through type/non-punch through type/reverse conduction type insulated gate bipolar transistor device.
根据本发明的上述方案，通过沉积侧墙氧化层并刻蚀形成侧墙结构，并进行接触孔刻蚀，能够通过控制侧墙氧化层的厚度和等离子刻蚀量来调整侧墙厚度，从而，控制接触孔到沟槽的间距以及接触孔的尺寸，实现了接触孔对沟槽多晶硅栅结构的自对准。本发明能缩小器件元胞结构的尺寸，提高元胞密度，从而提高单位面积的电流密度，降低芯片成本，提高性价比。According to the above solution of the present invention, by depositing the side wall oxide layer and etching to form the side wall structure, and performing contact hole etching, the thickness of the side wall can be adjusted by controlling the thickness of the side wall oxide layer and the amount of plasma etching, thereby, Controlling the distance from the contact hole to the trench and the size of the contact hole realizes the self-alignment of the contact hole to the trench polysilicon gate structure. The invention can reduce the size of the cell structure of the device, increase the cell density, thereby increase the current density per unit area, reduce the cost of the chip, and improve the cost performance.
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，并可依照说明书的内容予以实施，以下以本发明的较佳实施例并配合附图详细说明如后。The above description is only an overview of the technical solutions of the present invention. In order to understand the technical means of the present invention more clearly and implement them according to the contents of the description, the preferred embodiments of the present invention and accompanying drawings are described in detail below.
附图说明Description of drawings
构成本发明的一部分的附图用来提供对本发明的进一步理解，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：The drawings constituting a part of the present invention are used to provide a further understanding of the present invention, and the schematic embodiments and descriptions of the present invention are used to explain the present invention, and do not constitute an improper limitation of the present invention. In the attached picture:
图1示出了根据本发明一个实施例的绝缘栅双极型晶体管器件的正面结构示意图。Fig. 1 shows a schematic diagram of the front structure of an IGBT device according to an embodiment of the present invention.
图2示出了根据本发明一个实施例的绝缘栅双极型晶体管的制造方法的流程图。FIG. 2 shows a flowchart of a method for manufacturing an IGBT according to an embodiment of the present invention.
图3示出了根据本发明一个实施例的在衬底上生长垫氧化层和氮化硅膜层后的结构示意图。FIG. 3 shows a schematic diagram of the structure after growing a pad oxide layer and a silicon nitride film layer on a substrate according to an embodiment of the present invention.
图4示出了根据本发明一个实施例的对氮化硅膜层进行光刻后形成沟槽刻蚀的掩蔽层的结构示意图。FIG. 4 shows a schematic structural view of a trench-etched masking layer formed after performing photolithography on a silicon nitride film layer according to an embodiment of the present invention.
图5示出了根据本发明一个实施例的进行沟槽刻蚀形成多个沟槽后的结构示意图。FIG. 5 shows a schematic structural diagram after trench etching is performed to form multiple trenches according to an embodiment of the present invention.
图6示出了根据本发明一个实施例的在多个沟槽表面生成栅氧化介质层后的结构示意图。FIG. 6 shows a schematic structural diagram after gate oxide dielectric layers are formed on the surfaces of multiple trenches according to an embodiment of the present invention.
图7示出了根据本发明一个实施例的形成沟槽多晶硅栅结构的结构示意图。FIG. 7 shows a schematic structural diagram of forming a trench polysilicon gate structure according to an embodiment of the present invention.
图8示出了根据本发明一个实施例的沉积了氧化层介质膜层之后的结构示意图。FIG. 8 shows a schematic diagram of the structure after deposition of an oxide dielectric film layer according to an embodiment of the present invention.
图9示出了根据本发明一个实施例的刻蚀去除掩蔽层上方的氧化层介质膜层后的结构示意图。FIG. 9 shows a schematic view of the structure after etching and removing the dielectric film layer of the oxide layer above the masking layer according to an embodiment of the present invention.
图10示出了根据本发明一个实施例的刻蚀去除掩蔽层后的结构示意图。FIG. 10 shows a schematic diagram of the structure after etching and removing the masking layer according to an embodiment of the present invention.
图11示出了根据本发明一个实施例的形成PN结之后的结构示意图。FIG. 11 shows a schematic diagram of the structure after the PN junction is formed according to an embodiment of the present invention.
图12示出了根据本发明一个实施例的N+发射极离子注入后形成N型掺杂发射极区后的结构示意图。FIG. 12 shows a schematic structural diagram of forming an N-type doped emitter region after N+ emitter ion implantation according to an embodiment of the present invention.
图13示出了根据本发明一个实施例的沉积一层侧墙氧化层膜层后的结构示意图。FIG. 13 shows a schematic view of the structure after depositing a layer of sidewall oxide film according to an embodiment of the present invention.
图14示出了根据本发明一个实施例的形成侧墙后的结构示意图。Fig. 14 shows a schematic diagram of the structure after forming side walls according to an embodiment of the present invention.
图15示出了根据本发明一个实施例的离子注入和退火激活形成P型注入区后的结构示意图。FIG. 15 shows a schematic diagram of the structure after ion implantation and annealing activation to form a P-type implantation region according to an embodiment of the present invention.
图16示出了根据本发明一个实施例的形成钨塞填充结构后的结构示意图。FIG. 16 shows a schematic view of the structure after the tungsten plug filling structure is formed according to an embodiment of the present invention.
图17示出了根据本发明一个实施例的形成正面金属层后的结构示意图。FIG. 17 shows a schematic view of the structure after forming the front metal layer according to an embodiment of the present invention.
图18示出了根据本发明一个具体实施例的场截止型绝缘栅双极型晶体管的结构示意图。FIG. 18 shows a schematic structural diagram of a field stop IGBT transistor according to a specific embodiment of the present invention.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明具体实施例及相应的附图对本发明技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and corresponding drawings. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
以下结合附图说明本发明的绝缘栅双极型晶体管器件。The IGBT device of the present invention will be described below with reference to the accompanying drawings.
图1示出了根据本发明一个实施例的绝缘栅双极型晶体管器件的正面结构示意图。Fig. 1 shows a schematic diagram of the front structure of an IGBT device according to an embodiment of the present invention.
如图1所示，所述绝缘栅双极型晶体管器件(简称IGBT器件)为沟槽型IGBT器件，该器件的正面结构包括：N型衬底正面的多个沟槽104以及填充在所述多个沟槽104内的多个沟槽多晶硅栅结构106；沟槽104表面(底部及侧壁)与沟槽多晶硅栅结构之间为栅氧化介质层105；所述多个沟槽多晶硅栅结构106上方的氧化层介质膜层107及其两侧的侧墙结构112；相邻沟槽之间的PN结109；分别位于所述多个沟槽多晶硅栅结构中、相邻的沟槽多晶硅栅结构之间的多个接触孔114；位于所述多个接触孔两侧、且在所述侧墙结构下方的N型掺杂发射极区110；所述多个接触孔底部的P型注入区115；填充在所述多个接触孔114中的钨塞填充结构116；所述氧化层介质膜层107及其两侧的侧墙结构112上覆盖的正面金属层117；以及所述正面金属层上方的表面钝化层118。As shown in Figure 1, the insulated gate bipolar transistor device (IGBT device for short) is a trench type IGBT device, and the front structure of the device includes: a plurality of trenches 104 on the front side of the N-type substrate and filled in the A plurality of trench polysilicon gate structures 106 in the plurality of trenches 104; a gate oxide dielectric layer 105 is between the surface (bottom and sidewall) of the trench 104 and the trench polysilicon gate structure; the plurality of trench polysilicon gate structures The oxide dielectric film layer 107 above 106 and the sidewall structures 112 on both sides; the PN junction 109 between adjacent trenches; the adjacent trench polysilicon gate structures respectively located in the plurality of trench polysilicon gate structures A plurality of contact holes 114 between the structures; an N-type doped emitter region 110 located on both sides of the plurality of contact holes and below the sidewall structure; a P-type implant region at the bottom of the plurality of contact holes 115; the tungsten plug filling structure 116 filled in the plurality of contact holes 114; the front metal layer 117 covered on the oxide layer dielectric film layer 107 and the side wall structures 112 on both sides; and the front metal layer surface passivation layer 118 above.
所述多个沟槽多晶硅栅结构106上方的氧化层介质膜层107两侧的侧墙结构112是通过在氧化层介质膜层上沉积侧墙氧化层并进行等离子刻蚀形成的，可用于自对准地刻蚀形成所述多个接触孔114，并且可以通过不同尺寸的侧墙宽度(侧墙氧化层厚度)调整接触孔114到沟槽114的间距和接触孔114的尺寸。器件的元胞区域由侧墙112和氧化层介质膜层107形成介质结构，达到接触孔对沟槽多晶硅栅结构的自对准效果。通过控制侧墙氧化层的厚度，可将接触孔到沟槽的间距缩小到0.1μm以下，元胞结构的尺寸可以缩小到2μm以下。The sidewall structures 112 on both sides of the oxide dielectric film layer 107 above the plurality of trench polysilicon gate structures 106 are formed by depositing a sidewall oxide layer on the oxide dielectric film layer and performing plasma etching, which can be used for self- The plurality of contact holes 114 are formed by aligned etching, and the distance from the contact hole 114 to the trench 114 and the size of the contact hole 114 can be adjusted through different sidewall widths (sidewall oxide layer thickness). In the cell area of the device, a dielectric structure is formed by the side wall 112 and the oxide dielectric film layer 107, so as to achieve the self-alignment effect of the contact hole on the trench polysilicon gate structure. By controlling the thickness of the sidewall oxide layer, the distance between the contact hole and the trench can be reduced to less than 0.1 μm, and the size of the cell structure can be reduced to less than 2 μm.
所述绝缘栅双极型晶体管器件具体可以为场截止型/穿通型/非穿通型/逆导型绝缘栅双极型晶体管器件。The insulated gate bipolar transistor device may specifically be a field stop type/punch through type/non-punch through type/reverse conduction type insulated gate bipolar transistor device.
图2示出了根据本发明一个实施例的绝缘栅双极型晶体管器件的制造方法的流程图。FIG. 2 shows a flowchart of a method for manufacturing an IGBT device according to an embodiment of the present invention.
如图2所示，所述绝缘栅双极型晶体管器件的制造方法，包括以下步骤：As shown in Figure 2, the manufacturing method of the IGBT device includes the following steps:
步骤S1、在N型衬底101上热生长垫氧化层102。Step S1 , thermally growing a pad oxide layer 102 on the N-type substrate 101 .
根据器件所需的电压规格等参数要求，结合理论及仿真的数据，选取合适的衬底材料规格(如电阻率、外延层厚度或FZ-wafer的最终减薄厚度)，如果对应为场截止型(field-stop)和穿通型(punch through)等IGBT器件结构，还需确认场截止层的规格。例如，该衬底可以为N型掺杂外延硅片衬底或N型单晶硅片衬底。According to the parameter requirements such as the voltage specification required by the device, combined with the theoretical and simulated data, select the appropriate substrate material specification (such as resistivity, epitaxial layer thickness or final thinning thickness of FZ-wafer), if the corresponding field stop type (field-stop) and punch through (punch through) and other IGBT device structures, it is also necessary to confirm the specifications of the field stop layer. For example, the substrate may be an N-type doped epitaxial silicon substrate or an N-type single crystal silicon substrate.
步骤S2、在所述垫氧化层102上沉积一层氮化硅膜层103a，并利用沟槽光刻板刻蚀所述氮化硅膜层，形成沟槽刻蚀的掩蔽层103b。Step S2, depositing a silicon nitride film layer 103a on the pad oxide layer 102, and etching the silicon nitride film layer by using a trench photolithography plate to form a trench-etched masking layer 103b.
图3示出了根据本发明一个实施例的在衬底上生长垫氧化层和氮化硅膜层后的结构示意图。图4示出了根据本发明一个实施例的对氮化硅膜层进行光刻后形成沟槽刻蚀的掩蔽层的结构示意图。FIG. 3 shows a schematic diagram of the structure after growing a pad oxide layer and a silicon nitride film layer on a substrate according to an embodiment of the present invention. FIG. 4 shows a schematic structural view of a trench-etched masking layer formed after performing photolithography on a silicon nitride film layer according to an embodiment of the present invention.
如图3所示，在所述N型衬底101正面热生长一层垫氧化层102(Pad Oxide)，作为沟槽刻蚀的掩蔽层的缓冲层。在垫氧化层上102再沉积一层氮化硅(Nitride)膜层103a。如图4所示，利用沟槽光刻板对该氮化硅膜层进行光刻，形成沟槽图形，使之形成进行沟槽刻蚀的掩蔽层103b。As shown in FIG. 3 , a pad oxide layer 102 (Pad Oxide) is thermally grown on the front side of the N-type substrate 101 as a buffer layer for the masking layer for trench etching. A silicon nitride (Nitride) film layer 103 a is then deposited on the pad oxide layer 102 . As shown in FIG. 4 , the silicon nitride film layer is photoetched by using a trench photolithography plate to form a trench pattern to form a masking layer 103b for trench etching.
步骤S3、基于所述掩蔽层103b进行沟槽刻蚀，形成多个沟槽104。Step S3 , performing trench etching based on the masking layer 103 b to form a plurality of trenches 104 .
图5示出了根据本发明一个实施例的进行沟槽刻蚀形成多个沟槽后的结构示意图。形成掩蔽层103b之后，根据该掩蔽层103b进行沟槽刻蚀，如图5所示，刻蚀形成多个沟槽104。FIG. 5 shows a schematic structural diagram after trench etching is performed to form multiple trenches according to an embodiment of the present invention. After the masking layer 103b is formed, trench etching is performed according to the masking layer 103b , as shown in FIG. 5 , a plurality of trenches 104 are formed by etching.
步骤S4、在所述多个沟槽104中生成多个沟槽多晶硅栅结构106。Step S4 , generating a plurality of trench polysilicon gate structures 106 in the plurality of trenches 104 .
进一步地，步骤S4包括步骤S41、S42和S43。Further, step S4 includes steps S41, S42 and S43.
步骤S41、在所述多个沟槽104表面热生长栅氧化介质层105。Step S41 , thermally growing a gate oxide dielectric layer 105 on the surface of the plurality of trenches 104 .
图6示出了根据本发明一个实施例的在多个沟槽表面生成栅氧化介质层的结构示意图。如图6所示，形成多个沟槽104后，在经过沟槽圆角化等步骤后，在沟槽104表面(底部及侧壁)上热生长一层栅氧化介质层105(Gate Oxide)。FIG. 6 shows a schematic structural view of forming gate oxide dielectric layers on the surfaces of multiple trenches according to an embodiment of the present invention. As shown in FIG. 6, after forming a plurality of trenches 104, after steps such as trench filleting, a layer of gate oxide dielectric layer 105 (Gate Oxide) is thermally grown on the surface (bottom and sidewall) of the trenches 104. .
步骤S42、在所述多个沟槽104的栅氧化介质层105上沉积多晶硅。Step S42 , depositing polysilicon on the gate oxide dielectric layer 105 of the plurality of trenches 104 .
其中，可以采用化学气相沉积在多个沟槽104中沉积多晶硅。Wherein, chemical vapor deposition may be used to deposit polysilicon in the plurality of trenches 104 .
步骤S43、对所述多晶硅进行刻蚀，形成沟槽多晶硅栅结构106。Step S43 , etching the polysilicon to form a trench polysilicon gate structure 106 .
图7示出了根据本发明一个实施例的形成沟槽多晶硅栅结构的结构示意图。采用等离子刻蚀工艺，对沟槽104内的多晶硅进行刻蚀，形成如图7所示的沟槽多晶硅栅结构106(trench poly)。FIG. 7 shows a schematic structural diagram of forming a trench polysilicon gate structure according to an embodiment of the present invention. The polysilicon in the trench 104 is etched using a plasma etching process to form a trench polysilicon gate structure 106 (trench poly) as shown in FIG. 7 .
步骤S5、沉积氧化层介质膜层107，并对所述氧化层介质膜层107和所述掩蔽层103b进行刻蚀。Step S5, depositing the oxide dielectric film layer 107, and etching the oxide dielectric film layer 107 and the masking layer 103b.
步骤S5具体可以包括步骤S51、S52和S53；Step S5 may specifically include steps S51, S52 and S53;
步骤S51、沉积氧化层介质膜层107。Step S51 , depositing an oxide dielectric film layer 107 .
图8示出了根据本发明一个实施例的沉积了氧化层介质膜层之后的结构示意图。采用化学气相沉积工艺，在已经形成的结构上再沉积一层氧化层介质膜层107。FIG. 8 shows a schematic diagram of the structure after deposition of an oxide dielectric film layer according to an embodiment of the present invention. A chemical vapor deposition process is used to deposit an oxide dielectric film layer 107 on the formed structure.
步骤S52、刻蚀去除所述掩蔽层103b上方的氧化层介质膜层107，保留所述多个沟槽多晶硅栅结构上方的氧化层介质膜层107。Step S52, etching and removing the oxide dielectric film layer 107 above the masking layer 103b, and retaining the oxide dielectric film layer 107 above the plurality of trench polysilicon gate structures.
图9示出了根据本发明一个实施例的刻蚀去除掩蔽层上方的氧化层介质膜层后的结构示意图。采用等离子刻蚀工艺，刻蚀掉氮化硅掩蔽层103b上方的氧化层介质膜层，保留所述多个沟槽多晶硅栅结构106上方的氧化层介质膜层107，即，刻蚀停止在氮化硅掩蔽层103b，如图9所示。FIG. 9 shows a schematic view of the structure after etching and removing the dielectric film layer of the oxide layer above the masking layer according to an embodiment of the present invention. Using a plasma etching process, etch away the oxide layer dielectric film layer above the silicon nitride masking layer 103b, and retain the oxide layer dielectric film layer 107 above the plurality of trench polysilicon gate structures 106, that is, the etching stops at nitrogen SiO masking layer 103b, as shown in FIG. 9 .
步骤S53、刻蚀去除所述掩蔽层103b。Step S53, etching and removing the masking layer 103b.
图10示出了根据本发明一个实施例的刻蚀去除掩蔽层后的结构示意图。采用湿法刻蚀工艺，刻蚀去除氮化硅掩蔽层103b，为后续的离子注入等打开窗口，如图10所示，在保留的多个沟槽多晶硅栅结构106上方的氧化层介质膜层107之间形成多个离子注入窗口108。FIG. 10 shows a schematic diagram of the structure after etching and removing the masking layer according to an embodiment of the present invention. Wet etching process is used to etch and remove the silicon nitride masking layer 103b to open windows for subsequent ion implantation, etc., as shown in FIG. A plurality of ion implantation windows 108 are formed between 107 .
步骤S6、进行离子注入，形成PN结和N型掺杂发射极区；Step S6, performing ion implantation to form a PN junction and an N-type doped emitter region;
图11示出了根据本发明一个实施例的形成PN结之后的结构示意图。图12示出了根据本发明一个实施例的N+发射极离子注入后形成N型掺杂发射极区后的结构示意图。FIG. 11 shows a schematic diagram of the structure after the PN junction is formed according to an embodiment of the present invention. FIG. 12 shows a schematic structural diagram of forming an N-type doped emitter region after N+ emitter ion implantation according to an embodiment of the present invention.
如图11所示，通过多个离子注入窗口108，采用整片离子注入和扩散推阱工艺，形成PN结109从而形成P阱(PN结上方相邻两个沟槽多晶硅栅结构之间的区域)，其中，注入的离子为硼(Boron)离子。如图12所示，通过多个离子注入窗口108进行N+发射极离子注入和扩散退火，形成N型掺杂发射极区110，即，通过多个离子注入窗口108在多个沟槽之间注入N+离子，形成N型掺杂发射极区110，其中，注入的N+离子为砷(arsenic)离子。As shown in FIG. 11, through a plurality of ion implantation windows 108, a whole-chip ion implantation and diffusion push well process are used to form a PN junction 109 to form a P well (the area between two adjacent trench polysilicon gate structures above the PN junction) ), wherein the implanted ions are boron (Boron) ions. As shown in FIG. 12, N+ emitter ion implantation and diffusion annealing are performed through a plurality of ion implantation windows 108 to form an N-type doped emitter region 110, that is, implantation between a plurality of trenches through a plurality of ion implantation windows 108 N+ ions to form an N-type doped emitter region 110 , wherein the implanted N+ ions are arsenic (arsenic) ions.
步骤S7、在所述多个沟槽多晶硅栅结构106上方的氧化层介质膜层107两侧形成侧墙结构112，以基于所述侧墙结构自对准地刻蚀形成多个接触孔。Step S7 , forming sidewall structures 112 on both sides of the oxide dielectric film layer 107 above the plurality of trench polysilicon gate structures 106 , so as to form a plurality of contact holes by self-aligned etching based on the sidewall structures.
进一步地，步骤S7具体可以包括步骤S71、S72和S73。Further, step S7 may specifically include steps S71, S72 and S73.
步骤S71、沉积一层侧墙氧化层膜层111。Step S71 , depositing a sidewall oxide layer 111 .
图13示出了根据本发明一个实施例的沉积侧墙氧化层膜层后的结构示意图。采用化学气相沉积，沉积一层侧墙氧化层(Space oxide)膜层111。FIG. 13 shows a schematic diagram of the structure after depositing a sidewall oxide layer according to an embodiment of the present invention. A space oxide film layer 111 is deposited by chemical vapor deposition.
步骤S72、对所述侧墙氧化层膜层111进行刻蚀，保留所述多个沟槽多晶硅栅结构106上方的氧化层介质膜层107两侧的侧墙氧化层，形成侧墙结构112。Step S72 , etching the sidewall oxide layer 111 , retaining the sidewall oxide layers on both sides of the oxide dielectric film layer 107 above the plurality of trench polysilicon gate structures 106 to form sidewall structures 112 .
图14示出了根据本发明一个实施例的形成侧墙结构后的结构示意图。如图14所示，对侧墙氧化层111进行等离子刻蚀，仅保留在多个沟槽多晶硅栅结构107上方的氧化层介质膜层107两侧的侧墙氧化层膜层111，形成侧墙(Sidewall)结构112。Fig. 14 shows a schematic structural diagram of a side wall structure formed according to an embodiment of the present invention. As shown in FIG. 14, the sidewall oxide layer 111 is plasma etched, and only the sidewall oxide layer 111 on both sides of the oxide layer dielectric film layer 107 above the plurality of trench polysilicon gate structures 107 is retained to form a sidewall (Sidewall) structure 112.
步骤S73、基于相邻两个沟槽多晶硅栅结构106上方的氧化层介质膜层107的侧墙112之间形成的接触孔窗口113进行接触孔刻蚀，形成多个接触孔。Step S73 , performing contact hole etching based on the contact hole windows 113 formed between the sidewalls 112 of the oxide dielectric film layer 107 above two adjacent trench polysilicon gate structures 106 to form a plurality of contact holes.
具体地，采用等离子刻蚀工艺进行接触孔刻蚀，形成多个接触孔114。Specifically, a plasma etching process is used to etch the contact holes to form a plurality of contact holes 114 .
上述步骤自准对地形成了N+发射极的接触孔窗口，通过调整侧墙氧化层111的厚度和等离子刻蚀量，可以得到不同尺寸的侧墙宽度，从而决定了接触孔114到沟槽114的间距和接触孔114的尺寸。器件的元胞区域不需要光刻图形，而是由侧墙氧化层111和氧化层介质膜层107所形成的介质结构，达到接触孔对沟槽多晶硅栅结构的自对准效果。通过控制侧墙氧化层的厚度，可将接触孔到沟槽的间距缩小到0.1μm以下，元胞结构的尺寸可以缩小到2μm以下。The above steps are self-aligned and aligned to form the contact hole window of the N+ emitter. By adjusting the thickness of the sidewall oxide layer 111 and the amount of plasma etching, sidewall widths of different sizes can be obtained, thereby determining the contact hole 114 to the trench 114. The pitch and size of the contact hole 114. The cell area of the device does not need a photolithographic pattern, but a dielectric structure formed by the side wall oxide layer 111 and the oxide dielectric film layer 107, so as to achieve the self-alignment effect of the contact hole on the trench polysilicon gate structure. By controlling the thickness of the sidewall oxide layer, the distance between the contact hole and the trench can be reduced to less than 0.1 μm, and the size of the cell structure can be reduced to less than 2 μm.
步骤S8、在所述多个接触孔114处进行离子注入和退火激活，形成P型注入区。Step S8 , performing ion implantation and annealing activation at the plurality of contact holes 114 to form a P-type implantation region.
图15示出了根据本发明一个实施例的离子注入和退火激活形成P型注入区后的结构示意图。如图15所示，接触孔刻蚀完成后，形成多个接触孔114，随之进行接触孔P型离子注入和退火激活，形成P型注入区115。FIG. 15 shows a schematic diagram of the structure after ion implantation and annealing activation to form a P-type implantation region according to an embodiment of the present invention. As shown in FIG. 15 , after the etching of the contact holes is completed, a plurality of contact holes 114 are formed, followed by P-type ion implantation and annealing activation in the contact holes to form P-type implanted regions 115 .
步骤S9、在所述多个接触孔114中填充金属钨，形成钨塞填充结构116。Step S9 , filling metal tungsten in the plurality of contact holes 114 to form a tungsten plug filling structure 116 .
图16示出了根据本发明一个实施例的形成钨塞填充结构后的结构示意图。如图16所示，采用磁控溅射和化学气相沉积工艺在所述接触孔114中填充金属钨，并对表面多余的钨薄膜进行回刻，仅保留下在接触孔中的钨塞填充结构116，作为接触孔电极。FIG. 16 shows a schematic view of the structure after the tungsten plug filling structure is formed according to an embodiment of the present invention. As shown in Figure 16, the contact hole 114 is filled with metal tungsten by using magnetron sputtering and chemical vapor deposition process, and the redundant tungsten film on the surface is etched back, only the tungsten plug filling structure in the contact hole remains 116, as a contact hole electrode.
步骤S10、形成正面金属层117，在金属层上生成表面钝化层118，并刻蚀形成正面发射极封装窗口。Step S10 , forming a front metal layer 117 , forming a surface passivation layer 118 on the metal layer, and etching to form a front emitter package window.
图17示出了根据本发明一个实施例的形成正面金属层后的结构示意图。如图17所示，采用磁控溅射工艺，进行正面发射极(Emitter)金属沉积、金属层光刻和刻蚀，形成正面金属层结构117，作为正面发射极。在正面金属层117上生成表面钝化层118，按不同器件的要求，可以选择生成有机介质的表面钝化层(例如聚酰亚胺薄膜)，或者生成无机介质的表面钝化层(例如氮化硅薄膜)，并进行光刻或刻蚀形成最终的正面发射极封装窗口，至此器件正面的制作完成，形成如图1所示的绝缘栅双极型晶体管器件的正面结构。FIG. 17 shows a schematic view of the structure after forming the front metal layer according to an embodiment of the present invention. As shown in FIG. 17 , a front-side emitter (Emitter) metal deposition, metal layer photolithography and etching are performed by using a magnetron sputtering process to form a front-side metal layer structure 117 as a front-side emitter. Generate a surface passivation layer 118 on the front metal layer 117. According to the requirements of different devices, you can choose to generate a surface passivation layer (such as a polyimide film) of an organic medium, or generate a surface passivation layer of an inorganic medium (such as nitrogen Silicon thin film), and photolithography or etching to form the final front emitter packaging window, so far the fabrication of the front of the device is completed, forming the front structure of the IGBT device as shown in Figure 1.
步骤S11、进行背面结构的制作。Step S11 , fabricating the back structure.
对于背面工艺流程，可以按照场截止型(field-stop)、非穿通型(non punchthrough)、穿通型(punch through)以及逆导型(Reverse Conducting)等类别，进行相对应的结构制备。例如，图18示出了以场截止(field-stop)型IGBT为例的绝缘栅双极型晶体管的结构示意图，如图18所示，其背面结构包括：N型场截止区120、P型集电区121和背面金属层122。For the backside process flow, corresponding structures can be prepared according to field-stop type, non punchthrough type, punch through type, and reverse conducting type. For example, FIG. 18 shows a schematic structural diagram of an IGBT taking a field-stop IGBT as an example. As shown in FIG. Collector region 121 and back metal layer 122 .
根据本发明的上述绝缘栅双极型晶体管器件的制造方法，可用于场截止型/穿通型/非穿通型/逆导型绝缘栅双极型晶体管器件的制造。The manufacturing method of the above-mentioned insulated gate bipolar transistor device according to the present invention can be used in the manufacture of field stop type/punch through type/non-punch through type/reverse conduction type insulated gate bipolar transistor device.
以上对本发明的绝缘栅双极型晶体管的结构及其制造方法进行了描述。根据本发明的上述方案，通过沉积侧墙氧化层并刻蚀形成侧墙结构，并进行接触孔刻蚀，能够通过控制侧墙氧化层的厚度和等离子刻蚀量来调整侧墙厚度，从而，控制接触孔到沟槽的间距以及接触孔的尺寸，实现了接触孔对沟槽多晶硅栅结构的自对准。本发明能缩小器件元胞结构的尺寸，提高元胞密度，从而提高单位面积的电流密度，降低芯片成本，提高性价比。The structure and manufacturing method of the IGBT of the present invention have been described above. According to the above solution of the present invention, by depositing the side wall oxide layer and etching to form the side wall structure, and performing contact hole etching, the thickness of the side wall can be adjusted by controlling the thickness of the side wall oxide layer and the amount of plasma etching, thereby, Controlling the distance from the contact hole to the trench and the size of the contact hole realizes the self-alignment of the contact hole to the trench polysilicon gate structure. The invention can reduce the size of the cell structure of the device, increase the cell density, thereby increase the current density per unit area, reduce the cost of the chip, and improve the cost performance.
需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。The above are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still belong to the present invention. within the scope of the technical solution of the invention.
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| CN201611019709.1ACN106783983A (en) | 2016-11-18 | 2016-11-18 | Insulated gate bipolar transistor device and manufacturing method thereof |
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| CN201611019709.1ACN106783983A (en) | 2016-11-18 | 2016-11-18 | Insulated gate bipolar transistor device and manufacturing method thereof |
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| RJ01 | Rejection of invention patent application after publication | Application publication date:20170531 |