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CN106783655A - A kind of method for preparing semiconductor device metal cross section sample - Google Patents

A kind of method for preparing semiconductor device metal cross section sample
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Publication number
CN106783655A
CN106783655ACN201611081478.7ACN201611081478ACN106783655ACN 106783655 ACN106783655 ACN 106783655ACN 201611081478 ACN201611081478 ACN 201611081478ACN 106783655 ACN106783655 ACN 106783655A
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CN
China
Prior art keywords
metal
semiconductor device
cross
preparing semiconductor
section sample
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611081478.7A
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Chinese (zh)
Inventor
刘万鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Hiwafer Technology Co Ltd
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Chengdu Hiwafer Technology Co Ltd
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Publication date
Application filed by Chengdu Hiwafer Technology Co LtdfiledCriticalChengdu Hiwafer Technology Co Ltd
Priority to CN201611081478.7ApriorityCriticalpatent/CN106783655A/en
Publication of CN106783655ApublicationCriticalpatent/CN106783655A/en
Pendinglegal-statusCriticalCurrent

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Abstract

The invention provides a kind of new method for preparing semiconductor device metal cross section sample, the method includes inlaying semiconductor device with resin in conventional method, mechanical lapping polishing is carried out again, and chemical attack is innovatively used, the preferable metal cross-sectional facial disfigurement of ductility is more serious after solving the problems, such as mechanical lapping polishing.The sample prepared using the method can accurately measure the thickness of each layer metal under light microscope or SEM.The present invention has the characteristics of low cost, cycle is short, easy to operate, nonhazardous.

Description

A kind of method for preparing semiconductor device metal cross section sample
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology and detection, analysis field, more particularly to device metal is horizontalThe observation and measurement in section.
Background technology
Semiconductor integrated circuit manufacture many links, it is necessary to carry out the confirmation or failure analysis of technique.In inspectionDevice is surveyed generally to be required for carrying out each layer metal cross section observation and thickness measure.Therefore, commonly used observation and metering systemIncluding light microscope(OM), SEM(SEM).But with the reduction of device size, used again after direct sliverObservation by light microscope and the method for measurement cannot nowadays meet observation and the measurement request of people.
Using direct sliver(Including accurate sliver)The method observed with reference to SEM and measured, although simpleIt is easy to operate, but even if various splinter methods are accurate enough, metal fracture is irregular serious during still cannot solving sliverInfluence observation and the problem of the thickness measuring degree of accuracy.Using focused ion beam(FIB)Although preparing the method effect of cross-sectional sampleIt is really good, but focused ion beam equipment is expensive, and the company or mechanism that commission has the equipment go measurement charge height, cycle long.
Using resin it is cold inlay plus mechanical lapping polishing technology prepare sample cost it is relatively low, and with the hair of resin technologyExhibition, its firm time has been greatly shortened, and the most fast hardening of resin time has been less than a hour;On the other hand, the hair of automationExhibition popularization has caused that many polishing grinding equipments realize automation, the time cost of sample grinding and polishing, human cost and setsStandby cost is substantially reduced.In sum, resin is cold inlays plus mechanical lapping polishing has become and prepares the optimal of cross-sectional sampleOne of selection.
However, due to needing to detect device metal situation, the difference of hardness of other materials and resin in metal and deviceIt is different larger, and metal has good ductility, this causes the metal level pattern observed after mechanical lapping polishing and thickness simultaneouslyTruth in non-device.Etched using plasma etching machine, the metal in device example is deformed.And adoptMetal that can be preferably to areal deformation with the method for chemical attack carries out a certain degree of etching simultaneously because to different goldBelong to the difference of extent of corrosion, can accurately decompose multiple layer metal level and respective thickness.But use the metal etch such as conventional chloroazotic acidOperational danger is larger during liquid.Therefore, using the more gentle and small metal erosion liquid of toxic carry out chemical attack have it is non-Often important meaning.
The content of the invention
The present invention solves the technical problem of providing a kind of method, can efficiently, low cost, relatively safe prepare partlyThe metal cross section sample of conductor IC-components, and then complete the work such as the confirmation of its technique, quality testing and failure analysis.
In order to solve the above technical problems, one aspect of the present invention is:Partly leading for smithcraft will be have passed throughBody IC-components, are inlayed after being polished with mechanical lapping using resin, have been polished with certain density metal erosion corrosionSurface, then rinsed well and dried up with clear water, that is, obtain to be observed under light microscope and SEM and accurateReally measure the sample of each layer metal thickness.
Preferably, the smithcraft includes plating, evaporation and magnetron sputtering, and the metal includes gold(Au), silver(Ag)、Copper(Cu).
Preferably, the metal erosion liquid includes but is not limited to Wagner's reagent.In Wagner's reagent:Iodine 1To 13 grams, 5 to 35 grams of KI, 15 to 100 grams of water, and the ratio between molar concentration I2:I-≤0.5。
Preferably, the resin inlays the method polished with mechanical lapping is used to eliminate the cut of sample surfaces, and ensuresIt will not show cut under an optical microscope, and make region of interest exposed to sample surfaces, and its region of interest is mainly wrappedInclude dorsal pore, air bridges, the defect that need to be observed.
Preferably, the chemical attack time is 15 to 90 seconds, for correcting because mechanical lapping polishing causes cross sectionThe problem of deformation is with profit observation and accurately measures metal thickness.
Preferably, the chemical attack to metal also can accurately decompose multilayer to the difference of different metal extent of corrosionMetal level(Common such as Ti/Pt/Au)With respective thickness.
Specific embodiment
The technical scheme in the embodiment of the present invention is clearly and completely described below, it is clear that described embodimentOnly it is a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, the common skill in this areaThe every other embodiment that art personnel are obtained under the premise of creative work is not made, belongs to the model of present invention protectionEnclose.
The semiconductor device of smithcraft will be have passed through, is inlayed with after mechanical lapping polishing by resin, usedCross section deformation is corrected on the surface that certain density metal erosion corrosion has been polished, and multiple layer metal level is dividedSolution, then rinsed well and dried up with clear water, obtain to observe and accurately measuring under light microscope and SEMThe sample of each layer metal thickness,
Wherein, described multiple layer metal includes gold, silver, copper and the relatively good metal of other some ductility, semiconductorThe smithcraft that device is passed through is including but not limited to use plating, evaporation and magnetron sputtering technique;The metal erosion need bySample surfaces of the metal erosion drop after grinding and polishing, or the sample surfaces after grinding and polishing are immersed in metal erosion liquid;The chemical attack to metal also can accurately decompose multiple layer metal level and each thickness to the difference of different metal extent of corrosionDegree, its common multiple-layer metal includes i/Pt/Au multiple layer metals.
Below by taking a specific embodiment as an example:
The sample of 1 to 2 square centimeter centered on region of interest is cut from wafer, is used microsection geometrical clamp verticalIt is fixed.10 to 20 grams of epoxy resin are weighed, and by 5 matched with the resin model:1 ratio weighs appropriate curing agent, and the two is mixedWith stirring rod stir about 2 minutes to well mixed after conjunction.Well mixed resin is placed in drier, vacuum valve is opened,Vacuumize 5 minutes.While vacuumizing, one layer of releasing agent is coated in the mould inner wall for cleaning up.After releasing agent is dried,Vertical fixed sample is placed in mould center.Resin is taken out carefully to pour into mould.Normal pressure stands, and treats that resin is fully curedAfter be removed from the molds sample.Ground on the carborundum paper of 1200 mesh with automatic grinding and polishing machine, through hole has been ground to when observingStop during position.Sand paper is changed, each about 5 to 10 points of grinding and polishing is polished with 9 μm, 5 μm, 3 μm and 1 μm of metal hard rock polishing agent successivelyClock.Take about 5 milliliters of Wagner's reagents for preparing in advance(1 gram of iodine, 8 grams of KI, 100 grams of water)In 100 milliliters of small burningIn cup.The sample polishing that will be cleaned up is placed face down in the small beaker for containing IKI, stands 30 to 45 seconds, takes out sampleRinsed well with clear water after product.Sample is dried up with drying compressed air, the sample for obtaining can be clear under a scanning electron microscopeThe cross-sectional morphology of each layer metal of ground observation, and accurately measure its thickness.
Through the above way, a kind of side for preparing semiconductor device technology cross-sectional sample that the present invention is usedMethod can accurately measure the thickness of each layer metal under light microscope or SEM.The present invention have low cost,The characteristics of cycle is short, easy to operate, nonhazardous.
Embodiments of the invention are the foregoing is only, the scope of the claims of the invention is not thereby limited, it is every to utilize this hairEquivalent structure or equivalent flow conversion that bright description is made, or directly or indirectly it is used in other related technology necksDomain, is included within the scope of the present invention.

Claims (7)

CN201611081478.7A2016-11-302016-11-30A kind of method for preparing semiconductor device metal cross section samplePendingCN106783655A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
CN201611081478.7ACN106783655A (en)2016-11-302016-11-30A kind of method for preparing semiconductor device metal cross section sample

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
CN201611081478.7ACN106783655A (en)2016-11-302016-11-30A kind of method for preparing semiconductor device metal cross section sample

Publications (1)

Publication NumberPublication Date
CN106783655Atrue CN106783655A (en)2017-05-31

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN109444193A (en)*2018-09-132019-03-08胜科纳米(苏州)有限公司The failure analysis method of semiconductor chip
CN110501183A (en)*2019-08-282019-11-26广东风华高新科技股份有限公司 Metallographic section of ceramic electronic component and preparation method thereof
CN111710627A (en)*2020-05-282020-09-25北京芯可鉴科技有限公司 Chip packaging preprocessing method and chip analysis method
CN112098237A (en)*2019-06-182020-12-18万向一二三股份公司Method for testing hole punching aluminum layer elongation of aluminum plastic film of power lithium ion battery
CN114137150A (en)*2021-11-302022-03-04成都海威华芯科技有限公司Method for determining free sulfite in cyanide-free gold plating solution
CN114264260A (en)*2021-11-092022-04-01合肥新汇成微电子股份有限公司Processing method for effectively analyzing TIW structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN103075986A (en)*2013-01-112013-05-01清华大学Method for measuring film thickness
CN103700592A (en)*2013-11-292014-04-02中国电子科技集团公司第五十五研究所Manufacturing method for two-dimensional material field effect transistor based on self-alignment embedded gate structure
CN103792127A (en)*2014-01-242014-05-14西安空间无线电技术研究所Preparation method of LTCC (Low Temperature Co-fired Ceramic) section sample
US20150364567A1 (en)*2013-05-212015-12-17The 13Th Research Institute Of China Electronics Technology Group CorporationMethod for manufacturing graphene transistor based on self-aligning technology

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN103075986A (en)*2013-01-112013-05-01清华大学Method for measuring film thickness
US20150364567A1 (en)*2013-05-212015-12-17The 13Th Research Institute Of China Electronics Technology Group CorporationMethod for manufacturing graphene transistor based on self-aligning technology
CN103700592A (en)*2013-11-292014-04-02中国电子科技集团公司第五十五研究所Manufacturing method for two-dimensional material field effect transistor based on self-alignment embedded gate structure
CN103792127A (en)*2014-01-242014-05-14西安空间无线电技术研究所Preparation method of LTCC (Low Temperature Co-fired Ceramic) section sample

Cited By (8)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
CN109444193A (en)*2018-09-132019-03-08胜科纳米(苏州)有限公司The failure analysis method of semiconductor chip
CN112098237A (en)*2019-06-182020-12-18万向一二三股份公司Method for testing hole punching aluminum layer elongation of aluminum plastic film of power lithium ion battery
CN110501183A (en)*2019-08-282019-11-26广东风华高新科技股份有限公司 Metallographic section of ceramic electronic component and preparation method thereof
CN110501183B (en)*2019-08-282022-05-17广东风华高新科技股份有限公司 A kind of ceramic electronic component metallographic section and preparation method thereof
CN111710627A (en)*2020-05-282020-09-25北京芯可鉴科技有限公司 Chip packaging preprocessing method and chip analysis method
CN111710627B (en)*2020-05-282024-03-01北京芯可鉴科技有限公司Chip packaging pretreatment method and chip analysis method
CN114264260A (en)*2021-11-092022-04-01合肥新汇成微电子股份有限公司Processing method for effectively analyzing TIW structure
CN114137150A (en)*2021-11-302022-03-04成都海威华芯科技有限公司Method for determining free sulfite in cyanide-free gold plating solution

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Application publication date:20170531


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