A kind of wide-band agile frequency synthesizerTechnical field
The present invention relates to the comprehensive technical field of frequency agility, specially a kind of wide-band agile frequency synthesizer.
Background technology
At present, frequency agility track design is all based on PLL technology and DDS technologies, and this easily realizes frequency hopping control with two kinds of technologiesSystem is closely related.Based on the frequency agility track of PLL technology, have the advantages that high-frequency, broadband, Frequency spectrum quality are good, but due toThe presence of system feedback circuit, system signal stably exports the process for needing a tracking lock, it is difficult to realize frequency agility, typicallyIn hundreds of more than μ s even Microsecond grades.DDS has high frequency resolution, and frequency agility is fast, but current broadband is stillCan not realize, output bandwidth is generally 0-40%fc.Although the digital structure of DDS has many advantages, due to this structureAnd using the reason such as phase truncation, DAC digits during addressing ROM, result in that DDS clutter recognitions are poor, the purity of frequency spectrum is not as PLL.So at present frequency agility track scheme is all based on the hybrid frequency combining methods of DDS+PLL mostly, i.e. in DDS excitation PLL, PLLSlotting DDS, PLL and DDS direct conversion.Frequency agility track design needs the difficulty realized in cost, volume, power consumption and technologyEasily carry out comprehensive analysis in degree.
(1) DDS excitations PLL frequency agility schemes
The program can improve resolution ratio, and frequency converting time is shortened to a certain extent.Reference signal generates height by DDSThe signal of resolution ratio, signal is exported again by phase-locked loop circuit.The DDS can regard a frequency divider as, and PLL is considered as oneIndividual frequency multiplier, DDS determines the precision of signal resolution, and phaselocked loop determines signal frequency converting time.DDS signals are after PLL frequencys multiplicationOutput, fall in the loop bandwidth of PLL it is spuious cannot suppress with mutually making an uproar, cause Frequency spectrum quality poor.
(2) PLL interpolations DDS frequency agility scheme
Phase discriminator will be sent into after the mixing of the output of DDS and PLL feedback branches, the characteristics of the program utilizes DDS high-resolution,Overcome the spuious phase caused because of frequency multiplication to make an uproar deterioration, but, frequency frequency converting time is mainly determined by PLL.Band logical in the programWave filter design difficulty is larger, should filter the intermodulation component of frequency mixer generation, and loop parameter can not be affected again.If frequency mixerRadio frequency, intermediate frequency and local oscillator interport isolation are poor, can introduce the carrier leak and intermodulation component of higher amplitude, deteriorate radio-frequency channel index.Although the program can shorten certain frequency converting time, loop filtering design difficulty is larger, and spurious reduction index can not meet needAsk.
(3) PLL and DDS direct conversion frequency agility schemes
The program effectively overcomes the shortcoming of first two method, will not both deteriorate the spuious and index of mutually making an uproar of DDS outputs,Also the design difficulty of PLL loop filterings will not be increased.Due to DDS output frequencies it is relatively low, using PLL as local oscillation signal, by DDS frequenciesRate is mixed with PLL frequencies, exports higher operating frequency, and the program takes full advantage of the high-resolution of DDS and agile is specialPoint.Because DDS output frequencies are well below PLL output frequencies, the spuious amplitude of the DDS of frequency mixer introducing is larger, bandpass filteringDevice cannot filter the intermodulation component in band, so spurious reduction can not meet system requirements.Direct conversion scheme is by increasing by oneIndividual PLL, DDS output frequencies are carried out half of frequency multiplication to system requirements bandwidth or so, with original PLL mixing, filter intermodulationThe bandpass filter of component is easily designed, but circuit is complicated, and high cost, volume are big, are unsuitable for Miniaturization Design demand.
At present, various countries experts and scholars have carried out substantial amounts of research with regard to the PLL of fast frequency switching, mainly by Digital Frequency SynthesizeDevice, twin nuclei, VCO DC voltages are preset, become the method such as loop bandwidth and frequency and phase discrimination method realizes.
The content of the invention
For achieving the above object, the present invention provides following technical scheme：A kind of wide-band agile frequency synthesizer, will be voltage-controlledThe output frequency of oscillator is after digital governer regulation, then the signal and reference signal after the frequency dividing of the first frequency dividerReference signal after the second frequency divider frequency dividing sends into phase discriminator jointly, and phase discriminator is by comparing the frequency of above-mentioned two signalDifference one DC pulse voltage of output, through loop filter the high fdrequency component of the voltage is filtered, and produces a VCO control electricityPressure, and using digital capacitance battle array, according to predetermined frequency, directly change voltage tuning point in VCO charge pump phase lock loops, by tuningVoltage accelerates frequency stable process, the output of voltage controlled oscillator is progressively stable at into expected frequency and completes frequency agility, and passes throughTri-frequency divider realizes 1-64 times of frequency dividing, exports broader frequency.
Used as a kind of preferred scheme of the present invention, first frequency divider and the second frequency divider are fractional frequency division pattern.
Used as a kind of preferred scheme of the present invention, the phase discriminator adopts high-frequency phase discriminator, in combination with digital capacitanceBattle array, realizes the high-resolution rate-adaptive pacemaker precision of 3Hz.
Used as a kind of preferred scheme of the present invention, the voltage controlled oscillator adopts micropackaging compensation crystal oscillator, realize-102dBc/Hz@1K phase noises, 80dBc spurious reductions, the technical indicator of 70dBc harmonics restraints.
Used as a kind of preferred scheme of the present invention, the loop filter is using micropackaging resistance and electric capacity.
Compared with prior art, the invention has the beneficial effects as follows：Present invention is generally directed to the miniaturization communication dress such as hand-held stationMeter is installed, using highly integrated, low-power consumption, Miniaturization Design scheme, realizes that fast frequency switching, wide-band (25MHz～3.1GHz) are defeatedGo out and high-resolution (3Hz), frequency switching time is arbitrarily changed in the range of wide-band and is not more than 5 μ s, support 10000 jumps/s；Pass throughOptimization Simulation is designed, and in the case where reference source compensation crystal phase noise is -130dBc/Hz@1KHz, obtains good phase placeNoise, surveys as -100dBc/Hz@1KHz.
Description of the drawings
Fig. 1 is schematic structural view of the invention；
Fig. 2 is phase noise analogous diagram of the present invention；
Fig. 3 is agile analogous diagram of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, completeSite preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based onEmbodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not madeEmbodiment, belongs to the scope of protection of the invention.
Embodiment：
Fig. 1 is referred to, the present invention provides a kind of technical scheme：A kind of wide-band agile frequency synthesizer, it is characterised in that：By the output frequency of voltage controlled oscillator after digital governer regulation, then the signal after the frequency dividing of the first frequency divider and ginsengExamine reference signal of the signal after the second frequency divider frequency dividing and send into phase discriminator jointly, phase discriminator is by comparing above-mentioned two signalDifference on the frequency export a DC pulse voltage, filter the high fdrequency component of the voltage through loop filter, produce a VCO controlVoltage processed, and using digital capacitance battle array, according to predetermined frequency, directly change voltage tuning point in VCO charge pump phase lock loops, pass throughVT accelerates frequency stable process, the output of voltage controlled oscillator is progressively stable at into expected frequency and completes frequency agility, and1-64 times of frequency dividing is realized by tri-frequency divider, broader frequency is exported.
First frequency divider and the second frequency divider are fractional frequency division pattern, and the phase discriminator adopts high-frequency phase discriminator,In combination with digital capacitance battle array, the high-resolution rate-adaptive pacemaker precision of 3Hz is realized, the voltage controlled oscillator adopts micropackaging temperature compensationCrystal oscillator, realizes -102dBc/Hz@1K phase noises, 80dBc spurious reductions, the technical indicator of 70dBc harmonics restraints, instituteLoop filter is stated using micropackaging resistance and electric capacity, is -130dBc/Hz@1K in reference source phase noise using simulation softwareIn the case of, the indexs such as phase noise are simulated, meet design object.
Its phase noise emulation is as shown in Figure 2；
Agile analogous diagram is as shown in Figure 3.
In sum, this programme is designed using fractional frequency division, the preset technology of VCO DC voltages.Increase in VCO circuitsPlus digital variable varactor array, according to predetermined frequency, varactor optimum capacitance is selected, quickly adjustment VCO is electricVT in lotus pump phaselocked loop, fast and stable when realizing that frequency changes frequency.By emulation, it is contemplated that switching time is not more than 5 μ s,Holding equipment frequency hopping rate request, Miniaturization Design can be widely applied to the various occasions high to volume and power consumption requirements.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er QieIn the case of spirit or essential attributes without departing substantially from the present invention, the present invention can be in other specific forms realized.Therefore, no matterFrom the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended powerProfit is required rather than described above is limited, it is intended that all in the implication and scope of the equivalency of claim by fallingChange is included in the present invention.Any reference in claim should not be considered as and limit involved claim.