CN106656168B - Clock data recovery device and method - Google Patents
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- CN106656168B CN106656168BCN201611264489.9ACN201611264489ACN106656168BCN 106656168 BCN106656168 BCN 106656168BCN 201611264489 ACN201611264489 ACN 201611264489ACN 106656168 BCN106656168 BCN 106656168B
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- 238000011084recoveryMethods0.000titleclaimsabstractdescription61
- 238000000034methodMethods0.000titleclaimsabstractdescription26
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- 230000007274generation of a signal involved in cell-cell signalingEffects0.000claimsdescription7
- 239000013078crystalSubstances0.000claimsdescription5
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
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Abstract
Description
Technical Field
The present invention belongs to the field of signal detection technology, and more particularly, to a clock data recovery apparatus and a clock data recovery method.
Background
The baseband communication method in data communication is to transmit data directly, rather than by a carrier wave through modulation, and constitutes the mainstream of long-distance broadband data communication at present. The baseband communication can be divided into two modes of parallel data communication and serial data communication, wherein the serial data communication is to transmit byte signals bit by bit, and no additional synchronous clock signal is used. Serial data communication is often used for long-distance communication because it can save the cost of the system in many cases.
In a serial data communication system, a receiver cannot independently generate a clock signal for data synchronization between a transmitting side and a receiving side, but recovers the clock signal from a received data stream to achieve a synchronous operation. The Clock and Data Recovery (CDR) circuit is responsible for extracting a Clock from serial Data received by the receiver, and samples the serial Data with the Clock to generate a recovered Data signal, so that a subsequent serial-to-parallel conversion circuit can convert the sampled recovered Data signal from the serial signal to a parallel signal according to the Clock. Therefore, in a serial data communication system, the clock data recovery circuit plays a key role in a receiver and is a circuit module with extremely high working speed. The clock data recovery circuit generally adopts a structure based on a phase-locked loop, fig. 1 shows a schematic structural diagram of a clock data recovery device according to the prior art, and the clockdata recovery device 100 includes: a phase detector 101 for comparing a phase of received data with a phase of a sampling clock and generating an error signal according to a phase difference therebetween; a loop filter 102 for performing accumulation filtering on the error signal generated by the phase detector 101; and a voltage controlled oscillator 103 for generating a multiphase clock of data samples.
In a high-speed serial data communication system, serial data is interfered by crosstalk between data channels, device noise of a circuit, power supply fluctuation and the like, and any interference on the serial data generates fluctuation on the vertical voltage amplitude and the horizontal time amplitude of the data. Therefore, to ensure that the clock and data recovery circuit can correctly recover the clock and data, the phase of the clock in the phase locked loop needs to always track the phase of the serial data. The prior phase-locked loop realizes the adjustment of the loop bandwidth by adjusting the proportional gain of a loop filter, the larger the proportional gain is, the larger the loop bandwidth is, the faster the locking speed is, and the more timely the phase tracking is. However, as the loop bandwidth increases, the clock signal jitter of the vco output increases. Therefore, the sampling data obtained by sampling according to the clock signal output by the voltage-controlled oscillator is easy to generate errors, and the error rate of the clock data recovery circuit is improved. Therefore, in the conventional clock data recovery circuit, a contradiction exists between the improvement of the loop bandwidth and the reduction of the error rate, and the quick data phase tracking and the low error rate are difficult to be considered simultaneously.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a clock data recovery apparatus and a clock data recovery method, which can generate two clock signals according to error signals subjected to different filtering processes, so as to control an error rate of data recovery while quickly tracking a change of the data signals.
According to an aspect of the present invention, there is provided a clock data recovery apparatus including: the phase discriminator is used for generating an error signal according to the phase relation between a data signal and a clock signal, and the clock signal at least comprises a first clock signal and a second clock signal; a first loop filter for performing a first loop filtering on the error signal; a first voltage controlled oscillator for generating the first clock signal from the error signal subjected to the first loop filtering; and the second clock signal generating module is used for generating the second clock signal according to the error signal generated by the phase discriminator.
Preferably, the second clock signal generating module includes: a low pass filter for low pass filtering the error signal filtered by the first loop; a second voltage controlled oscillator for generating the second clock signal from the low pass filtered error signal.
Preferably, the low pass filter comprises an integrator.
Preferably, the integrator comprises: the first input end of the adder receives the error signal filtered by the first loop, the second input end of the adder is connected with the output end of the operation module, and the output end of the adder is connected with the input end of the operation module.
Preferably, the second voltage controlled oscillator comprises an LC voltage controlled oscillator, an RC voltage controlled oscillator or a crystal voltage controlled oscillator.
Preferably, the second clock signal generating module includes: a second loop filter for second loop filtering the error signal from the phase detector; a second voltage controlled oscillator for generating the second clock signal from the error signal filtered by a second loop.
Preferably, the second clock signal generation module further includes: and the low-pass filter is used for performing low-pass filtering on the error signal subjected to the second loop filtering and sending the error signal subjected to the low-pass filtering to the second voltage-controlled oscillator.
Preferably, the first loop filter includes: the first multiplier is used for multiplying the error signal by a preset proportional adjustment coefficient to obtain a first multiplied error signal; the second multiplier is used for multiplying the error signal by a preset integral adjusting coefficient to obtain a second multiplied error signal; an integrator for performing accumulation filtering on the second multiplied error signal; an adder for adding the first multiplied error signal and the second multiplied error signal cumulatively filtered by the integrator to obtain a first loop filtered error signal.
Preferably, the second loop filter includes: the first multiplier is used for multiplying the error signal from the phase discriminator by a preset proportional adjustment coefficient to obtain a first multiplied error signal; the second multiplier is used for multiplying the error signal from the phase discriminator by a preset integral adjusting coefficient to obtain a second multiplied error signal; an integrator for performing accumulation filtering on the second multiplied error signal; an adder for adding the first multiplied error signal and the second multiplied error signal cumulatively filtered by the integrator to obtain a second loop filtered error signal.
According to another aspect of the present invention, there is provided a clock data recovery method including: generating an error signal according to the phase relation of a data signal and a clock signal through a phase discriminator, wherein the clock signal at least comprises a first clock signal and a second clock signal; performing a first loop filtering on the error signal by a first loop filter; generating, by a first voltage controlled oscillator, the first clock signal from the error signal that is subjected to a first loop filtering; generating, by a second clock signal generation module, the second clock signal from the error signal generated by the phase detector.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic structural diagram of a clock data recovery apparatus according to the prior art.
Fig. 2 is a schematic structural diagram of a clock data recovery apparatus according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a clock data recovery apparatus according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a clock data recovery apparatus according to an embodiment of the present invention.
Fig. 5 shows a schematic structural diagram of an integrator included in the low-pass filter according to the embodiment of the present invention.
Fig. 6 shows a schematic structural diagram of a loop filter according to an embodiment of the present invention.
Fig. 7 is a diagram illustrating a phase relationship between signals in a clock data recovery process according to the prior art.
Fig. 8 is a diagram illustrating jitter amplitudes of respective signals in a clock data recovery process according to the related art.
Fig. 9 is a diagram illustrating jitter amplitudes of signals during clock data recovery according to an embodiment of the present invention.
Fig. 10 shows a flow chart of a clock data recovery method according to an embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
To ensure that the clock and data in the data signal are correctly recovered, at least two clock signals are required, including a first clock signal and a second clock signal. Fig. 7 is a schematic diagram showing the phase relationship between signals in a clock data recovery process according to the prior art, when a loop is locked, a first clock signal is aligned with a flip edge of data, and a second clock signal is aligned with a center point of the data. And sampling the data signal by using the first clock signal and the second clock signal to obtain a recovered data signal.
Fig. 8 is a schematic diagram showing jitter amplitudes of signals in a clock data recovery process according to the prior art, tc represents the jitter amplitude of the second clock signal, ts represents a timing margin (timing margin) of the whole system, and td corresponds to the jitter amplitude of the data signal under the action of high-frequency and low-frequency interference, and is a sampling point which is easy to cause errors. If the timing margin ts is very small, the jitter amplitude tc of the second clock signal is very large due to the large loop bandwidth, sampling at a sampling point td corresponding to the jitter amplitude tc is easily caused, and the error rate of data recovery is easily increased due to the delay of the clock signal caused by the clock data recovery circuit.
Fig. 2 is a schematic structural diagram of a clock data recovery apparatus according to an embodiment of the present invention. The clockdata recovery apparatus 200 includes: aphase detector 201, aloop filter 202, a low pass filter 203, a first voltage controlled oscillator 204 and a second voltage controlled oscillator 205.
Thephase detector 201 is configured to generate an error signal according to a phase relationship between a data signal and a clock signal, where the clock signal includes at least a first clock signal and a second clock signal.
Theloop filter 202 is used for loop filtering the error signal.
The first voltage controlled oscillator 204 is configured to generate the first clock signal according to the error signal after loop filtering.
The low pass filter 203 is used to low pass filter the error signal that is loop filtered.
The second voltage controlled oscillator 205 is configured to generate the second clock signal according to the low-pass filtered error signal.
In some embodiments, the low pass filter 203 may include an integrator. For example, fig. 5 shows a schematic structural diagram of an integrator included in a low-pass filter according to an embodiment of the present invention, where the integrator 500 includes an adder and an operation module for performing delay accumulation on an input signal, an output terminal of the adder is connected to an input terminal of the operation module, and an output terminal of the operation module is connected to one input terminal of the adder to form a loop.
Fig. 6 shows a schematic structural diagram of a loop filter according to an embodiment of the present invention. In some embodiments, theloop filter 202 may include: afirst multiplier 2021, asecond multiplier 2022, anintegrator 2023, and anadder 2024.
Thefirst multiplier 2021 is configured to multiply the error signal by a preset scaling factor to obtain a first multiplied error signal.
Thesecond multiplier 2022 is configured to multiply the error signal by a predetermined integral adjustment coefficient to obtain a second multiplied error signal.
Theintegrator 2023 is used to cumulatively filter the second multiplied error signal. In some embodiments, theintegrator 2023 may have a structure similar to that of the integrator 500, and the integrator 500 is described in detail above with reference to fig. 5, and will not be described herein again.
In some embodiments, the first voltage controlled oscillator 204 and the second voltage controlled oscillator 205 may be any one of an LC voltage controlled oscillator, an RC voltage controlled oscillator, and a crystal voltage controlled oscillator.
Fig. 9 is a schematic diagram illustrating jitter amplitudes of signals in a clock data recovery process according to an embodiment of the present invention, where a first clock signal can quickly track changes of an edge of input data, and is subjected to low-pass filtering, a second clock signal changes relatively slowly, high-frequency jitter is suppressed, and a jitter amplitude tc is reduced, so as to reduce an error rate of data recovery and improve a correct sampling rate of a data signal.
In this embodiment, according to the clock data recovery apparatus and method of the embodiments of the present invention, different filtering processes are performed on error signals generated by controlling two clock signals according to different properties of the two clock signals. And performing loop filtering on the error signal generated by the phase discriminator, performing low-pass filtering, and generating a second clock signal according to the error signal subjected to the low-pass filtering. The method has the advantages that the loop bandwidth is larger by adjusting the proportional adjustment coefficient of the loop filtering, so that the first clock signal can track the data signal more quickly, meanwhile, the error signal subjected to the loop filtering is subjected to low-pass filtering, the high-frequency jitter of the second clock signal is reduced, and the correct sampling rate of the data signal is improved.
Fig. 3 is a schematic structural diagram of a clock data recovery apparatus according to an embodiment of the present invention. The clockdata recovery apparatus 300 includes: aphase detector 301, a first loop filter 302, asecond loop filter 303, a first voltage controlled oscillator 304 and a second voltage controlledoscillator 305.
Thephase detector 301 is configured to generate an error signal according to a phase relationship between a data signal and a clock signal, where the clock signal includes at least a first clock signal and a second clock signal.
The first loop filter 302 is used for first loop filtering the error signal.
Asecond loop filter 303 is used for second loop filtering the error signal.
The first voltage controlled oscillator 304 is configured to generate the first clock signal according to the error signal filtered by the first loop.
A second voltage controlledoscillator 305 is used to generate the second clock signal from the error signal filtered by the second loop.
In some embodiments, the first loop filter 302 and thesecond loop filter 303 may have a structure similar to that of theloop filter 202, and theloop filter 202 is described in detail above with reference to fig. 6, and is not described here again.
The first loop filter 302 and thesecond loop filter 303 may set different scaling coefficients.
In some embodiments, the first voltage controlled oscillator 204 and the second voltage controlled oscillator 205 may be any one of an LC voltage controlled oscillator, an RC voltage controlled oscillator, and a crystal voltage controlled oscillator.
Fig. 9 is a schematic diagram illustrating jitter amplitudes of signals in a clock data recovery process according to an embodiment of the present invention, where a first loop filter with a large loop bandwidth is performed on an error signal generated by controlling a first clock signal, so that the first clock signal can quickly track an edge change of input data. And second loop filtering with a smaller loop bandwidth is carried out on an error signal generated by controlling a second clock signal, so that the second clock signal changes relatively slowly, high-frequency jitter is inhibited, and the jitter amplitude tc is reduced, thereby reducing the error rate of data recovery and improving the correct sampling rate of the data signal.
In this embodiment, different filtering processes are performed on error signals that control the generation of the two clock signals, for different properties of the two clock signals. The method comprises the steps of carrying out first loop filtering on an error signal generated by a phase discriminator, generating a first clock signal according to the error signal filtered by the first loop, carrying out second loop filtering different from the first loop filtering on the error signal generated by the phase discriminator, generating a second clock signal according to the error signal filtered by the second loop, and reducing high-frequency jitter of the second clock signal by controlling loop bandwidth of the second loop filtering, so that the error rate of data recovery is controlled, and the correct sampling rate of a data signal is improved.
Fig. 4 is a schematic structural diagram of a clock data recovery apparatus according to an embodiment of the present invention. The clockdata recovery apparatus 400 includes: aphase detector 401, a first loop filter 402, a second loop filter 403, a low pass filter 404, a first voltage controlledoscillator 405 and a second voltage controlled oscillator 406.
Thephase detector 401 is configured to generate an error signal according to a phase relationship between a data signal and a clock signal, where the clock signal includes at least a first clock signal and a second clock signal.
The first loop filter 402 is used for first loop filtering the error signal.
A second loop filter 403 is used to perform a second loop filtering on the error signal.
A low pass filter 404 is used to low pass filter the error signal filtered by the second loop.
The first voltage controlledoscillator 405 is configured to generate the first clock signal based on the error signal that is subjected to the first loop filtering.
The second voltage controlled oscillator 406 is configured to generate the second clock signal according to the low-pass filtered error signal.
In some embodiments, the low pass filter 404 may include an integrator. For example, fig. 5 shows a schematic structural diagram of an integrator included in a low-pass filter according to an embodiment of the present invention, where the integrator 500 includes an adder and an operation module for performing delay accumulation on an input signal, an output terminal of the adder is connected to an input terminal of the operation module, and an output terminal of the operation module is connected to one input terminal of the adder to form a loop.
In some embodiments, the first loop filter 402 and the second loop filter 403 may have a structure similar to that of theloop filter 202, and theloop filter 202 is described in detail above with reference to fig. 6, and is not described herein again.
The first loop filter 402 and the second loop filter 403 may set different scaling coefficients.
In some embodiments, the first voltage controlledoscillator 405 and the second voltage controlled oscillator 406 may be any one of an LC voltage controlled oscillator, an RC voltage controlled oscillator, and a crystal voltage controlled oscillator.
Fig. 9 is a diagram illustrating jitter amplitudes of signals in a clock data recovery process according to an embodiment of the present invention, and the error signal generated by controlling the first clock signal is subjected to first loop filtering, so that the first clock signal can quickly track changes of input data edges. And performing second loop filtering on an error signal generated by controlling a second clock signal, then performing low-pass filtering on the error signal subjected to the second loop filtering, and under the combined action of the second loop filtering and the low-pass filtering, the second clock signal changes slowly relatively, high-frequency jitter is inhibited, and the jitter amplitude tc is reduced, so that the error rate of data recovery is reduced, and the correct sampling rate of a data signal is improved.
In this embodiment, different filtering processes are performed on error signals that control the generation of the two clock signals, for different properties of the two clock signals. The method comprises the steps of performing first loop filtering on an error signal generated by a phase discriminator, generating a first clock signal according to the error signal subjected to the first loop filtering, performing second loop filtering different from the first loop filtering on the error signal generated by the phase discriminator, performing low-pass filtering on the error signal subjected to the second loop filtering, generating a second clock signal according to the error signal subjected to the low-pass filtering, and performing low-pass filtering on the error signal subjected to the second loop filtering by controlling the loop bandwidth of the second loop filtering to reduce the high-frequency jitter of the second clock signal, so that the error rate of data recovery can be controlled, and the correct sampling rate of data signals is improved.
Fig. 10 shows a flow chart of a clock data recovery method according to an embodiment of the invention.
In step S1, an error signal is generated according to the phase relationship between the data signal and a clock signal, the clock signal including at least a first clock signal and a second clock signal.
In step S2, loop filtering is performed on the error signal.
In some embodiments, the error signal may be separately first loop filtered and second loop filtered. The first loop filter and the second loop filter have different scaling factors.
In step S3, the first clock signal is generated from the loop filtered error signal.
In some embodiments, the first clock signal may be generated from the error signal that is subjected to the first loop filtering.
In step S4, the loop-filtered error signal is low-pass filtered, and the second clock signal is generated according to the low-pass filtered error signal.
In some embodiments, the error signal filtered by the second loop may be low pass filtered and the second clock signal may be generated based on the low pass filtered error signal.
In some embodiments, the error signal may be separately first loop filtered and second loop filtered. The first loop filter and the second loop filter have different scaling factors. When the scaling factor of the second loop filter is smaller than a preset value, the error signal filtered by the second loop filter may not be low-pass filtered.
In this embodiment, different filtering processes are performed on error signals that control the generation of the two clock signals, for different properties of the two clock signals. The error signal generated by the phase discriminator may be loop filtered and then low pass filtered, and the second clock signal may be generated based on the low pass filtered error signal. The method has the advantages that the proportional adjustment coefficient of the loop filter is adjusted to obtain larger loop bandwidth, so that the first clock signal can track the data signal more quickly, meanwhile, the error signal subjected to the loop filter is subjected to low-pass filtering, high-frequency jitter of the second clock signal is reduced, the error rate of data recovery is controlled, and the correct sampling rate of the data signal is improved. The error signal generated by the phase discriminator can be subjected to first loop filtering, a first clock signal is generated according to the error signal subjected to the first loop filtering, second loop filtering different from the first loop filtering is performed on the error signal generated by the phase discriminator, low-pass filtering is performed on the error signal subjected to the second loop filtering, a second clock signal is generated according to the error signal subjected to the low-pass filtering, and high-frequency jitter of the second clock signal is reduced under the combined action of the second loop filtering and the low-pass filtering, so that the error rate of data recovery is controlled, and the correct sampling rate of the data signal is improved.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A clock data recovery apparatus comprising:
the phase discriminator is used for generating an error signal according to the phase relation between a data signal and a clock signal, and the clock signal at least comprises a first clock signal and a second clock signal;
a first loop filter for performing a first loop filtering on the error signal;
a first voltage controlled oscillator for generating the first clock signal according to the error signal filtered by the first loop so that the first clock signal can quickly track the edge of the data signal;
and the second clock signal generation module is used for performing low-pass filtering processing on the error signal generated by the phase discriminator and generating the second clock signal according to the error signal, the second clock signal is aligned with the central point of the data signal, and the low-pass filtering processing is used for inhibiting high-frequency jitter of the second clock signal.
2. The clock data recovery apparatus of claim 1, wherein the second clock signal generation module comprises:
a low pass filter for low pass filtering the error signal filtered by the first loop;
a second voltage controlled oscillator for generating the second clock signal from the low pass filtered error signal.
3. The clock data recovery apparatus of claim 2, wherein the low pass filter comprises an integrator.
4. The clock data recovery apparatus of claim 3, wherein the integrator comprises: the first input end of the adder receives the error signal filtered by the first loop, the second input end of the adder is connected with the output end of the operation module, and the output end of the adder is connected with the input end of the operation module.
5. The clock data recovery apparatus of claim 2, wherein the second voltage controlled oscillator comprises an LC voltage controlled oscillator, an RC voltage controlled oscillator, or a crystal voltage controlled oscillator.
6. The clock data recovery apparatus of claim 1, wherein the second clock signal generation module comprises:
a second loop filter for second loop filtering the error signal from the phase detector;
a second voltage controlled oscillator for generating the second clock signal from the error signal filtered by a second loop.
7. The clock data recovery apparatus of claim 6, wherein the second clock signal generation module further comprises:
and the low-pass filter is used for performing low-pass filtering on the error signal subjected to the second loop filtering and sending the error signal subjected to the low-pass filtering to the second voltage-controlled oscillator.
8. The clock data recovery apparatus of claim 1, wherein the first loop filter comprises:
the first multiplier is used for multiplying the error signal by a preset proportional adjustment coefficient to obtain a first multiplied error signal;
the second multiplier is used for multiplying the error signal by a preset integral adjusting coefficient to obtain a second multiplied error signal;
an integrator for performing accumulation filtering on the second multiplied error signal;
an adder for adding the first multiplied error signal and the second multiplied error signal cumulatively filtered by the integrator to obtain a first loop filtered error signal.
9. The clock data recovery apparatus of claim 6, wherein the second loop filter comprises:
the first multiplier is used for multiplying the error signal from the phase discriminator by a preset proportional adjustment coefficient to obtain a first multiplied error signal;
the second multiplier is used for multiplying the error signal from the phase discriminator by a preset integral adjusting coefficient to obtain a second multiplied error signal;
an integrator for performing accumulation filtering on the second multiplied error signal;
an adder for adding the first multiplied error signal and the second multiplied error signal cumulatively filtered by the integrator to obtain a second loop filtered error signal.
10. A clock data recovery method, comprising:
generating an error signal according to the phase relation of a data signal and a clock signal through a phase discriminator, wherein the clock signal at least comprises a first clock signal and a second clock signal;
performing a first loop filtering on the error signal by a first loop filter;
generating the first clock signal according to the error signal filtered by the first loop by a first voltage-controlled oscillator, so that the first clock signal can quickly track the edge of the data signal;
and performing low-pass filtering processing on the error signal generated by the phase discriminator through a second clock signal generation module, and generating the second clock signal according to the error signal, wherein the second clock signal is aligned with the central point of the data signal, and the low-pass filtering processing is used for suppressing high-frequency jitter of the second clock signal.
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| TWI630799B (en)* | 2017-07-26 | 2018-07-21 | 北京集創北方科技股份有限公司 | Phase detector and clock and data recovery device |
| CN108055036B (en)* | 2017-10-31 | 2020-12-29 | 北京集创北方科技股份有限公司 | Loop bandwidth adjusting method and device of clock data recovery circuit |
| CN107911113B (en)* | 2017-10-31 | 2021-01-12 | 北京集创北方科技股份有限公司 | Clock data recovery circuit, loop bandwidth adjusting method thereof and processor |
| CN110493152B (en)* | 2019-08-19 | 2021-09-28 | 哈尔滨工业大学 | Self-adaptive equalization circuit based on frequency spectrum balancing method |
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