技术领域technical field
本发明涉及光电子技术领域，特别涉及一种发光二极管的外延片及制备方法。The invention relates to the technical field of optoelectronics, in particular to an epitaxial wafer of a light emitting diode and a preparation method thereof.
背景技术Background technique
发光二极管(英文：Light Emitting Diode，简称：LED)作为光电子产业中极具影响力的新产品，具有体积小、使用寿命长、颜色丰富多彩、能耗低等特点，广泛应用于照明、显示屏、信号灯、背光源、玩具等领域。芯片是LED的核心组件，它由外延片经过多道工序加工而成。Light Emitting Diode (English: Light Emitting Diode, referred to as: LED), as a very influential new product in the optoelectronics industry, has the characteristics of small size, long service life, colorful colors, and low energy consumption. It is widely used in lighting, display screens , signal lights, backlight, toys and other fields. The chip is the core component of the LED, which is processed by epitaxial wafers through multiple processes.
通常外延片包括蓝宝石衬底和依次生长在蓝宝石衬底上的缓冲层、未掺杂GaN层、n型层、多量子阱层和p型层。蓝宝石的主要组分为Al2O3，Al2O3与GaN之间存在很大的晶格失配，虽然缓冲层可以起到一定的缓冲作用，减少Al2O3与GaN之间的晶格失配，但是外延片的生长过程中仍然会产生较多的晶格缺陷，导致外延片晶体质量较差，影响LED的可靠性和稳定性。Generally, the epitaxial wafer includes a sapphire substrate and a buffer layer, an undoped GaN layer, an n-type layer, a multi-quantum well layer and a p-type layer grown sequentially on the sapphire substrate. The main component of sapphire is Al2 O3 , there is a large lattice mismatch between Al2 O3 and GaN, although the buffer layer can play a buffer role to reduce the crystal lattice between Al2 O3 and GaN. Lattice mismatch, but more lattice defects will still be generated during the growth process of the epitaxial wafer, resulting in poor crystal quality of the epitaxial wafer, affecting the reliability and stability of the LED.
发明内容Contents of the invention
为了解决GaN与蓝宝石衬底的晶格失配度较高导致外延片的生长过程中会产生较多的晶格缺陷的问题，本发明实施例提供了一种发光二极管的外延片及制备方法。所述技术方案如下：In order to solve the problem that the high lattice mismatch between GaN and the sapphire substrate causes more lattice defects during the growth process of the epitaxial wafer, the embodiments of the present invention provide an epitaxial wafer and a preparation method of a light emitting diode. Described technical scheme is as follows:
一方面，本发明实施例提供了一种发光二极管的外延片，所述外延片包括蓝宝石衬底和依次层叠在所述蓝宝石衬底上的缓冲层、成核层、未掺杂GaN层、n型层、多量子阱层和p型层，所述成核层包括交替层叠的SiN子层和AlxGa1-xN子层，其中0＜x＜1。On the one hand, an embodiment of the present invention provides an epitaxial wafer of a light emitting diode, the epitaxial wafer includes a sapphire substrate and a buffer layer, a nucleation layer, an undoped GaN layer, n type layer, multi-quantum well layer and p-type layer, the nucleation layer includes alternately stacked SiN sublayers and AlxGa1-xNsublayers , where 0<x<1.
优选地，0.1≤x≤0.3。Preferably, 0.1≤x≤0.3.
进一步地，所述SiN子层的厚度为2～30nm，所述AlxGa1-xN子层的厚度为2～30nm。Further, the thickness of the SiN sub-layer is 2-30 nm, and the thickness of the Alx Ga1-x N sub-layer is 2-30 nm.
优选地，所述SiN子层和所述AlxGa1-xN子层的层数相同，且所述SiN子层的层数为10～80。Preferably, the number of layers of the SiN sublayer and the AlxGa1-xN sublayer are the same, and the number of layers of the SiN sublayer is 10-80.
优选地，所述成核层的厚度大于或等于200nm。Preferably, the thickness of the nucleation layer is greater than or equal to 200 nm.
另一方面，本发明实施例还提供了一种发光二极管的外延片的制备方法，所述制备方法包括：On the other hand, the embodiment of the present invention also provides a method for preparing an epitaxial wafer of a light-emitting diode, the preparation method comprising:
提供一蓝宝石衬底；providing a sapphire substrate;
在所述蓝宝石衬底上外延生长缓冲层；epitaxially growing a buffer layer on the sapphire substrate;
在所述缓冲层上生长成核层；growing a nucleation layer on the buffer layer;
在所述成核层上生长未掺杂GaN层；growing an undoped GaN layer on the nucleation layer;
在所述未掺杂GaN层上生长n型层；growing an n-type layer on the undoped GaN layer;
在所述n型层上生长多量子阱层；growing a multiple quantum well layer on the n-type layer;
在所述多量子阱层上生长p型层，growing a p-type layer on the multiple quantum well layer,
其中，所述成核层包括交替生长的SiN子层和AlxGa1-xN子层，其中0＜x＜1。Wherein, the nucleation layer includes alternately grown SiN sublayers and AlxGa1-xNsublayers , where 0<x<1.
进一步地，所述SiN子层的生长压力为300～900torr，所述AlxGa1-xN子层的生长压力为100～900torr。Further, the growth pressure of the SiN sub-layer is 300-900 torr, and the growth pressure of the AlxGa1-xN sub-layer is 100-900 torr.
优选地，所述SiN子层和所述AlxGa1-xN子层的层数相同，且所述SiN子层的层数为10～80。Preferably, the number of layers of the SiN sublayer and the AlxGa1-xN sublayer are the same, and the number of layers of the SiN sublayer is 10-80.
可选地，所述在所述缓冲层上生长成核层，包括：Optionally, the growing a nucleation layer on the buffer layer includes:
在氢气气氛或氮氢混合气氛中生长所述成核层。The nucleation layer is grown in a hydrogen atmosphere or a nitrogen-hydrogen mixed atmosphere.
可选地，所述在氢气气氛或氮氢混合气氛中生长所述成核层，包括：Optionally, growing the nucleation layer in a hydrogen atmosphere or a nitrogen-hydrogen mixed atmosphere includes:
在氢气气氛中生长所述SiN子层，在氮氢混合气氛中生长所述AlxGa1-xN子层。The SiN sublayer is grown in a hydrogen atmosphere, and the AlxGa1-xN sublayer is grown in a nitrogen-hydrogen mixed atmosphere.
本发明实施例提供的技术方案带来的有益效果是：通过在缓冲层和未掺杂GaN层之间设置一层成核层，成核层包括交替层叠的SiN子层和AlxGa1-xN子层，AlxGa1-xN与蓝宝石衬底、GaN的晶格匹配较好，AlxGa1-xN层和SiN层交替层叠形成超晶格结构，GaN和蓝宝石衬底之间的晶格失配度降低，晶格缺陷减少，晶格质量提高。LED的可靠性和稳定性得以提升。而且可以避免应力的产生，改善外延片的翘曲度，提高发光效率和抗静电能力。另外，SiN层可以提供电子，有利于电流的扩展，降低外延片的正向电压，进一步提高发光效率。The beneficial effect brought by the technical solution provided by the embodiment of the present invention is: by setting a nucleation layer between the buffer layer and the undoped GaN layer, the nucleation layer includes alternately stacked SiN sublayers and Alx Ga1- x N sub-layer, Alx Ga1-x N has better lattice matching with sapphire substrate and GaN, and Alx Ga1-x N layer and SiN layer are stacked alternately to form a superlattice structure The lattice mismatch between them is reduced, the lattice defects are reduced, and the lattice quality is improved. LED reliability and stability are improved. Moreover, it can avoid the generation of stress, improve the warpage of the epitaxial wafer, and improve the luminous efficiency and antistatic ability. In addition, the SiN layer can provide electrons, which is beneficial to the expansion of the current, reduces the forward voltage of the epitaxial wafer, and further improves the luminous efficiency.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.
图1是本发明实施例提供的一种发光二极管的外延片的结构示意图；FIG. 1 is a schematic structural view of an epitaxial wafer of a light emitting diode provided by an embodiment of the present invention;
图2是本发明实施例提供的一种成核层的局部结构示意图；2 is a schematic diagram of a partial structure of a nucleation layer provided by an embodiment of the present invention;
图3是本发明实施例提供的一种多量子阱层的局部结构示意图；3 is a schematic diagram of a partial structure of a multi-quantum well layer provided by an embodiment of the present invention;
图4是本发明实施例提供的一种发光二极管的外延片的制备方法的流程图；4 is a flowchart of a method for preparing an epitaxial wafer of a light-emitting diode provided by an embodiment of the present invention;
图5是本发明实施例提供的另一种发光二极管的外延片的制备方法的流程图。FIG. 5 is a flow chart of another method for manufacturing an epitaxial wafer of a light emitting diode provided by an embodiment of the present invention.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.
图1是本发明实施例提供的一种发光二极管的外延片的结构示意图，如图1所示，该外延片包括依次层叠在蓝宝石衬底10上的缓冲层20、成核层30、未掺杂GaN层40、n型层50、多量子阱层60和p型层70。图2是本发明实施例提供的一种成核层的局部结构示意图，如图2所示，成核层30包括交替层叠的SiN子层和AlxGa1-xN子层，其中0＜x＜1。Fig. 1 is a schematic structural view of an epitaxial wafer of a light-emitting diode provided by an embodiment of the present invention. As shown in Fig. 1, the epitaxial wafer includes a buffer layer 20, a nucleation layer 30, an undoped GaN layer 40 , n-type layer 50 , multiple quantum well layer 60 and p-type layer 70 . FIG. 2 is a schematic diagram of a local structure of a nucleation layer provided by an embodiment of the present invention. As shown in FIG. 2 , the nucleation layer 30 includes alternately stacked SiN sublayers and AlxGa1-xNsublayers , where 0<x<1.
通过在缓冲层和未掺杂GaN层之间设置一层成核层，成核层包括交替层叠的SiN子层和AlxGa1-xN子层，AlxGa1-xN与蓝宝石衬底、GaN的晶格匹配较好，AlxGa1-xN层和SiN层交替层叠形成超晶格结构，GaN和蓝宝石衬底之间的晶格失配度降低，晶格缺陷减少，晶格质量提高。LED的可靠性和稳定性得以提升。而且可以避免应力的产生，改善外延片的翘曲度，提高发光效率和抗静电能力。另外，SiN层可以提供电子，有利于电流的扩展，降低外延片的正向电压，进一步提高发光效率。By setting a nucleation layer between the buffer layer and the undoped GaN layer, the nucleation layer includes alternately stacked SiN sub-layers and Alx Ga1-x N sub-layers, Alx Ga1-x N and sapphire substrate The substrate and GaN have better lattice matching. Alx Ga1-x N layers and SiN layers are alternately stacked to form a superlattice structure. The lattice mismatch between GaN and sapphire substrates is reduced, and the lattice defects are reduced. Quality improvement. LED reliability and stability are improved. Moreover, it can avoid the generation of stress, improve the warpage of the epitaxial wafer, and improve the luminous efficiency and antistatic ability. In addition, the SiN layer can provide electrons, which is beneficial to the expansion of the current, reduces the forward voltage of the epitaxial wafer, and further improves the luminous efficiency.
优选地，0.1≤x≤0.3，例如x＝0.1，AlxGa1-xN子层32中，Al的组分过低会导致成核层电阻过大，使正向电压升高，Al的组分过高会降低晶格的质量。Preferably, 0.1≤x≤0.3, for example, x=0.1, in the AlxGa1-xNsublayer 32, if the composition of Al is too low, the resistance of the nucleation layer will be too high, which will increase the forward voltage. Too high composition will reduce the quality of the lattice.
可选地，SiN子层的厚度可以为2～30nm，AlxGa1-xN子层的厚度可以为2～30nm。Optionally, the thickness of the SiN sub-layer may be 2-30 nm, and the thickness of the Alx Ga1-x N sub-layer may be 2-30 nm.
优选地，SiN子层31的厚度小于AlxGa1-xN子层32的厚度，有利于减小成核层30的总电阻，进一步降低正向电压。Preferably, the thickness of the SiN sublayer 31 is smaller than that of the AlxGa1-xNsublayer 32, which is beneficial to reduce the total resistance of the nucleation layer 30 and further reduce the forward voltage.
可选地，SiN子层31的厚度为6nm，AlxGa1-xN子层32的厚度为10nm。Optionally, the thickness of the SiN sub-layer 31 is 6 nm, and the thickness of the Alx Ga1-x N sub-layer 32 is 10 nm.
在本发明的另一种实现方式中，SiN子层31的厚度也可以等于AlxGa1-xN子层32的厚度，例如，SiN子层31的厚度和AlxGa1-xN子层32的厚度均为8nm。In another implementation of the present invention, the thickness of the SiN sublayer 31 can also be equal to the thickness of the AlxGa1-xNsublayer 32, for example, the thickness of the SiN sublayer 31 and the thickness of the AlxGa1-xN sublayer Layers 32 each have a thickness of 8 nm.
进一步地，成核层30的厚度大于或等于200nm，成核层30的厚度过薄则不能充分减少外延片中的晶格缺陷，同时会使得成核层30的方阻增大，不利于电流的横向扩展。Further, the thickness of the nucleation layer 30 is greater than or equal to 200nm, and if the thickness of the nucleation layer 30 is too thin, the lattice defects in the epitaxial wafer cannot be sufficiently reduced, and at the same time, the square resistance of the nucleation layer 30 will increase, which is not conducive to current flow. horizontal expansion.
可选地，SiN子层31和AlxGa1-xN子层32的层数相同，且SiN子层31的层数可以为10～80。Optionally, the number of layers of the SiN sublayer 31 and the AlxGa1-xNsublayer 32 is the same, and the number of layers of the SiN sublayer 31 may be 10-80.
优选地，SiN子层3的层数为40，SiN子层31和AlxGa1-xN子层32的层数过小无法有效降低外延片中的晶格缺陷，层数过大会使得生产过于复杂，增加制作成本。Preferably, the number of layers of the SiN sublayer 3 is 40, the number of layers of the SiN sublayer 31 and the AlxGa1-xNsublayer 32 is too small to effectively reduce the lattice defects in the epitaxial wafer, and the number of layers is too large to make the production It is too complicated and increases the production cost.
需要说明的是，图2中仅作为举例，示出了成核层中的部分结构，并不用以限制SiN子层和AlxGa1-xN子层交替的层数。It should be noted that FIG. 2 is only used as an example to show a part of the structure of the nucleation layer, and is not intended to limit the number of alternate layers of SiN sublayers and AlxGa1-xN sublayers.
此外，在生长SiN子层31时，控制流入反应腔的Si的流量为15毫升/分钟，流入反应腔的NH3的流量为30升/分钟。In addition, when growing the SiN sub-layer 31, the flow rate of Si flowing into the reaction chamber is controlled to be 15 ml/min, and the flow rate ofNH3 flowing into the reaction chamber is 30 liters/min.
可选地，在生长SiN子层31时，可以控制流入反应腔的Si的流量为15～20毫升/分钟，提高Si的流量，可以提高生长出的SiN子层31中Si的组分，有利于降低成核层60的电阻，降低正向电压，但Si的组分过高也会导致晶格质量下降。Optionally, when growing the SiN sub-layer 31, the flow rate of Si flowing into the reaction chamber can be controlled to be 15-20 ml/min, and the flow rate of Si can be increased to increase the composition of Si in the grown SiN sub-layer 31. It is beneficial to reduce the resistance of the nucleation layer 60 and reduce the forward voltage, but too high a composition of Si will also lead to a decrease in lattice quality.
图3是本发明实施例提供的一种多量子阱层的局部结构示意图，如图3所示，多量子阱层60包括多个交替的In0.2Ga0.8N阱层61和GaN垒层62。FIG. 3 is a schematic diagram of a partial structure of a multi-quantum well layer provided by an embodiment of the present invention. As shown in FIG. 3 , the multi-quantum well layer 60 includes a plurality of alternating In0.2 Ga0.8 N well layers 61 and GaN barrier layers 62 .
可选地，多量子阱层60的周期数为12～18，在本实施例中，多量子阱层60的周期数可以是15。Optionally, the number of periods of the multi-quantum well layer 60 is 12-18, and in this embodiment, the number of periods of the multi-quantum well layer 60 may be 15.
进一步地，In0.2Ga0.8N阱层61的厚度可以为2nm，GaN垒层62的厚度可以为13.5nm。Further, the thickness of the In0.2 Ga0.8 N well layer 61 may be 2 nm, and the thickness of the GaN barrier layer 62 may be 13.5 nm.
可选地，未掺杂GaN层40的厚度可以为1μm。Optionally, the thickness of the undoped GaN layer 40 may be 1 μm.
在本发明实施例的第一种实现方式中，成核层在氢气气氛中生长，成核层的生长压力为400torr，SiN子层的层数为40，AlxGa1-xN子层为Al0.1Ga0.9N层，Al0.1Ga0.9N层的厚度为10nm，SiN子层31的厚度为6nm，生长SiN子层时，控制Si的流量为15毫升/分钟，NH3的流量为30升/分钟，将上述外延片制成4×5mil的LED芯片，经过测试，其相比传统的LED芯片，正向电压从2.95V降低至2.85V，HBM(Human-Body Model，人体放电模式)下的抗静电能力从2000V提高到了4000V。In the first implementation of the embodiment of the present invention, the nucleation layer is grown in a hydrogen atmosphere, the growth pressure of the nucleation layer is 400torr, the number of SiN sublayers is 40, and the AlxGa1-xNsublayer is Al0.1 Ga0.9 N layer, the thickness of the Al0.1 Ga0.9 N layer is 10nm, the thickness of the SiN sublayer 31 is 6nm, when growing the SiN sublayer, control the flow rate of Si to be 15 ml/min, and the flow rate of NH to be30 liters / minute, the above-mentioned epitaxial wafer is made into a 4 × 5mil LED chip. After testing, compared with the traditional LED chip, the forward voltage is reduced from 2.95V to 2.85V, and the HBM (Human-Body Model, human body discharge mode) The antistatic ability of the battery has been increased from 2000V to 4000V.
在本发明实施例的第二种实现方式中，成核层在氢气气氛中生长，成核层的生长压力为400torr，SiN子层的层数为40，AlxGa1-xN子层为Al0.1Ga0.9N层，Al0.1Ga0.9N层和SiN子层的厚度均为8nm，生长SiN子层时，控制Si的流量为15毫升/分钟，NH3的流量为30升/分钟，将上述外延片制成4×5mil的LED芯片，经过测试，其正向电压降低至2.88V，HBM下的抗静电能力为4000V。In the second implementation of the embodiment of the present invention, the nucleation layer is grown in a hydrogen atmosphere, the growth pressure of the nucleation layer is 400torr, the number of layers of the SiN sublayer is 40, and the AlxGa1-xNsublayer is The thickness of the Al0.1 Ga0.9 N layer, the Al0.1 Ga0.9 N layer and the SiN sub-layer is 8 nm. When growing the SiN sub-layer, the flow rate of Si is controlled to be 15 ml/min, and the flow rate of NH3 is 30 liters/min. The above-mentioned epitaxial wafer is made into a 4×5 mil LED chip. After testing, its forward voltage is reduced to 2.88V, and the antistatic ability under HBM is 4000V.
在本发明实施例的第三种实现方式中，成核层在氢气气氛中生长，成核层的生长压力为400torr，SiN子层的层数为40，AlxGa1-xN子层为Al0.1Ga0.9N层，Al0.1Ga0.9N层的厚度为10nm，SiN子层31的厚度为6nm，生长SiN子层时，控制Si的流量为20毫升/分钟，NH3的流量为30升/分钟，将上述外延片制成4×5mil的LED芯片，经过测试，其正向电压降低至2.83V，HBM下的抗静电能力为4000V。In the third implementation of the embodiment of the present invention, the nucleation layer is grown in a hydrogen atmosphere, the growth pressure of the nucleation layer is 400torr, the number of SiN sublayers is 40, and the AlxGa1-xNsublayer is Al0.1 Ga0.9 N layer, the thickness of the Al0.1 Ga0.9 N layer is 10nm, the thickness of the SiN sublayer 31 is 6nm, when growing the SiN sublayer, control the flow rate of Si to be 20 ml/min, and the flow rate of NH to be30 liters The above-mentioned epitaxial wafer was made into a 4×5 mil LED chip. After testing, its forward voltage was reduced to 2.83V, and the antistatic ability under HBM was 4000V.
在本发明实施例的第四种实现方式中，成核层在氢气气氛中生长，成核层的生长压力为400torr，SiN子层的层数为60，AlxGa1-xN子层为Al0.1Ga0.9N层，Al0.1Ga0.9N层的厚度为5nm，SiN子层31的厚度为3nm，生长SiN子层时，控制Si的流量为15毫升/分钟，NH3的流量为30升/分钟，将上述外延片制成4×5mil的LED芯片，经过测试，其正向电压降低至2.80V，HBM下的抗静电能力为4000V。In the fourth implementation of the embodiment of the present invention, the nucleation layer is grown in a hydrogen atmosphere, the growth pressure of the nucleation layer is 400torr, the number of SiN sublayers is 60, and the AlxGa1-xNsublayer is Al0.1 Ga0.9 N layer, the thickness of the Al0.1 Ga0.9 N layer is 5nm, the thickness of the SiN sublayer 31 is 3nm, when growing the SiN sublayer, control the flow of Si to be 15 ml/min, and the flow of NH to be30 liters The above-mentioned epitaxial wafer was made into a 4×5 mil LED chip. After testing, its forward voltage was reduced to 2.80V, and the antistatic ability under HBM was 4000V.
在本发明实施例的第五种实现方式中，成核层在氢气气氛中生长，SiN子层的生长压力为500torr，AlxGa1-xN子层的生长压力为150torr，SiN子层的层数为60，AlxGa1-xN子层为Al0.1Ga0.9N层，Al0.1Ga0.9N层的厚度为5nm，SiN子层31的厚度为3nm，生长SiN子层时，控制Si流量为15毫升/分钟，NH3的流量为30升/分钟，将上述外延片制成4×5mil的LED芯片，经过测试，其正向电压降低至2.82V，HBM下的抗静电能力为6000V。In the fifth implementation of the embodiment of the present invention, the nucleation layer is grown in a hydrogen atmosphere, the growth pressure of the SiN sublayer is 500torr, the growth pressure of the AlxGa1-xN sublayer is 150torr, and the growth pressure of the SiN sublayer is The number of layers is 60, the Alx Ga1-x N sublayer is an Al0.1 Ga0.9 N layer, the thickness of the Al0.1 Ga0.9 N layer is 5nm, and the thickness of the SiN sublayer 31 is 3nm. When growing the SiN sublayer, control the Si The flow rate is 15 ml/min, and the flow rate ofNH3 is 30 liters/min. The above-mentioned epitaxial wafer is made into a 4×5 mil LED chip. After testing, its forward voltage is reduced to 2.82V, and the antistatic ability under HBM is 6000V .
在本发明实施例的第六种实现方式中，成核层在氢气气氛中生长，成核层的生长压力为400torr，SiN子层的层数为20，AlxGa1-xN子层为Al0.1Ga0.9N层，Al0.1Ga0.9N层的厚度为20nm，SiN子层31的厚度为10nm，生长SiN子层时，控制Si的流量为15毫升/分钟，NH3的流量为30升/分钟，将上述外延片制成4×5mil的LED芯片，经过测试，其正向电压降低至2.80V，HBM下的抗静电能力为6000V。In the sixth implementation of the embodiment of the present invention, the nucleation layer is grown in a hydrogen atmosphere, the growth pressure of the nucleation layer is 400torr, the number of SiN sublayers is 20, and the AlxGa1-xNsublayer is Al0.1 Ga0.9 N layer, the thickness of the Al0.1 Ga0.9 N layer is 20nm, the thickness of the SiN sublayer 31 is 10nm, when growing the SiN sublayer, control the flow rate of Si to be 15 ml/min, and the flow rate of NH to be30 liters The above-mentioned epitaxial wafer was made into a 4×5 mil LED chip. After testing, its forward voltage was reduced to 2.80V, and the antistatic ability under HBM was 6000V.
在本发明实施例的第七种实现方式中，成核层在氢气气氛中生长，成核层的生长压力为400torr，SiN子层的层数为40，AlxGa1-xN子层为Al0.3Ga0.7N层，Al0.1Ga0.9N层的厚度为10nm，SiN子层31的厚度为6nm，生长SiN子层时，控制Si的流量为15毫升/分钟，NH3的流量为30升/分钟，将上述外延片制成4×5mil的LED芯片，经过测试，其正向电压降低至2.82V，HBM下的抗静电能力为6000V。In the seventh implementation of the embodiment of the present invention, the nucleation layer is grown in a hydrogen atmosphere, the growth pressure of the nucleation layer is 400 torr, the number of SiN sublayers is 40, and the AlxGa1-xNsublayer is Al0.3 Ga0.7 N layer, the thickness of Al0.1 Ga0.9 N layer is 10nm, the thickness of SiN sublayer 31 is 6nm, when growing SiN sublayer, control the flow rate of Si to be 15 ml/min, the flow rate ofNH3 to be 30 liters The above-mentioned epitaxial wafer was made into a 4×5 mil LED chip. After testing, its forward voltage was reduced to 2.82V, and the antistatic ability under HBM was 6000V.
在本发明实施例的第八种实现方式中，在氢气气氛中生长SiN子层，在氮气与氢气的混合气氛中生长AlxGa1-xN子层，其中，氮气和氢气的摩尔比为2比8，成核层的生长压力为400torr，SiN子层的层数为40，AlxGa1-xN子层为Al0.1Ga0.9N层，Al0.1Ga0.9N层的厚度为10nm，SiN子层31的厚度为6nm，生长SiN子层时，控制Si的流量为15毫升/分钟，NH3的流量为30升/分钟，将上述外延片制成4×5mil的LED芯片，LED的可靠性和稳定性得以提升，正向电压得到降低，抗静电能力得到提升，经过测试，其正向电压降低至2.82V，HBM下的抗静电能力为4000V。In the eighth implementation of the embodiment of the present invention, the SiN sublayer is grown in a hydrogen atmosphere, and the AlxGa1-xN sublayer is grown in a mixed atmosphere of nitrogen and hydrogen, wherein the molar ratio of nitrogen to hydrogen is 2 to 8, the growth pressure of the nucleation layer is 400 torr, the number of SiN sublayers is 40, the Alx Ga1-x N sublayer is an Al0.1 Ga0.9 N layer, and the thickness of the Al0.1 Ga0.9 N layer is 10nm, The thickness of the SiN sub-layer 31 is 6nm. When growing the SiN sub-layer, the flow of controlling Si is 15 ml/min, and the flow of NH is30 liters/min. The above-mentioned epitaxial wafer is made into a 4×5 mil LED chip. The reliability and stability are improved, the forward voltage is reduced, and the antistatic ability is improved. After testing, the forward voltage is reduced to 2.82V, and the antistatic ability under HBM is 4000V.
图4是本发明实施例提供的一种发光二极管的外延片的制备方法的流程图，如图4所示，该制备方法包括：Fig. 4 is a flow chart of a method for preparing an epitaxial wafer of a light-emitting diode provided by an embodiment of the present invention. As shown in Fig. 4, the preparation method includes:
S11：提供一蓝宝石衬底。S11: Provide a sapphire substrate.
S12：在蓝宝石衬底上外延生长缓冲层。S12: epitaxially growing a buffer layer on the sapphire substrate.
S13：在缓冲层上生长成核层。S13: growing a nucleation layer on the buffer layer.
S14：在成核层上生长未掺杂GaN层。S14: growing an undoped GaN layer on the nucleation layer.
S15：在未掺杂GaN层上生长n型层。S15: growing an n-type layer on the undoped GaN layer.
S16：在n型层上生长多量子阱层。S16: growing multiple quantum well layers on the n-type layer.
S17：在多量子阱层上生长p型层。S17: growing a p-type layer on the multi-quantum well layer.
其中，成核层包括交替生长的SiN子层和AlxGa1-xN子层，其中0＜x＜1。Wherein, the nucleation layer includes alternately grown SiN sublayers and AlxGa1-xNsublayers , where 0<x<1.
通过在缓冲层和未掺杂GaN层之间设置一层成核层，成核层包括交替层叠的SiN子层和AlxGa1-xN子层，AlxGa1-xN与蓝宝石衬底、GaN的晶格匹配较好，AlxGa1-xN层和SiN层交替层叠形成超晶格结构，GaN和蓝宝石衬底之间的晶格失配度降低，晶格缺陷减少，晶格质量提高。LED的可靠性和稳定性得以提升。而且可以避免应力的产生，改善外延片的翘曲度，提高发光效率和抗静电能力。另外，SiN层可以提供电子，有利于电流的扩展，降低外延片的正向电压，进一步提高发光效率。By setting a nucleation layer between the buffer layer and the undoped GaN layer, the nucleation layer includes alternately stacked SiN sub-layers and Alx Ga1-x N sub-layers, Alx Ga1-x N and sapphire substrate The substrate and GaN have better lattice matching. Alx Ga1-x N layers and SiN layers are alternately stacked to form a superlattice structure. The lattice mismatch between GaN and sapphire substrates is reduced, and the lattice defects are reduced. Quality improvement. LED reliability and stability are improved. Moreover, it can avoid the generation of stress, improve the warpage of the epitaxial wafer, and improve the luminous efficiency and antistatic ability. In addition, the SiN layer can provide electrons, which is beneficial to the expansion of the current, reduces the forward voltage of the epitaxial wafer, and further improves the luminous efficiency.
图5是本发明实施例提供的另一种发光二极管的外延片的制备方法的流程图，如图5所示，该制备方法包括：Fig. 5 is a flow chart of another method for preparing an epitaxial wafer of a light-emitting diode provided by an embodiment of the present invention. As shown in Fig. 5, the preparation method includes:
S21：提供一蓝宝石衬底。S21: Provide a sapphire substrate.
在步骤S21中，可以对蓝宝石衬底进行清洁。In step S21, the sapphire substrate may be cleaned.
具体地，可以先将蓝宝石衬底在MOCVD(Meta1Organic Chemical VaporDeposition，金属有机化合物化学气相沉淀)反应腔中加热至1060℃，再在氢气气氛里对蓝宝石衬底进行退火处理以及氮化处理10分钟。Specifically, the sapphire substrate can be heated to 1060° C. in a MOCVD (Meta1Organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition) reaction chamber, and then the sapphire substrate is annealed and nitrided in a hydrogen atmosphere for 10 minutes.
S22：在蓝宝石衬底上外延生长缓冲层。S22: epitaxially growing a buffer layer on the sapphire substrate.
可选地，控制缓冲层的生长温度为600℃。Optionally, the growth temperature of the buffer layer is controlled to be 600°C.
实现时，可以将MOCVD反应腔的温度降低至600℃。When implemented, the temperature of the MOCVD reaction chamber can be lowered to 600°C.
可选地，在蓝宝石衬底上生长厚度为20nm的缓冲层，由于缓冲层没有掺杂，生长的缓冲层厚度过厚会增大外延片的正向电阻，使得正向电压升高，缩短外延片的寿命。Optionally, a buffer layer with a thickness of 20nm is grown on the sapphire substrate. Since the buffer layer is not doped, too thick a grown buffer layer will increase the forward resistance of the epitaxial wafer, which will increase the forward voltage and shorten the epitaxy. life of the tablet.
优选地，步骤S22还可以包括：Preferably, step S22 may also include:
对缓冲层进行退火处理。Anneal the buffer layer.
具体地，停止向MOCVD反应腔内通入氮化镓，将MOCVD反应腔的温度提高至1060℃进行退火，退火时间可以为5分钟。Specifically, stop feeding gallium nitride into the MOCVD reaction chamber, raise the temperature of the MOCVD reaction chamber to 1060° C. for annealing, and the annealing time may be 5 minutes.
S23：在缓冲层上生长成核层。S23: growing a nucleation layer on the buffer layer.
具体地，成核层包括交替生长的SiN子层和AlxGa1-xN子层，其中0＜x＜1。Specifically, the nucleation layer includes alternately grown SiN sublayers and AlxGa1-xNsublayers , where 0<x<1.
可选地，SiN子层的厚度可以为2～30nm，AlxGa1-xN子层的厚度可以为2～30nm。Optionally, the thickness of the SiN sub-layer may be 2-30 nm, and the thickness of the Alx Ga1-x N sub-layer may be 2-30 nm.
需要说明的是，SiN子层和AlxGa1-xN子层的厚度可以相同也可以不同。It should be noted that the thicknesses of the SiN sublayer and the AlxGa1-xN sublayer may be the same or different.
具体实施时，可以先在缓冲层上生长一层SiN子层，再在SiN子层上生长一层AlxGa1-xN子层，也可以先在缓冲层上生长一层AlxGa1-xN子层，再在AlxGa1-xN子层上生长一层SiN子层。In specific implementation, a SiN sublayer can be grown on the buffer layer first, and then an AlxGa1-xN sublayer can be grown on the SiN sublayer, or an AlxGa1-xN sublayer can be grown on the buffer layerfirst .-x N sublayer, and then grow a SiN sublayer on the Alx Ga1-x N sublayer.
进一步地，SiN子层和AlxGa1-xN子层的层数相同，且SiN子层的层数为10～80。Further, the number of layers of the SiN sub-layer and the Alx Ga1-x N sub-layer is the same, and the number of layers of the SiN sub-layer is 10-80.
可选地，SiN子层的层数为40，SiN子层和AlxGa1-xN子层的层数过小无法有效降低外延片中的晶格缺陷，层数过大会使得生产过于复杂，增加制作成本。Optionally, the number of layers of the SiN sublayer is 40, the number of layers of the SiN sublayer and the AlxGa1-xN sublayer is too small to effectively reduce the lattice defects in the epitaxial wafer, and the number of layers is too large to make the production too complicated , increasing the production cost.
可选地，SiN子层的生长压力可以为300～900torr，AlxGa1-xN子层的生长压力可以为100～900torr。Optionally, the growth pressure of the SiN sub-layer may be 300-900 torr, and the growth pressure of the Alx Ga1-x N sub-layer may be 100-900 torr.
此外，SiN子层和AlxGa1-xN子层的厚度可以随着SiN子层的层数的增加而减小，随着SiN子层的层数的减小而增加。例如，在SiN子层的层数为20时，SiN子层的厚度可以为10nm，AlxGa1-xN子层的厚度可以为20nm；在SiN子层的层数为40时，SiN子层的厚度可以为6nm，AlxGa1-xN子层的厚度可以为10nm；在SiN子层的层数增加到60时，SiN子层的厚度可以为3nm，AlxGa1-xN子层的厚度可以为5nm。In addition, the thicknesses of the SiN sublayer and the AlxGa1-xN sublayer can decrease as the number of SiN sublayers increases, and increase as the number of SiN sublayers decreases. For example, when the number of SiN sublayers is 20, the thickness of the SiN sublayer can be 10nm, and the thickness of the AlxGa1-xN sublayer can be 20nm; when the number of SiN sublayers is 40, the SiN sublayer The thickness of the layer can be 6nm, and the thickness of the Alx Ga1-x N sublayer can be 10nm; when the number of SiN sublayers increases to 60, the thickness of the SiN sublayer can be 3nm, and the Alx Ga1-x N The thickness of the sublayer may be 5 nm.
作为举例，SiN子层和AlxGa1-xN子层的生长压力均为400torr。As an example, the growth pressures of the SiN sublayer and the AlxGa1-xN sublayer are both 400torr.
优选地，成核层的厚度大于或等于200nm，成核层的厚度过薄则不能充分减少外延片中的晶格缺陷，同时会使得成核层的方阻增大，不利于电流的横向扩展。Preferably, the thickness of the nucleation layer is greater than or equal to 200nm. If the thickness of the nucleation layer is too thin, the lattice defects in the epitaxial wafer cannot be sufficiently reduced, and at the same time, the square resistance of the nucleation layer will increase, which is not conducive to the lateral expansion of the current. .
此外，可以在氢气气氛或氮氢混合气氛中生长成核层。In addition, the nucleation layer may be grown in a hydrogen atmosphere or a nitrogen-hydrogen mixed atmosphere.
在本实施例中，可以在氢气气氛中生长SiN子层和AlxGa1-xN子层，或者，在氢气气氛中生长SiN子层，在氮氢混合气氛中生长AlxGa1-xN子层，其中，氮气和氢气的摩尔比可以为2比8，在不同的气氛中分别生长SiN子层和AlxGa1-xN子层可以有利于提高成核层的质量。In this embodiment, the SiN sublayer and the AlxGa1-xNsublayer can be grown in a hydrogen atmosphere, or the SiN sublayer can be grown in a hydrogen atmosphere, and the AlxGa1-x layer can be grown in a nitrogen-hydrogen mixed atmosphere. The N sublayer, wherein the molar ratio of nitrogen and hydrogen can be 2 to 8, respectively growing the SiN sublayer and the AlxGa1-xNsublayer in different atmospheres can be beneficial to improve the quality of the nucleation layer.
优选地，0.1≤x≤0.3，AlxGa1-xN子层中，Al的组分过低会导致成核层电阻过大，使正向电压升高，Al的组分过高会降低晶格的质量。Preferably, 0.1≤x≤0.3, in the AlxGa1-xN sub-layer, if the composition of Al is too low, the resistance of the nucleation layer will be too high, which will increase the forward voltage, and if the composition of Al is too high, it will reduce The quality of the lattice.
可选地，在生长SiN子层31时，可以控制流入反应腔的Si的流量为15～20毫升/分钟，提高Si的流量，可以提高生长出的SiN子层中Si的组分，有利于降低成核层的电阻，降低正向电压，但Si的组分过高也会导致晶格质量下降。Optionally, when growing the SiN sublayer 31, the flow rate of Si flowing into the reaction chamber can be controlled to be 15-20 ml/min, and increasing the flow rate of Si can increase the composition of Si in the grown SiN sublayer, which is beneficial to Reduce the resistance of the nucleation layer and reduce the forward voltage, but too high a Si composition will also lead to a decrease in the quality of the lattice.
S24：在成核层上生长未掺杂GaN层。S24: growing an undoped GaN layer on the nucleation layer.
可选地，未掺杂GaN层的生长温度可以为1100℃。Optionally, the growth temperature of the undoped GaN layer may be 1100°C.
S25：在未掺杂GaN层上生长n型层。S25: growing an n-type layer on the undoped GaN layer.
可选地，n型层的生长速率可以为3.4μm/h，其生长厚度可以为2.5μm。Optionally, the growth rate of the n-type layer may be 3.4 μm/h, and its growth thickness may be 2.5 μm.
S26：在n型层上生长多量子阱层。S26: growing multiple quantum well layers on the n-type layer.
可选地，生长的多量子阱层可以是In0.2Ga0.8N/GaN，其中，In0.2Ga0.8N阱层的厚度可以为2nm，GaN垒层的厚度可以为13.5nm，多量子阱层的周期数可以为15。Optionally, the grown multi-quantum well layer can be In0.2 Ga0.8 N/GaN, wherein the thickness of the In0.2 Ga0.8 N well layer can be 2 nm, the thickness of the GaN barrier layer can be 13.5 nm, and the multi-quantum well layer The number of cycles can be 15.
S27：在多量子阱层上生长p型层。S27: growing a p-type layer on the multi-quantum well layer.
可选地，p型层的生长速率可以为0.3μm/h，其生长厚度可以为100nm。Optionally, the growth rate of the p-type layer may be 0.3 μm/h, and its growth thickness may be 100 nm.
对采用本发明实施例的制备方法制作的外延片进行清洗、镀膜、光刻等半导体工艺后，分割为4×5mil的LED芯片进行测试，其正向电压可以达到2.8～2.88V，HBM(Human-Body Model，人体放电模式)下的抗静电能力可以达到4000～6000V。The epitaxial wafer produced by the preparation method of the embodiment of the present invention is subjected to semiconductor processes such as cleaning, coating, and photolithography, and then divided into 4×5 mil LED chips for testing. The forward voltage can reach 2.8-2.88V, HBM (Human -Body Model, the antistatic capacity of the human body discharge model) can reach 4000~6000V.
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611057941.4ACN106601883A (en) | 2016-11-26 | 2016-11-26 | Epitaxial wafer of light emitting diode and preparation method |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611057941.4ACN106601883A (en) | 2016-11-26 | 2016-11-26 | Epitaxial wafer of light emitting diode and preparation method |
| Publication Number | Publication Date |
|---|---|
| CN106601883Atrue CN106601883A (en) | 2017-04-26 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611057941.4APendingCN106601883A (en) | 2016-11-26 | 2016-11-26 | Epitaxial wafer of light emitting diode and preparation method |
| Country | Link |
|---|---|
| CN (1) | CN106601883A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108336203A (en)* | 2017-12-29 | 2018-07-27 | 华灿光电(苏州）有限公司 | A kind of gallium nitride based LED epitaxial slice and its manufacturing method |
| CN110556454A (en)* | 2018-06-01 | 2019-12-10 | 上海新微技术研发中心有限公司 | Nitride epitaxial structure grown on silicon-based substrate and growth method thereof |
| CN110767785A (en)* | 2019-11-12 | 2020-02-07 | 佛山市国星半导体技术有限公司 | High-quality epitaxial structure and manufacturing method thereof |
| CN112289900A (en)* | 2020-09-16 | 2021-01-29 | 华灿光电(苏州）有限公司 | Ultraviolet light emitting diode epitaxial wafer and preparation method thereof |
| CN112786746A (en)* | 2020-12-31 | 2021-05-11 | 华灿光电（浙江）有限公司 | Epitaxial wafer of light emitting diode and preparation method thereof |
| CN116978991A (en)* | 2023-09-22 | 2023-10-31 | 江西兆驰半导体有限公司 | LED epitaxial wafer, preparation method thereof and LED |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617192A (en)* | 2015-01-22 | 2015-05-13 | 华灿光电(苏州）有限公司 | Manufacturing method of light emitting diode epitaxial wafer |
| CN105552186A (en)* | 2014-10-29 | 2016-05-04 | 南通同方半导体有限公司 | Blue LED epitaxial structure with suppression polarization effect barrier layer |
| CN105810725A (en)* | 2014-12-31 | 2016-07-27 | 中晟光电设备（上海）股份有限公司 | Silicon-based gallium nitride semiconductor wafer and manufacturing method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552186A (en)* | 2014-10-29 | 2016-05-04 | 南通同方半导体有限公司 | Blue LED epitaxial structure with suppression polarization effect barrier layer |
| CN105810725A (en)* | 2014-12-31 | 2016-07-27 | 中晟光电设备（上海）股份有限公司 | Silicon-based gallium nitride semiconductor wafer and manufacturing method thereof |
| CN104617192A (en)* | 2015-01-22 | 2015-05-13 | 华灿光电(苏州）有限公司 | Manufacturing method of light emitting diode epitaxial wafer |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108336203A (en)* | 2017-12-29 | 2018-07-27 | 华灿光电(苏州）有限公司 | A kind of gallium nitride based LED epitaxial slice and its manufacturing method |
| CN108336203B (en)* | 2017-12-29 | 2020-07-24 | 华灿光电(苏州）有限公司 | A kind of gallium nitride-based light-emitting diode epitaxial wafer and its manufacturing method |
| CN110556454A (en)* | 2018-06-01 | 2019-12-10 | 上海新微技术研发中心有限公司 | Nitride epitaxial structure grown on silicon-based substrate and growth method thereof |
| CN110556454B (en)* | 2018-06-01 | 2021-08-03 | 上海新微技术研发中心有限公司 | Nitride epitaxial structure grown on silicon base substrate and its growth method |
| CN110767785A (en)* | 2019-11-12 | 2020-02-07 | 佛山市国星半导体技术有限公司 | High-quality epitaxial structure and manufacturing method thereof |
| CN112289900A (en)* | 2020-09-16 | 2021-01-29 | 华灿光电(苏州）有限公司 | Ultraviolet light emitting diode epitaxial wafer and preparation method thereof |
| CN112289900B (en)* | 2020-09-16 | 2021-10-08 | 华灿光电(苏州）有限公司 | Ultraviolet light emitting diode epitaxial wafer and preparation method thereof |
| CN112786746A (en)* | 2020-12-31 | 2021-05-11 | 华灿光电（浙江）有限公司 | Epitaxial wafer of light emitting diode and preparation method thereof |
| CN112786746B (en)* | 2020-12-31 | 2024-02-13 | 华灿光电（浙江）有限公司 | Epitaxial wafer of light-emitting diode and preparation method thereof |
| CN116978991A (en)* | 2023-09-22 | 2023-10-31 | 江西兆驰半导体有限公司 | LED epitaxial wafer, preparation method thereof and LED |
| CN116978991B (en)* | 2023-09-22 | 2023-12-12 | 江西兆驰半导体有限公司 | LED epitaxial wafer, preparation method thereof and LED |
| Publication | Publication Date | Title |
|---|---|---|
| CN102368519B (en) | A kind of method improving semiconductor diode multiple quantum well light emitting efficiency | |
| CN106057988B (en) | A kind of preparation method of the epitaxial wafer of GaN base light emitting | |
| CN106601883A (en) | Epitaxial wafer of light emitting diode and preparation method | |
| CN105405939B (en) | A kind of light emitting diode and its manufacture method | |
| CN106129207A (en) | Epitaxial wafer of gallium nitride-based light-emitting diode and preparation method | |
| CN107331745A (en) | Epitaxial wafer of light emitting diode and preparation method thereof | |
| CN108336198B (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| CN102738328B (en) | Epitaxial wafer of light-emitting diode and manufacturing method thereof | |
| CN109103303B (en) | Method for preparing light-emitting diode epitaxial wafer and light-emitting diode epitaxial wafer | |
| CN117393667B (en) | Light-emitting diode epitaxial wafer and preparation method thereof, LED | |
| CN103904177B (en) | LED epitaxial slice and its manufacture method | |
| CN107452843A (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN106653971B (en) | Epitaxial wafer of GaN-based light emitting diode and growth method thereof | |
| CN106711295A (en) | Growth method of GaN-based light emitting diode epitaxial wafer | |
| CN109545918B (en) | A kind of gallium nitride-based light-emitting diode epitaxial wafer and preparation method thereof | |
| CN116190520A (en) | LED epitaxial wafer for improving wavelength yield, preparation method thereof and LED chip | |
| CN106972083A (en) | Preparation method of epitaxial wafer of light-emitting diode | |
| CN106098874B (en) | Epitaxial wafer of light emitting diode and preparation method | |
| CN106848017B (en) | Epitaxial wafer of GaN-based light emitting diode and growth method thereof | |
| CN108987544A (en) | A kind of LED epitaxial slice and its manufacturing method | |
| CN108695416A (en) | A kind of LED epitaxial slice and preparation method thereof | |
| CN105870278B (en) | A kind of gallium nitride based light emitting diode and preparation method thereof | |
| CN104993027A (en) | Light emitting diode epitaxial wafer and manufacturing method therefor | |
| CN117410402B (en) | Light-emitting diode epitaxial wafer, preparation method thereof and Micro-LED chip | |
| CN108630791A (en) | GaN-based light-emitting diode epitaxial wafer and manufacturing method thereof |
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | Application publication date:20170426 | |
| RJ01 | Rejection of invention patent application after publication |