技术领域technical field
本发明涉及显示技术领域，更为具体的说，涉及一种移位寄存单元、栅极驱动电路及显示装置。The present invention relates to the field of display technology, and more specifically, to a shift register unit, a gate drive circuit and a display device.
背景技术Background technique
随着电子技术的发展，显示装置已被广泛应用于各行领域和各种电子产品中，成为人们生活和工作不可或缺的一部分，如电视、手机、电脑、个人数字助理等。现有的显示装置中，显示装置包括有栅极驱动电路，栅极驱动电路主要用于扫描多级栅极线，以通过扫描栅极线而对与栅极线电连接的像素阵列进行扫描，进而配合其他线路结构而进行画面的显示。由于人们对栅极驱动电路的多样性的需求，因此栅极驱动电路的设计成为开发者现今主要研究趋势之一。With the development of electronic technology, display devices have been widely used in various fields and various electronic products, and become an indispensable part of people's life and work, such as televisions, mobile phones, computers, personal digital assistants, etc. In the existing display device, the display device includes a gate driving circuit, and the gate driving circuit is mainly used for scanning multi-level gate lines, so as to scan the pixel array electrically connected to the gate lines by scanning the gate lines, And then cooperate with other line structures to display the screen. Due to people's demand for the diversity of gate driving circuits, the design of gate driving circuits has become one of the main research trends of developers today.
发明内容Contents of the invention
有鉴于此，本发明提供了一种移位寄存单元、栅极驱动电路及显示装置，将移位寄存单元与栅极线连接的端口和与上下级移位寄存单元连接的端口区分，即，将扫描输出端作为连接栅极线的端口，而将级联输出端作为连接上下级移位寄存单元的端口，满足栅极驱动电路的多样性的设计。In view of this, the present invention provides a shift register unit, a gate drive circuit, and a display device, which distinguish the ports connected to the gate lines of the shift register unit from the ports connected to the upper and lower shift register units, that is, The scanning output terminal is used as a port connected to the gate line, and the cascaded output terminal is used as a port connected to the upper and lower shift register units, so as to meet the diversity design of the gate driving circuit.
为实现上述目的，本发明提供的技术方案如下：In order to achieve the above object, the technical scheme provided by the invention is as follows:
一种移位寄存单元，应用于栅极驱动电路，包括：输入模块、上拉节点、上拉控制模块、第一下拉节点、第一下拉控制模块、第一下拉生成模块、第二下拉节点、第二下拉控制模块、第二下拉生成模块、扫描输出模块、扫描输出端、级联输出模块、级联输出端和电容；A shift register unit, applied to a gate drive circuit, comprising: an input module, a pull-up node, a pull-up control module, a first pull-down node, a first pull-down control module, a first pull-down generating module, a second A pull-down node, a second pull-down control module, a second pull-down generating module, a scan output module, a scan output terminal, a cascade output module, a cascade output terminal and a capacitor;
其中，所述输入模块响应于第一控制端的电位而控制第一电压端与所述上拉节点的接通状态，以及，响应于第二控制端的电位而控制第二电压端与所述上拉节点的接通状态，其中，所述第一电压端和所述第二电压端的输出电平极性相反；Wherein, the input module controls the connected state of the first voltage terminal and the pull-up node in response to the potential of the first control terminal, and controls the connection state of the second voltage terminal and the pull-up node in response to the potential of the second control terminal. an on-state of the node, wherein the output levels of the first voltage terminal and the second voltage terminal have opposite polarities;
所述上拉控制模块响应于所述上拉节点的电位而控制第三电压端分别与所述第一下拉节点和所述第二下拉节点的接通状态；The pull-up control module controls the on-states of the third voltage terminal and the first pull-down node and the second pull-down node respectively in response to the potential of the pull-up node;
所述第一下拉控制模块响应于所述第一下拉节点的电位而控制所述第四电压端与所述扫描输出端的接通状态，以及，控制所述第三电压端分别与所述上拉节点和所述级联输出端的接通状态，其中，所述第三电压端和所述第四电压端输出电平相同，且所述第三电压端输出电压低于所述第四电压端输出电压；The first pull-down control module controls the on-state of the fourth voltage terminal and the scan output terminal in response to the potential of the first pull-down node, and controls the connection between the third voltage terminal and the scan output terminal respectively. The on-state of the pull-up node and the cascade output terminal, wherein the output levels of the third voltage terminal and the fourth voltage terminal are the same, and the output voltage of the third voltage terminal is lower than the fourth voltage terminal output voltage;
所述第一下拉生成模块响应于第一信号端的电位而控制所述第三电压端与所述第一下拉节点的接通状态，以及，响应于第二信号端的电位而控制所述第二信号端与所述第一下拉节点的接通状态，其中，所述第一信号端和所述第二信号端的输出信号为互补时钟信号，且在所述上拉控制模块控制所述第三电压端与所述第一下拉节点接通时，所述第一下拉节点的电位为所述第三电压端的输出电位；The first pull-down generation module controls the connection state of the third voltage terminal and the first pull-down node in response to the potential of the first signal terminal, and controls the first pull-down node in response to the potential of the second signal terminal. The connected state of the two signal terminals and the first pull-down node, wherein the output signals of the first signal terminal and the second signal terminal are complementary clock signals, and the pull-up control module controls the first pull-down node When the three voltage terminals are connected to the first pull-down node, the potential of the first pull-down node is the output potential of the third voltage terminal;
所述第二下拉控制模块响应于所述第二下拉节点的电位而控制所述第四电压端与所述扫描输出端的接通状态，以及，控制所述第三电压端分别与所述上拉节点和所述级联输出端的接通状态；The second pull-down control module controls the on-state of the fourth voltage terminal and the scan output terminal in response to the potential of the second pull-down node, and controls the connection between the third voltage terminal and the pull-up terminal respectively. on-states of nodes and outputs of said cascade;
所述第二下拉生成模块响应于所述第二信号端的电位而控制所述第三电压端与所述第二下拉节点的接通状态，以及，响应于所述第一信号端的电位而控制所述第一信号端与所述第二下拉节点的接通状态，其中，在所述上拉控制模块控制所述第三电压端与所述第二下拉节点接通时，所述第二下拉节点的电位为所述第三电压端的电位；The second pull-down generation module controls the connection state of the third voltage terminal and the second pull-down node in response to the potential of the second signal terminal, and controls the connected state of the second pull-down node in response to the potential of the first signal terminal. The connected state of the first signal terminal and the second pull-down node, wherein, when the pull-up control module controls the connection between the third voltage terminal and the second pull-down node, the second pull-down node The potential of is the potential of the third voltage terminal;
所述扫描输出模块响应于所述上拉节点的电位而控制时钟信号端与扫描输出端的接通状态；The scan output module controls the connection state of the clock signal terminal and the scan output terminal in response to the potential of the pull-up node;
所述级联输出模块响应于所述上拉节点的电位而控制时钟信号端与级联输出端的接通状态；The cascade output module controls the on-state of the clock signal terminal and the cascade output terminal in response to the potential of the pull-up node;
以及，所述电容用于将所述扫描输出端的电位耦合至所述上拉节点。And, the capacitor is used to couple the potential of the scanning output terminal to the pull-up node.
可选的，所述输入模块包括：第一晶体管和第二晶体管；Optionally, the input module includes: a first transistor and a second transistor;
其中，所述第一晶体管的栅极连接至所述第一控制端，所述第一晶体管的第一端连接至所述第一电压端，所述第一晶体管的第二端连接至所述上拉节点；所述第二晶体管的栅极连接至所述第二控制端，所述第二晶体管的第一端连接至所述第二电压端，所述第二晶体管的第二端连接至所述上拉节点。Wherein, the gate of the first transistor is connected to the first control terminal, the first terminal of the first transistor is connected to the first voltage terminal, and the second terminal of the first transistor is connected to the pull-up node; the gate of the second transistor is connected to the second control terminal, the first terminal of the second transistor is connected to the second voltage terminal, and the second terminal of the second transistor is connected to the pull-up node.
可选的，所述上拉控制模块包括：第三晶体管和第四晶体管；Optionally, the pull-up control module includes: a third transistor and a fourth transistor;
其中，所述第三晶体管和第四晶体管的栅极均连接至所述上拉节点，所述第三晶体管和第四晶体管的第一端均连接至所述第三电压端，所述第三晶体管的第二端连接至所述第一下拉节点，所述第四晶体管的第二端连接至所述第二下拉节点。Wherein, the gates of the third transistor and the fourth transistor are both connected to the pull-up node, the first terminals of the third transistor and the fourth transistor are both connected to the third voltage terminal, and the third The second end of the transistor is connected to the first pull-down node, and the second end of the fourth transistor is connected to the second pull-down node.
可选的，所述第一下拉控制模块包括：第五晶体管、第六晶体管和第七晶体管；Optionally, the first pull-down control module includes: a fifth transistor, a sixth transistor, and a seventh transistor;
其中，所述第五晶体管、第六晶体管和第七晶体管的栅极均连接至所述第一下拉节点，所述第五晶体管的第一端连接至所述第四电压端，所述第五晶体管的第二端连接至所述扫描输出端，所述第六晶体管的第一端连接至所述第三电压端，所述第六晶体管的第二端连接至所述上拉节点，所述第七晶体管的第一端连接至所述第三电压端，所述第七晶体管的第二端连接至所述级联输出端。Wherein, the gates of the fifth transistor, the sixth transistor and the seventh transistor are all connected to the first pull-down node, the first terminal of the fifth transistor is connected to the fourth voltage terminal, and the first The second terminal of the fifth transistor is connected to the scan output terminal, the first terminal of the sixth transistor is connected to the third voltage terminal, and the second terminal of the sixth transistor is connected to the pull-up node, so The first terminal of the seventh transistor is connected to the third voltage terminal, and the second terminal of the seventh transistor is connected to the cascaded output terminal.
可选的，所述第一下拉生成模块包括：第八晶体管和第九晶体管；Optionally, the first pull-down generation module includes: an eighth transistor and a ninth transistor;
其中，所述第八晶体管的栅极连接至所述第一信号端，所述第八晶体管的第一端连接至所述第三电压端，所述第八晶体管的第二端连接至所述第一下拉节点，所述第九晶体管的栅极连接至所述第二信号端，所述第九晶体管的第一端连接至所述第二信号端，所述第九晶体管的第二端连接至所述第一下拉节点。Wherein, the gate of the eighth transistor is connected to the first signal terminal, the first terminal of the eighth transistor is connected to the third voltage terminal, and the second terminal of the eighth transistor is connected to the The first pull-down node, the gate of the ninth transistor is connected to the second signal terminal, the first terminal of the ninth transistor is connected to the second signal terminal, and the second terminal of the ninth transistor Connect to the first pull-down node.
可选的，所述第二下拉控制模块包括：第十晶体管、第十一晶体管和第十二晶体管；Optionally, the second pull-down control module includes: a tenth transistor, an eleventh transistor, and a twelfth transistor;
其中，所述第十晶体管、第十一晶体管和第十二晶体管的栅极均连接至所述第二下拉节点，所述第十晶体管的第一端连接至所述第四电压端，所述第十晶体管的第二端连接至所述扫描输出端，所述第十一晶体管的第一端连接至所述第三电压端，所述第十一晶体管的第二端连接至所述上拉节点，所述第十二晶体管的第一端连接至所述第三电压端，所述第十二晶体管的第二端连接至所述级联输出端。Wherein, the gates of the tenth transistor, the eleventh transistor and the twelfth transistor are all connected to the second pull-down node, the first terminal of the tenth transistor is connected to the fourth voltage terminal, and the The second end of the tenth transistor is connected to the scan output end, the first end of the eleventh transistor is connected to the third voltage end, and the second end of the eleventh transistor is connected to the pull-up node, the first end of the twelfth transistor is connected to the third voltage end, and the second end of the twelfth transistor is connected to the cascade output end.
可选的，所述第二下拉生成模块包括：第十三晶体管和第十四晶体管；Optionally, the second pull-down generation module includes: a thirteenth transistor and a fourteenth transistor;
其中，所述第十三晶体管的栅极连接至所述第二信号端，所述第十三晶体管的第一端连接至所述第三电压端，所述第十三晶体管的第二端连接至所述第二下拉节点，所述第十四晶体管的栅极连接至所述第一信号端，所述第十四晶体管的第一端连接至所述第一信号端，所述第十四晶体管的第二端连接至所述第二下拉节点。Wherein, the gate of the thirteenth transistor is connected to the second signal terminal, the first terminal of the thirteenth transistor is connected to the third voltage terminal, and the second terminal of the thirteenth transistor is connected to to the second pull-down node, the gate of the fourteenth transistor is connected to the first signal terminal, the first terminal of the fourteenth transistor is connected to the first signal terminal, and the fourteenth transistor The second end of the transistor is connected to the second pull-down node.
可选的，所述扫描输出模块包括：第十五晶体管，所述第十五晶体管的栅极连接至所述上拉节点，所述第十五晶体管的第一端连接至所述时钟信号端，所述第十五晶体管的第二端连接至所述扫描输出端。Optionally, the scan output module includes: a fifteenth transistor, the gate of the fifteenth transistor is connected to the pull-up node, and the first terminal of the fifteenth transistor is connected to the clock signal terminal , the second terminal of the fifteenth transistor is connected to the scanning output terminal.
可选的，所述级联输出模块包括：第十六晶体管，所述第十六晶体管的栅极连接至所述上拉节点，所述第十六晶体管的第一端连接至所述时钟信号端，所述第十六晶体管的第二端连接至所述级联输出端。Optionally, the cascade output module includes: a sixteenth transistor, the gate of the sixteenth transistor is connected to the pull-up node, and the first end of the sixteenth transistor is connected to the clock signal end, the second end of the sixteenth transistor is connected to the cascade output end.
可选的，所述第一信号端和第二信号端的电平与所述第三电压端的电平相同时，所述第一信号端和第二信号端输出电压与所述第三电压端输出电压相同。Optionally, when the levels of the first signal terminal and the second signal terminal are the same as the level of the third voltage terminal, the output voltages of the first signal terminal and the second signal terminal are the same as the output voltages of the third voltage terminal. same voltage.
可选的，所述时钟信号端的电平与所述第四电压端的电平相同时，所述时钟信号端输出电压与所述第四电压端输出电压相同。Optionally, when the level of the clock signal terminal is the same as the level of the fourth voltage terminal, the output voltage of the clock signal terminal is the same as the output voltage of the fourth voltage terminal.
可选的，在所述栅极驱动电路沿第一方向扫描时，所述第一控制端输出开启信号；Optionally, when the gate drive circuit scans along the first direction, the first control terminal outputs an enable signal;
以及，在所述栅极驱动电路沿第二方向扫描时，所述第二控制端输出开启信号，其中，所述第一方向和第二方向相反。And, when the gate driving circuit scans along a second direction, the second control terminal outputs a turn-on signal, wherein the first direction is opposite to the second direction.
可选的，所述第一信号端和第二信号端的输出信号均为帧反转信号。Optionally, the output signals of the first signal terminal and the second signal terminal are frame inversion signals.
相应的，本发明还提供了一种栅极驱动电路，包括N级移位寄存单元，每级所述移位寄存单元均为上述的移位寄存单元。Correspondingly, the present invention also provides a gate drive circuit, comprising N stages of shift register units, and the shift register units of each stage are the aforementioned shift register units.
可选的，定义相邻两级移位寄存单元为第i级移位寄存单元和第i+1级移位寄存单元，其中，Optionally, two adjacent shift register units are defined as the i-th shift register unit and the i+1-th shift register unit, wherein,
所述第i级移位寄存单元的级联输出端连接至所述第i+1级移位寄存单元的第一控制端，以及，所述第i+1级移位寄存单元的级联输出端连接至所述第i级移位寄存单元的第二控制端。The cascade output terminal of the i-th stage shift register unit is connected to the first control terminal of the i+1-th stage shift register unit, and the cascade output of the i+1-th stage shift register unit The terminal is connected to the second control terminal of the i-th stage shift register unit.
相应的，本发明还提供了一种显示装置，所述显示装置包括上述的栅极驱动电路。Correspondingly, the present invention also provides a display device, which includes the above-mentioned gate driving circuit.
相较于现有技术，本发明提供的技术方案至少具有以下优点：Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:
本发明提供了一种移位寄存单元、栅极驱动电路及显示装置，应用于栅极驱动电路，包括：输入模块、上拉节点、上拉控制模块、第一下拉节点、第一下拉控制模块、第一下拉生成模块、第二下拉节点、第二下拉控制模块、第二下拉生成模块、扫描输出模块、扫描输出端、级联输出模块、级联输出端和电容；其中，通过各个模块之间的相互配合，使得扫描输出端输出扫描信号至与其连接的栅极线，同时，使得级联输出端输出信号至与其连接的上下级移位寄存单元。由上述内容可知，本发明提供的技术方案，将移位寄存单元与栅极线连接的端口和与上下级移位寄存单元连接的端口区分，即，将扫描输出端作为连接栅极线的端口，而将级联输出端作为连接上下级移位寄存单元的端口，满足栅极驱动电路的多样性的设计。The invention provides a shift register unit, a gate drive circuit and a display device, which are applied to the gate drive circuit, including: an input module, a pull-up node, a pull-up control module, a first pull-down node, a first pull-down A control module, a first pull-down generation module, a second pull-down node, a second pull-down control module, a second pull-down generation module, a scan output module, a scan output terminal, a cascade output module, a cascade output terminal, and a capacitor; wherein, by The mutual cooperation between the various modules makes the scanning output end output the scanning signal to the gate line connected thereto, and at the same time makes the cascade output end output the signal to the upper and lower shift register units connected thereto. It can be seen from the above that the technical solution provided by the present invention distinguishes the port connecting the shift register unit to the gate line from the port connected to the upper and lower shift register units, that is, the scan output terminal is used as the port connected to the gate line , and the cascaded output terminal is used as a port connecting the upper and lower shift register units to meet the diversity design of the gate drive circuit.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.
图1为本申请实施例提供的一种移位寄存单元的结构示意图；FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present application;
图2为本申请实施例提供的另一种移位寄存单元的结构示意图；FIG. 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present application;
图3为本申请实施例提供的一种沿第一方向扫描的时序图；FIG. 3 is a timing diagram of scanning along the first direction provided by the embodiment of the present application;
图4为本申请实施例提供的一种沿第二方向扫描的时序图；FIG. 4 is a timing diagram of scanning along the second direction provided by the embodiment of the present application;
图5为本申请实施例提供的一种栅极驱动电路的结构示意图；FIG. 5 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present application;
图6为本申请实施例提供的一种显示装置的结构示意图。FIG. 6 is a schematic structural diagram of a display device provided by an embodiment of the present application.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
正如背景技术所述，现有的显示装置中，显示装置包括有栅极驱动电路，栅极驱动电路主要用于扫描多级栅极线，以通过扫描栅极线而对与栅极线电连接的像素阵列进行扫描，进而配合其他线路结构而进行画面的显示。由于人们对栅极驱动电路的多样性的需求，因此栅极驱动电路的设计成为开发者现今主要研究趋势之一。As described in the background, in the existing display device, the display device includes a gate driving circuit, and the gate driving circuit is mainly used for scanning multi-level gate lines, so as to electrically connect with the gate lines by scanning the gate lines. The pixel array scans, and then cooperates with other circuit structures to display the screen. Due to people's demand for the diversity of gate driving circuits, the design of gate driving circuits has become one of the main research trends of developers today.
基于此，本申请实施例提供了一种移位寄存单元、栅极驱动电路及显示装置，将移位寄存单元与栅极线连接的端口和与上下级移位寄存单元连接的端口区分，即，将扫描输出端作为连接栅极线的端口，而将级联输出端作为连接上下级移位寄存单元的端口，满足栅极驱动电路的多样性的设计。为实现上述目的，本申请实施例提供的技术方案如下，具体结合图1至图6所示，对本申请实施例提供的技术方案进行详细的描述。Based on this, an embodiment of the present application provides a shift register unit, a gate drive circuit, and a display device, which distinguishes the port connecting the shift register unit to the gate line and the port connected to the upper and lower shift register units, that is, , the scan output terminal is used as a port connected to the gate line, and the cascaded output terminal is used as a port connected to the upper and lower shift register units, so as to meet the diversity design of the gate drive circuit. In order to achieve the above purpose, the technical solutions provided by the embodiments of the present application are as follows. Specifically, referring to FIG. 1 to FIG. 6 , the technical solutions provided by the embodiments of the present application are described in detail.
参考图1所示，为本申请实施例提供的一种移位寄存单元的结构示意图，其中，移位寄存单元应用于栅极驱动电路，移位寄存单元包括：Referring to FIG. 1 , it is a schematic structural diagram of a shift register unit provided in an embodiment of the present application, wherein the shift register unit is applied to a gate drive circuit, and the shift register unit includes:
输入模块100、上拉节点P、上拉控制模块200、第一下拉节点Q1、第一下拉控制模块301、第一下拉生成模块401、第二下拉节点Q2、第二下拉控制模块302、第二下拉生成模块402、扫描输出模块500、扫描输出端Gout、级联输出模块600、级联输出端Gout_sub和电容C；Input module 100, pull-up node P, pull-up control module 200, first pull-down node Q1, first pull-down control module 301, first pull-down generation module 401, second pull-down node Q2, second pull-down control module 302 , the second pull-down generation module 402, the scan output module 500, the scan output terminal Gout, the cascaded output module 600, the cascaded output terminal Gout_sub and the capacitor C;
其中，所述输入模块100响应于第一控制端SET的电位而控制第一电压端DIR1与所述上拉节点P的接通状态，以及，响应于第二控制端RESET的电位而控制第二电压端DIR2与所述上拉节点P的接通状态，其中，所述第一电压端DIR1和所述第二电压端DIR2的输出电平极性相反；Wherein, the input module 100 controls the connected state of the first voltage terminal DIR1 and the pull-up node P in response to the potential of the first control terminal SET, and controls the second voltage terminal DIR1 in response to the potential of the second control terminal RESET. The on state of the voltage terminal DIR2 and the pull-up node P, wherein the output levels of the first voltage terminal DIR1 and the second voltage terminal DIR2 have opposite polarities;
所述上拉控制模块200响应于所述上拉节点P的电位而控制第三电压端V3分别与所述第一下拉节点Q1和所述第二下拉节点Q2的接通状态；The pull-up control module 200 controls the connected states of the third voltage terminal V3 and the first pull-down node Q1 and the second pull-down node Q2 respectively in response to the potential of the pull-up node P;
所述第一下拉控制模块301响应于所述第一下拉节点Q1的电位而控制所述第四电压端V4与所述扫描输出端Gout的接通状态，以及，控制所述第三电压端V3分别与所述上拉节点P和所述级联输出端Gout_sub的接通状态，其中，所述第三电压端V3和所述第四电压端V4输出电平相同，且所述第三电压端V3输出电压低于所述第四电压端V4输出电压；需要说明的是，第三电压端V3和第四电压端V4输出电平相同，是指同时输出相比参考电压为正性的电压，或者负性的电压，即电压的相位相同。The first pull-down control module 301 controls the on-state of the fourth voltage terminal V4 and the scanning output terminal Gout in response to the potential of the first pull-down node Q1, and controls the third voltage Terminal V3 is connected to the on-state of the pull-up node P and the cascaded output terminal Gout_sub respectively, wherein the output levels of the third voltage terminal V3 and the fourth voltage terminal V4 are the same, and the third voltage terminal V3 and the fourth voltage terminal V4 have the same output level, and the third voltage terminal V3 The output voltage of the voltage terminal V3 is lower than the output voltage of the fourth voltage terminal V4; it should be noted that the output levels of the third voltage terminal V3 and the fourth voltage terminal V4 are the same, which means that the simultaneous output is positive compared to the reference voltage. Voltage, or negative voltage, that is, the phase of the voltage is the same.
所述第一下拉生成模块401响应于第一信号端Clock1的电位而控制所述第三电压端V3与所述第一下拉节点Q1的接通状态，以及，响应于第二信号端Clock2的电位而控制所述第二信号端Clock2与所述第一下拉节点Q1的接通状态，其中，所述第一信号端Clock1和所述第二信号端Clock2的输出信号为互补时钟信号，且在所述上拉控制模块200控制所述第三电压端V3与所述第一下拉节点Q1接通时，所述第一下拉节点Q1的电位为所述第三电压端V3的输出电位；The first pull-down generating module 401 controls the on-state of the third voltage terminal V3 and the first pull-down node Q1 in response to the potential of the first signal terminal Clock1, and, in response to the potential of the second signal terminal Clock2 potential to control the on-state of the second signal terminal Clock2 and the first pull-down node Q1, wherein the output signals of the first signal terminal Clock1 and the second signal terminal Clock2 are complementary clock signals, And when the pull-up control module 200 controls the connection between the third voltage terminal V3 and the first pull-down node Q1, the potential of the first pull-down node Q1 is the output of the third voltage terminal V3 Potential;
所述第二下拉控制模块302响应于所述第二下拉节点Q2的电位而控制所述第四电压端V4与所述扫描输出端Gout的接通状态，以及，控制所述第三电压端V3分别与所述上拉节点P和所述级联输出端Gout_sub的接通状态；The second pull-down control module 302 controls the connected state of the fourth voltage terminal V4 and the scanning output terminal Gout in response to the potential of the second pull-down node Q2, and controls the third voltage terminal V3 Respectively connected states with the pull-up node P and the cascaded output terminal Gout_sub;
所述第二下拉生成模块402响应于所述第二信号端Clock2的电位而控制所述第三电压端V3与所述第二下拉节点Q2的接通状态，以及，响应于所述第一信号端Clock1的电位而控制所述第一信号端Clock1与所述第二下拉节点Q2的接通状态，其中，在所述上拉控制模块200控制所述第三电压端V3与所述第二下拉节点Q2接通时，所述第二下拉节点Q2的电位为所述第三电压端V3的电位；The second pull-down generating module 402 controls the on-state of the third voltage terminal V3 and the second pull-down node Q2 in response to the potential of the second signal terminal Clock2, and, in response to the first signal The potential of the terminal Clock1 controls the on-state of the first signal terminal Clock1 and the second pull-down node Q2, wherein the pull-up control module 200 controls the third voltage terminal V3 and the second pull-down node Q2 When the node Q2 is turned on, the potential of the second pull-down node Q2 is the potential of the third voltage terminal V3;
所述扫描输出模块500响应于所述上拉节点P的电位而控制时钟信号端CK与扫描输出端Gout的接通状态；The scan output module 500 controls the on-state of the clock signal terminal CK and the scan output terminal Gout in response to the potential of the pull-up node P;
所述级联输出模块600响应于所述上拉节点P的电位而控制时钟信号端CK与级联输出端Gout_sub的接通状态；The cascade output module 600 controls the on-state of the clock signal terminal CK and the cascade output terminal Gout_sub in response to the potential of the pull-up node P;
以及，所述电容C用于将所述扫描输出端Gout的电位耦合至所述上拉节点P。And, the capacitor C is used to couple the potential of the scanning output terminal Gout to the pull-up node P.
本申请实施例提供的技术方案，通过各个模块之间的相互配合，使得扫描输出端输出扫描信号至与其连接的栅极线，同时，使得级联输出端输出信号至与其连接的上下级移位寄存单元，其中，将移位寄存单元与栅极线连接的端口和与上下级移位寄存单元连接的端口区分，即，将扫描输出端作为连接栅极线的端口，而将级联输出端作为连接上下级移位寄存单元的端口，满足栅极驱动电路的多样性的设计。In the technical solution provided by the embodiment of the present application, through the mutual cooperation between the various modules, the scan output terminal outputs the scan signal to the gate line connected to it, and at the same time, the output signal of the cascaded output terminal is shifted to the upper and lower stages connected to it. The register unit, wherein the port connected to the gate line of the shift register unit is distinguished from the port connected to the upper and lower shift register units, that is, the scan output terminal is used as the port connected to the gate line, and the cascaded output terminal is used as the port connected to the gate line. As a port connecting upper and lower shift register units, it is designed to meet the diversity of gate drive circuits.
结合图2所示，对本申请实施例提供的一种具体的移位寄存单元的结构进行详细说明。其中，图2为本申请实施例提供的另一种移位寄存单元的结构示意图。With reference to FIG. 2 , the structure of a specific shift register unit provided by the embodiment of the present application will be described in detail. Wherein, FIG. 2 is a schematic structural diagram of another shift register unit provided in the embodiment of the present application.
结合参考图1和图2所示，在本申请一实施例中，所述输入模块100包括：第一晶体管M1和第二晶体管M2；As shown in combination with reference to FIG. 1 and FIG. 2 , in an embodiment of the present application, the input module 100 includes: a first transistor M1 and a second transistor M2;
其中，所述第一晶体管M1的栅极连接至所述第一控制端SET，所述第一晶体管M1的第一端连接至所述第一电压端DIR1，所述第一晶体管M1的第二端连接至所述上拉节点P；所述第二晶体管M2的栅极连接至所述第二控制端RESET，所述第二晶体管M2的第一端连接至所述第二电压端DIR2，所述第二晶体管M2的第二端连接至所述上拉节点P。Wherein, the gate of the first transistor M1 is connected to the first control terminal SET, the first terminal of the first transistor M1 is connected to the first voltage terminal DIR1, and the second terminal of the first transistor M1 terminal is connected to the pull-up node P; the gate of the second transistor M2 is connected to the second control terminal RESET, and the first terminal of the second transistor M2 is connected to the second voltage terminal DIR2, so The second terminal of the second transistor M2 is connected to the pull-up node P.
需要说明的是，本申请实施例对于提供的第一晶体管M1和第二晶体管M2的导通类型相同，其可以为N型晶体管，还可以为P型晶体管，对此需要根据实际应用进行具体设计；本申请实施例优选提供的第一晶体管M1和第二晶体管M2的导通类型相同。另外，由于需要将上拉节点P的电位明确，因而，对于输入模块100而言，在第一控制端SET控制上拉节点P与第一电压端DIR1之间接通时，第二控制端RESET不能控制上拉节点P与第二电压端DIR2之间接通；以及，在第二控制端RESET控制上拉节点P与第二电压端DIR2之间接通时，第一控制端SET不能控制上拉节点P与第一电压端DIR1之间接通；也就是说，第一晶体管M1和第二晶体管M2不能同时导通。It should be noted that the embodiment of the present application provides the same conduction type for the first transistor M1 and the second transistor M2, which may be N-type transistors or P-type transistors, which need to be specifically designed according to actual applications ; The conduction types of the first transistor M1 and the second transistor M2 preferably provided in the embodiment of the present application are the same. In addition, since the potential of the pull-up node P needs to be clearly defined, for the input module 100, when the first control terminal SET controls the connection between the pull-up node P and the first voltage terminal DIR1, the second control terminal RESET cannot Control the connection between the pull-up node P and the second voltage terminal DIR2; and, when the second control terminal RESET controls the connection between the pull-up node P and the second voltage terminal DIR2, the first control terminal SET cannot control the connection between the pull-up node P It is connected with the first voltage terminal DIR1; that is, the first transistor M1 and the second transistor M2 cannot be turned on at the same time.
结合参考图1和图2所示，在本申请一实施例中，所述上拉控制模块200包括：第三晶体管M3和第四晶体管M4；Referring to FIG. 1 and FIG. 2 , in an embodiment of the present application, the pull-up control module 200 includes: a third transistor M3 and a fourth transistor M4;
其中，所述第三晶体管M3和第四晶体管M4的栅极均连接至所述上拉节点P，所述第三晶体管M3和第四晶体管M4的第一端均连接至所述第三电压端V3，所述第三晶体管M3的第二端连接至所述第一下拉节点Q1，所述第四晶体管M4的第二端连接至所述第二下拉节点Q2。Wherein, the gates of the third transistor M3 and the fourth transistor M4 are both connected to the pull-up node P, and the first terminals of the third transistor M3 and the fourth transistor M4 are both connected to the third voltage terminal V3, the second end of the third transistor M3 is connected to the first pull-down node Q1, and the second end of the fourth transistor M4 is connected to the second pull-down node Q2.
需要说明的是，本申请实施例提供的第三晶体管M3和第四晶体管M4的导通类型相同，且本申请对两者的导通类型不做具体限制，其均可以为N型晶体管，还可以为P型晶体管，对此需要根据实际应用中上拉节点P的有效电位进行设计。It should be noted that the conduction types of the third transistor M3 and the fourth transistor M4 provided in the embodiment of the present application are the same, and the present application does not specifically limit the conduction types of the two transistors, both of which may be N-type transistors, or It may be a P-type transistor, which needs to be designed according to the effective potential of the pull-up node P in practical applications.
此外，本申请实施例提供的第三电压端V3和第四电压端V4输出的电平信号相同，其可以为高电平信号，还可以为低电平信号，对此需要根据实际应用进行具体设计；其中，第三电压端V3输出的电平信号满足在输出至级联输出端Gout_sub时，不能对与其连接的上下级移位寄存单元进行扫描(即该信号不能使上下级移位寄存单元中晶体管导通)即可，以及，第四电压端V4输出的电平信号满足在输出至扫描输出端Gout时，不能对与扫描输出端Gout连接的栅极线进行扫描(即该信号不能对与栅极线连接的像素阵列进行扫描)即可。In addition, the level signals output by the third voltage terminal V3 and the fourth voltage terminal V4 provided in the embodiment of the present application are the same, which can be a high-level signal or a low-level signal, which needs to be determined according to actual applications. Design; wherein, the level signal output by the third voltage terminal V3 satisfies that when it is output to the cascaded output terminal Gout_sub, the upper and lower shift register units connected to it cannot be scanned (that is, the signal cannot make the upper and lower shift register units The middle transistor is turned on), and the level signal output by the fourth voltage terminal V4 satisfies that when it is output to the scanning output terminal Gout, the gate line connected to the scanning output terminal Gout cannot be scanned (that is, the signal cannot scan the gate line connected to the scanning output terminal Gout). The pixel array connected to the gate line can be scanned).
结合参考图1和图2所示，在本申请一实施例中，所述第一下拉控制模块301包括：第五晶体管M5、第六晶体管M6和第七晶体管M7；Referring to FIG. 1 and FIG. 2 , in an embodiment of the present application, the first pull-down control module 301 includes: a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7;
其中，所述第五晶体管M5、第六晶体管M6和第七晶体管M7的栅极均连接至所述第一下拉节点Q1，所述第五晶体管M5的第一端连接至所述第四电压端V4，所述第五晶体管M5的第二端连接至所述扫描输出端Gout，所述第六晶体管M6的第一端连接至所述第三电压端V3，所述第六晶体管M6的第二端连接至所述上拉节点P，所述第七晶体管M7的第一端连接至所述第三电压端V3，所述第七晶体管M7的第二端连接至所述级联输出端Gout_sub。Wherein, the gates of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all connected to the first pull-down node Q1, and the first terminal of the fifth transistor M5 is connected to the fourth voltage terminal V4, the second terminal of the fifth transistor M5 is connected to the scanning output terminal Gout, the first terminal of the sixth transistor M6 is connected to the third voltage terminal V3, and the first terminal of the sixth transistor M6 Two terminals are connected to the pull-up node P, the first terminal of the seventh transistor M7 is connected to the third voltage terminal V3, and the second terminal of the seventh transistor M7 is connected to the cascaded output terminal Gout_sub .
在本申请一实施例中，第一下拉控制模块301和第二下拉控制模块302的电路结构相同，即，所述第二下拉控制模块302包括：第十晶体管M10、第十一晶体管M11和第十二晶体管M12；In an embodiment of the present application, the first pull-down control module 301 and the second pull-down control module 302 have the same circuit structure, that is, the second pull-down control module 302 includes: a tenth transistor M10, an eleventh transistor M11 and Twelfth transistor M12;
其中，所述第十晶体管M10、第十一晶体管M11和第十二晶体管M12的栅极均连接至所述第二下拉节点Q2，所述第十晶体管M10的第一端连接至所述第四电压端V4，所述第十晶体管M10的第二端连接至所述扫描输出端Gout，所述第十一晶体管M11的第一端连接至所述第三电压端V3，所述第十一晶体管M11的第二端连接至所述上拉节点P，所述第十二晶体管M12的第一端连接至所述第三电压端V3，所述第十二晶体管M12的第二端连接至所述级联输出端Gout_sub。Wherein, the gates of the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 are all connected to the second pull-down node Q2, and the first end of the tenth transistor M10 is connected to the fourth Voltage terminal V4, the second terminal of the tenth transistor M10 is connected to the scanning output terminal Gout, the first terminal of the eleventh transistor M11 is connected to the third voltage terminal V3, the eleventh transistor The second terminal of M11 is connected to the pull-up node P, the first terminal of the twelfth transistor M12 is connected to the third voltage terminal V3, and the second terminal of the twelfth transistor M12 is connected to the Cascade output Gout_sub.
需要说明的是，在本申请其他实施例中，第一下拉控制模块301和第二下拉控制模块302的电路结构还可以设计为不同，对此本申请不做具体限制。以及，本申请实施例提供的第五晶体管M5、第六晶体管M6和第七晶体管M7的导通类型相同，其均可以为P型晶体管，还可以为N型晶体管，对此需要根据第一下拉节点Q1的有效电位进行具体设计；以及，本申请实施例提供的第十晶体管M10、第十一晶体管M11和第十二晶体管M12的导通类型相同，其均可以为P型晶体管，还可以为N型晶体管，对此需要根据第二下拉节点Q1的有效电位进行具体设计。It should be noted that, in other embodiments of the present application, the circuit structures of the first pull-down control module 301 and the second pull-down control module 302 may also be designed differently, which is not specifically limited in this application. And, the conduction types of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 provided in the embodiment of the present application are the same, and they can all be P-type transistors or N-type transistors. The effective potential of the node Q1 is pulled for specific design; and, the conduction types of the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 provided in the embodiment of the present application are the same, and they can all be P-type transistors, or It is an N-type transistor, which needs to be specifically designed according to the effective potential of the second pull-down node Q1.
结合参考图1和图2所示，在本申请一实施例中，所述第一下拉生成模块401包括：第八晶体管M8和第九晶体管M9；As shown in combination with reference to FIG. 1 and FIG. 2 , in an embodiment of the present application, the first pull-down generation module 401 includes: an eighth transistor M8 and a ninth transistor M9;
其中，所述第八晶体管M8的栅极连接至所述第一信号端Clock1，所述第八晶体管M8的第一端连接至所述第三电压端V3，所述第八晶体管M8的第二端连接至所述第一下拉节点Q1，所述第九晶体管M9的栅极连接至所述第二信号端Clock2，所述第九晶体管M9的第一端连接至所述第二信号端Clock2，所述第九晶体管M9的第二端连接至所述第一下拉节点Q1。Wherein, the gate of the eighth transistor M8 is connected to the first signal terminal Clock1, the first terminal of the eighth transistor M8 is connected to the third voltage terminal V3, and the second terminal of the eighth transistor M8 terminal is connected to the first pull-down node Q1, the gate of the ninth transistor M9 is connected to the second signal terminal Clock2, and the first terminal of the ninth transistor M9 is connected to the second signal terminal Clock2 , the second end of the ninth transistor M9 is connected to the first pull-down node Q1.
在本申请一实施例中，第一下拉生成模块401和第二下拉生成模块402的电路结构相同，且对于第一信号端Clock1和第二信号端Clock2的连接关系相反，即，所述第二下拉生成模块402包括：第十三晶体管M13和第十四晶体管M14；In an embodiment of the present application, the first pull-down generation module 401 and the second pull-down generation module 402 have the same circuit structure, and the connection relationship between the first signal terminal Clock1 and the second signal terminal Clock2 is opposite, that is, the first pull-down generation module 402 The second pull-down generating module 402 includes: a thirteenth transistor M13 and a fourteenth transistor M14;
其中，所述第十三晶体管M13的栅极连接至所述第二信号端Clock2，所述第十三晶体管M13的第一端连接至所述第三电压端V3，所述第十三晶体管M13的第二端连接至所述第二下拉节点Q2，所述第十四晶体管M14的栅极连接至所述第一信号端Clock1，所述第十四晶体管M14的第一端连接至所述第一信号端Clock1，所述第十四晶体管M14的第二端连接至所述第二下拉节点Q2。Wherein, the gate of the thirteenth transistor M13 is connected to the second signal terminal Clock2, the first terminal of the thirteenth transistor M13 is connected to the third voltage terminal V3, and the thirteenth transistor M13 The second terminal of the fourteenth transistor M14 is connected to the second pull-down node Q2, the gate of the fourteenth transistor M14 is connected to the first signal terminal Clock1, and the first terminal of the fourteenth transistor M14 is connected to the first A signal terminal Clock1, the second terminal of the fourteenth transistor M14 is connected to the second pull-down node Q2.
需要说明的是，本申请实施例提供的第八晶体管M8和第九晶体管M9的导通类型相同，其可以为N型晶体管，还可以为P型晶体管，对此需要根据第一信号端Clock1和第二信号端Clock2的有效电平进行具体设计；以及，本申请实施例提供的第十三晶体管M13和第十四晶体管M14的导通类型相同，其可以为N型晶体管，还可以为P型晶体管，对此需要根据第一信号端Clock1和第二信号端Clock2的有效电平进行具体设计。It should be noted that the conduction types of the eighth transistor M8 and the ninth transistor M9 provided in the embodiment of the present application are the same, and they may be N-type transistors or P-type transistors, which need to be based on the first signal terminal Clock1 and The active level of the second signal terminal Clock2 is specifically designed; and, the conduction types of the thirteenth transistor M13 and the fourteenth transistor M14 provided in the embodiment of the present application are the same, which can be N-type transistors or P-type transistors The transistor needs to be specifically designed according to the active levels of the first signal terminal Clock1 and the second signal terminal Clock2.
结合参考图1和图2所示，在本申请一实施例中，所述扫描输出模块500包括：第十五晶体管M15；As shown in combination with reference to FIG. 1 and FIG. 2 , in an embodiment of the present application, the scan output module 500 includes: a fifteenth transistor M15;
其中，所述第十五晶体管M15的栅极连接至所述上拉节点P，所述第十五晶体管M15的第一端连接至所述时钟信号端CK，所述第十五晶体管M15的第二端连接至所述扫描输出端Gout。Wherein, the gate of the fifteenth transistor M15 is connected to the pull-up node P, the first end of the fifteenth transistor M15 is connected to the clock signal terminal CK, and the first end of the fifteenth transistor M15 The two terminals are connected to the scanning output terminal Gout.
以及，结合参考图1和图2所示，所述级联输出模块600包括：第十六晶体管M16；And, as shown in conjunction with reference to FIG. 1 and FIG. 2 , the cascaded output module 600 includes: a sixteenth transistor M16;
其中，所述第十六晶体管M16的栅极连接至所述上拉节点P，所述第十六晶体管M16的第一端连接至所述时钟信号端CK，所述第十六晶体管M16的第二端连接至所述级联输出端Gout_sub。Wherein, the gate of the sixteenth transistor M16 is connected to the pull-up node P, the first end of the sixteenth transistor M16 is connected to the clock signal terminal CK, and the first end of the sixteenth transistor M16 The two terminals are connected to the cascade output terminal Gout_sub.
需要说明的是，本申请实施例提供的第十五晶体管M15和第十六晶体管M16的导通类型相同，其可以为N型晶体管，还可以为P型晶体管，对此需要根据上拉节点P的有效电位进行具体设计。It should be noted that the conduction types of the fifteenth transistor M15 and the sixteenth transistor M16 provided in the embodiment of the present application are the same, and they may be N-type transistors or P-type transistors. For this, the pull-up node P The effective potential of the specific design.
在本申请一实施例中，所述第一信号端Clock1和第二信号端Clock2的电平与所述第三电压端V3的电平相同时，所述第一信号端Clock1和第二信号端Clock2输出电压与所述第三电压端V3输出电压相同。In an embodiment of the present application, when the levels of the first signal terminal Clock1 and the second signal terminal Clock2 are the same as the level of the third voltage terminal V3, the first signal terminal Clock1 and the second signal terminal The output voltage of Clock2 is the same as the output voltage of the third voltage terminal V3.
其中，为了使第八晶体管M8或第十三晶体管M13在截止时的关断效果更好，和为了使第七晶体管M7或第十四晶体管M14在截止时的关断效果更好，本申请优选的第一信号端Clock1和第二信号端Clock2的电平与所述第三电压端V3的电平相同时，即电压信号相位相同时，第一信号端Clock1和第二信号端Clock2输出电压与第三电压端V3输出电压相同，进而使得第八晶体管M8或第十三晶体管M13关断时栅极端电压和第一端电压相同，和使得第七晶体管M7或第十四晶体管M14的关断时栅极端电压和第一端电压相同，以提高关断效果。具体例如，当第一信号端Clock1或第二信号端Clock2输出的电平信号为低电平时，且同时第三电压端V3输出的电平信号为低电平时，此时，第一信号端Clock1或第二信号端Clock2输出电压与所述第三电压端V3输出电压相同，如均为-15V。Among them, in order to make the turn-off effect of the eighth transistor M8 or the thirteenth transistor M13 better when it is turned off, and in order to make the turn-off effect of the seventh transistor M7 or the fourteenth transistor M14 better when it is turned off, the present application preferably When the levels of the first signal terminal Clock1 and the second signal terminal Clock2 are the same as the level of the third voltage terminal V3, that is, when the phases of the voltage signals are the same, the output voltages of the first signal terminal Clock1 and the second signal terminal Clock2 are equal to The output voltage of the third voltage terminal V3 is the same, so that the gate terminal voltage is the same as the first terminal voltage when the eighth transistor M8 or the thirteenth transistor M13 is turned off, and the seventh transistor M7 or the fourteenth transistor M14 is turned off. The voltage at the gate terminal is the same as the voltage at the first terminal to improve the turn-off effect. Specifically, for example, when the level signal output by the first signal terminal Clock1 or the second signal terminal Clock2 is low level, and at the same time, when the level signal output by the third voltage terminal V3 is low level, at this time, the first signal terminal Clock1 Or the output voltage of the second signal terminal Clock2 is the same as the output voltage of the third voltage terminal V3, for example, both are -15V.
以及，所述时钟信号端CK的电平与所述第四电压端V4的电平相同时，所述时钟信号端CK输出电压与所述第四电压端V4输出电压相同。其中，由于在扫描输出模块500响应于上拉节点P的电位，而控制时钟信号端CK与扫描输出端Gout接通时，与扫描输出端Gout连接的栅极线的电位为时钟信号端CK输出的电位，故而，为了使与栅极线连接的晶体管达到更好的关断目的，本申请优选的时钟信号端CK的电平与第四电压端V4的电平相同时，时钟信号端CK输出电压与所述第四电压端V4输出电压相同，如，在时钟信号端CK为下降沿输出低电平、且第四电压端V4输出低电平时，时钟信号端CK选择更低的电压值输出，即与第四电压端V4输出的电压相同。And, when the level of the clock signal terminal CK is the same as the level of the fourth voltage terminal V4, the output voltage of the clock signal terminal CK is the same as the output voltage of the fourth voltage terminal V4. Wherein, since the scanning output module 500 responds to the potential of the pull-up node P and controls the clock signal terminal CK to connect to the scanning output terminal Gout, the potential of the gate line connected to the scanning output terminal Gout is the output of the clock signal terminal CK. Therefore, in order to achieve a better turn-off of the transistor connected to the gate line, when the level of the preferred clock signal terminal CK in this application is the same as the level of the fourth voltage terminal V4, the clock signal terminal CK outputs The voltage is the same as the output voltage of the fourth voltage terminal V4, for example, when the clock signal terminal CK outputs a low level on the falling edge and the fourth voltage terminal V4 outputs a low level, the clock signal terminal CK selects a lower voltage value for output , which is the same as the voltage output from the fourth voltage terminal V4.
在本申请一实施例中，栅极驱动电路可以为双向扫描的栅极驱动电路，其中，在所述栅极驱动电路沿第一方向扫描时，所述第一控制端SET输出开启信号；In an embodiment of the present application, the gate driving circuit may be a bidirectional scanning gate driving circuit, wherein, when the gate driving circuit scans along the first direction, the first control terminal SET outputs a turn-on signal;
以及，在所述栅极驱动电路沿第二方向扫描时，所述第二控制端RESET输出开启信号，其中，所述第一方向和第二方向相反。And, when the gate driving circuit scans along a second direction, the second control terminal RESET outputs an enable signal, wherein the first direction is opposite to the second direction.
即，在栅极驱动电路沿第一方向扫描时，移位寄存单元的第一控制端SET首先输出开启信号，以使移位寄存单元开始工作，且在开启信号输出完毕后，移位寄存单元的扫描输出端输出扫描栅极线的信号，和级联输出端输出相应信号(相应信号为为上一级移位寄存单元提供的关闭信号和为下一级移位寄存单元提供的开启信号，其中，关闭信号和开启信号为同一信号)至上下级移位寄存单元，并在结束阶段时，第二控制端RESET输出关闭信号，以使移位寄存单元的扫描输出端不再输出扫描信号；That is, when the gate drive circuit scans along the first direction, the first control terminal SET of the shift register unit first outputs a start signal, so that the shift register unit starts to work, and after the start signal is output, the shift register unit The scan output terminal outputs the signal of the scan gate line, and the cascaded output terminal outputs the corresponding signal (the corresponding signal is the closing signal provided for the shift register unit of the upper stage and the open signal provided for the shift register unit of the next stage, Wherein, the close signal and the open signal are the same signal) to the upper and lower shift register units, and at the end stage, the second control terminal RESET outputs the close signal, so that the scan output terminal of the shift register unit no longer outputs scan signals;
以及，在栅极驱动电路沿第二方向扫描时，移位寄存单元的第二控制端RESET首先输出开启信号，以使移位寄存单元开始工作，且在开启信号输出完毕后，移位寄存单元的扫描输出端输出扫描栅极线的信号，和级联输出端输出相应信号(相应信号为为上一级移位寄存单元提供的关闭信号和为下一级移位寄存单元提供的开启信号，其中，关闭信号和开启信号为同一信号)至上下级移位寄存单元，并在结束阶段时，第一控制端RET输出关闭信号，以使移位寄存单元的扫描输出端不再输出扫描信号。And, when the gate drive circuit scans along the second direction, the second control terminal RESET of the shift register unit first outputs a start signal, so that the shift register unit starts to work, and after the start signal is output, the shift register unit The scan output terminal outputs the signal of the scan gate line, and the cascaded output terminal outputs the corresponding signal (the corresponding signal is the closing signal provided for the shift register unit of the upper stage and the open signal provided for the shift register unit of the next stage, Wherein, the close signal and the open signal are the same signal) to the upper and lower shift register units, and at the end stage, the first control terminal RET outputs the close signal, so that the scan output terminal of the shift register unit no longer outputs scan signals.
此外，为了满足在所述上拉控制模块200控制所述第三电压端V3与所述第二下拉节点Q2接通时，所述第二下拉节点Q2的电位为所述第三电压端V3的电位，以及，在所述上拉控制模块200控制所述第三电压端V3与所述第一下拉节点Q1接通时，所述第一下拉节点Q1的电位为所述第三电压端V3的输出电位，本申请实施例提供的第三晶体管M3的宽长比大于第九晶体管的宽长比，以及，第四晶体管M4的宽长比大于第十四晶体管M14的宽长比。In addition, in order to meet the requirement that when the pull-up control module 200 controls the connection between the third voltage terminal V3 and the second pull-down node Q2, the potential of the second pull-down node Q2 is equal to that of the third voltage terminal V3. potential, and, when the pull-up control module 200 controls the third voltage terminal V3 to be connected to the first pull-down node Q1, the potential of the first pull-down node Q1 is the third voltage terminal For the output potential of V3, the aspect ratio of the third transistor M3 provided by the embodiment of the present application is greater than that of the ninth transistor, and the aspect ratio of the fourth transistor M4 is greater than that of the fourteenth transistor M14.
在本申请一实施例中，由于第一下拉生成模块401和第二下拉生成模块402与第一信号端Clock1和第二信号端Clock2的连接关系相反，且第一信号端Clock1和第二信号端Clock2的输出信号为互补时钟信号，所以在移位寄存单元扫描完毕后，第一下拉节点Q1和第二下拉节点Q2交替为第二信号端Clock2和第一信号端Clock1输出的有效电平信号，为了达到降低功耗的目的，本申请实施例优选的所述第一信号端Clock1和第二信号端Clock2的输出信号均为帧反转信号，即，使得第一下拉节点Q1和第二下拉节点Q2在移位寄存单元扫描完毕后，其上的有效电平信号为一帧画面交替一次。In an embodiment of the present application, since the connection relationship between the first pull-down generation module 401 and the second pull-down generation module 402 and the first signal terminal Clock1 and the second signal terminal Clock2 is opposite, and the first signal terminal Clock1 and the second signal terminal Clock1 The output signal of the terminal Clock2 is a complementary clock signal, so after the shift register unit is scanned, the first pull-down node Q1 and the second pull-down node Q2 are alternately the active levels output by the second signal terminal Clock2 and the first signal terminal Clock1 signal, in order to achieve the purpose of reducing power consumption, the preferred output signals of the first signal terminal Clock1 and the second signal terminal Clock2 in the embodiment of the present application are frame inversion signals, that is, the first pull-down node Q1 and the second After the shift register unit scans the second pull-down node Q2, the active level signal on it alternates once for one frame.
下面结合驱动方法对本申请实施例提供的移位寄存单元的各个组成模块和组成模块的每个晶体管的接通和截止情况进行进一步的描述。需要说明的是，下面以高电平信号有效的移位寄存单元进行描述，即，以第一晶体管M1至第十六晶体管M16均为N型晶体管为例进行说明，以及，以第三电压端V3和第四电压端V4的输出信号为低电平信号，移位寄存单元的扫描输出端Gout和级联输出端Gout_sub的输出的有效电平为高电平为例进行说明。The individual modules of the shift register unit provided by the embodiment of the present application and the on and off conditions of each transistor of the module will be further described below in conjunction with the driving method. It should be noted that the shift register unit with an effective high-level signal will be described below, that is, the first transistor M1 to the sixteenth transistor M16 are all N-type transistors for illustration, and the third voltage terminal The output signals of V3 and the fourth voltage terminal V4 are low-level signals, and the effective levels of the outputs of the scanning output terminal Gout and the cascade output terminal Gout_sub of the shift register unit are high-level as an example for illustration.
结合图1、图2、图3和图4所示，对本申请实施例提供的驱动方法进行详细说明，其中，本申请实施例提供的驱动方法，应用于上述的移位寄存单元，且驱动方法包括：第一阶段T1、第二阶段T2和第三阶段T3。With reference to Fig. 1, Fig. 2, Fig. 3 and Fig. 4, the driving method provided by the embodiment of the present application is described in detail, wherein, the driving method provided in the embodiment of the present application is applied to the above-mentioned shift register unit, and the driving method Including: the first stage T1, the second stage T2 and the third stage T3.
参考图3所示，为本申请实施例提供的一种沿第一方向扫描的时序图，其中，第一电压端DIR1的输出电平为高电平，第二电压端DIR2的输出电平为低电平，在沿第一方向扫描时：Referring to FIG. 3 , it is a timing diagram of scanning along the first direction provided by the embodiment of the present application, wherein the output level of the first voltage terminal DIR1 is high level, and the output level of the second voltage terminal DIR2 is Low level, when scanning in the first direction:
在第一阶段T1，输入模块100响应于第一控制端SET的电位，而控制第一电压端DIR1与上拉节点P之间接通，上拉节点P的电位为第一电压端DIR1输出的高电平；其中，上拉控制模块200响应于上拉节点P的电位，而控制第三电压端V3分别与第一下拉节点Q1和第二下拉节点Q2之间接通；以及，扫描输出模块500和级联输出模块600均响应于上拉节点P的电位，而控制时钟信号端CK分别与扫描输出端Gout和级联输出端Gout_sub之间接通，此时时钟信号端CK输出电平为低电平(即输出信号为关闭信号)。In the first stage T1, the input module 100 controls the connection between the first voltage terminal DIR1 and the pull-up node P in response to the potential of the first control terminal SET, and the potential of the pull-up node P is the high output of the first voltage terminal DIR1. level; wherein, the pull-up control module 200 responds to the potential of the pull-up node P, and controls the third voltage terminal V3 to connect with the first pull-down node Q1 and the second pull-down node Q2 respectively; and, the scan output module 500 and the cascaded output module 600 respond to the potential of the pull-up node P, and control the connection between the clock signal terminal CK and the scan output terminal Gout and the cascade output terminal Gout_sub respectively, and the output level of the clock signal terminal CK is low at this time. Level (that is, the output signal is off signal).
具体结合图2和图3所示，在第一阶段T1，第一控制端SET输出电平为高点平，而控制第一晶体管M1导通，使得上拉节点P的电位为第一电压端DIR1输出的高电平。进而与上拉节点P连接的第三晶体管M3、第四晶体管M4、第十五晶体管M15和第十六晶体管M16均导通，以使得第一下拉节点Q1和第二下拉节点Q2的电位为第三电压端V3输出的低电平，以及，使得扫描输出端Gout和级联输出端Gout_sub的输出信号为时钟信号端CK输出的电平。其中，由于第一下拉节点Q1和第二下拉节点Q2的电位均为低电平，故而，使得与两者连通的晶体管均为截止状态。Specifically as shown in Figure 2 and Figure 3, in the first stage T1, the output level of the first control terminal SET is high and flat, and the first transistor M1 is controlled to be turned on, so that the potential of the pull-up node P is the first voltage terminal High level of DIR1 output. Furthermore, the third transistor M3, the fourth transistor M4, the fifteenth transistor M15, and the sixteenth transistor M16 connected to the pull-up node P are all turned on, so that the potentials of the first pull-down node Q1 and the second pull-down node Q2 are The low level output by the third voltage terminal V3, and the output signal of the scan output terminal Gout and the cascade output terminal Gout_sub are at the level output by the clock signal terminal CK. Wherein, since the potentials of the first pull-down node Q1 and the second pull-down node Q2 are both at low level, the transistors connected to them are all in an off state.
在第二阶段T2，扫描输出模块500和级联输出模块600均响应于上拉节点P的电位，而控制时钟信号端CK分别与扫描输出端Gout和级联输出端Gout_sub之间接通，此时时钟信号端CK输出电平为高电平。In the second stage T2, both the scan output module 500 and the cascade output module 600 respond to the potential of the pull-up node P, and the control clock signal terminal CK is respectively connected to the scan output terminal Gout and the cascade output terminal Gout_sub, at this time The output level of the clock signal terminal CK is high level.
具体结合图2和图3所示，在第二阶段T2，此时电容C的一极板的电位为时钟信号端CK输出的高电平，故而，电容C将会将与其另一极板连接的上拉节点P的高电平，在第一阶段T1的基础上再次拉高。由于上拉节点P的电位保持为高电平，因而与上拉节点P连通的晶体管保持第一阶段T1的状态不变。以及，在第二阶段T2，时钟信号端CK输出电平为高电平，该高电平信号分别通过第十五晶体管M15和第十六晶体管M16，传输至扫描输出端Gout和级联输出端Gout_sub。Specifically as shown in Figure 2 and Figure 3, in the second stage T2, the potential of one plate of the capacitor C is the high level output by the clock signal terminal CK, so the capacitor C will be connected to the other plate The high level of the pull-up node P is pulled high again on the basis of the first stage T1. Since the potential of the pull-up node P remains high, the transistors connected to the pull-up node P keep the state of the first stage T1 unchanged. And, in the second stage T2, the output level of the clock signal terminal CK is high level, and the high level signal is transmitted to the scan output terminal Gout and the cascade output terminal through the fifteenth transistor M15 and the sixteenth transistor M16 respectively Gout_sub.
在第三阶段T3，输入模块100响应于第二控制端RESET的电位，而控制第二电压端DIR2与上拉节点P之间接通，上拉节点P的电位为第二电压端DIR2输出的低电平；其中，第一下拉生成模块401响应于第二信号端Clock2的电位，而控制第二信号端Clock2与第一下拉节点Q1之间接通；或者，第二下拉生成模块402响应于第一信号端Clock1的电位，而控制第一信号端Clock1与第二下拉节点Q2之间接通。此时，第一下拉节点Q1控制第一下拉控制模块301工作，或第二下拉节点Q2控制第二下拉控制模块302工作，使得上拉节点P与第三电压端V3之间接通、扫描输出端Gout与第四电压端V4之间接通和级联输出端Gout_sub与第三电压端V3之前接通。In the third stage T3, the input module 100 controls the connection between the second voltage terminal DIR2 and the pull-up node P in response to the potential of the second control terminal RESET, and the potential of the pull-up node P is the low voltage output by the second voltage terminal DIR2. level; wherein, the first pull-down generating module 401 controls the connection between the second signal terminal Clock2 and the first pull-down node Q1 in response to the potential of the second signal terminal Clock2; or, the second pull-down generating module 402 responds to The potential of the first signal terminal Clock1 controls the connection between the first signal terminal Clock1 and the second pull-down node Q2. At this time, the first pull-down node Q1 controls the first pull-down control module 301 to work, or the second pull-down node Q2 controls the second pull-down control module 302 to work, so that the connection between the pull-up node P and the third voltage terminal V3 is connected and scanned. The connection between the output terminal Gout and the fourth voltage terminal V4 is connected before the connection between the cascaded output terminal Gout_sub and the third voltage terminal V3.
具体结合图2和图3所示，在第三阶段T3，第二控制端RESET输出高电平，而控制第二晶体管M2导通，使得上拉节点P的电位为第二电压端DIR2输出的低电平，此时与上拉节点P连通的晶体管均截止。由于第一信号端Clock1输出的高电平，故而，第一信号端Clock1控制第十四晶体管M14导通，将第一信号端Clock1输出的高电平传输至第二下拉节点Q2，且第一下拉节点Q1的电位为第三电压端V3输出的低电平；此时，第二下拉节点Q2控制第十晶体管M10、第十一晶体管M11和第十二晶体管M12导通，使得扫描输出端Gout的电位为第四电压端V4输出的低电平、上拉节点P的电位为第三电压端V3输出的低电平和级联输出端Gout_sub的电位为第三电压端V3输出的低电平。其中，由于第三电压端V3输出电压低于第四电压端V4输出电压，而第十五晶体管M15此时Vgs＝第三电压端V3的电压值-第四电压端V4的电压值，即，第十五晶体管M15此时Vgs为负数，使得第十五晶体管M15的漏电流较小，提高了移位寄存单元的输出稳定性。此外，由于级联输出端Gout_sub输出电压值为第三电压端V3输出的更低的低电平，故而，能够有效的关闭上下级移位寄存单元中相应连通的晶体管，避免由于电压值较高造成误导通。Specifically as shown in Figure 2 and Figure 3, in the third stage T3, the second control terminal RESET outputs a high level, and controls the second transistor M2 to turn on, so that the potential of the pull-up node P is the output of the second voltage terminal DIR2 At this time, the transistors connected to the pull-up node P are all turned off. Due to the high level output by the first signal terminal Clock1, the first signal terminal Clock1 controls the turn-on of the fourteenth transistor M14 to transmit the high level output by the first signal terminal Clock1 to the second pull-down node Q2, and the first The potential of the pull-down node Q1 is the low level output by the third voltage terminal V3; at this time, the second pull-down node Q2 controls the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 to conduct, so that the scanning output terminal The potential of Gout is the low level output from the fourth voltage terminal V4, the potential of the pull-up node P is the low level output from the third voltage terminal V3, and the potential of the cascade output terminal Gout_sub is the low level output from the third voltage terminal V3 . Wherein, since the output voltage of the third voltage terminal V3 is lower than the output voltage of the fourth voltage terminal V4, and the fifteenth transistor M15 at this time Vgs=voltage value of the third voltage terminal V3−voltage value of the fourth voltage terminal V4, that is, The Vgs of the fifteenth transistor M15 is a negative number at this time, so that the leakage current of the fifteenth transistor M15 is small, and the output stability of the shift register unit is improved. In addition, since the output voltage value of the cascaded output terminal Gout_sub is a lower low level than that output by the third voltage terminal V3, it can effectively close the corresponding connected transistors in the upper and lower shift register units, avoiding cause misleading.
需要说明的是，在第三阶段T3，还可以将第一信号端Clock1设置为输出低电平，而将第二信号端Clock2设置为输出高电平，对此本申请实施例不做具体限制。It should be noted that in the third stage T3, the first signal terminal Clock1 can also be set to output a low level, and the second signal terminal Clock2 can be set to output a high level, which is not specifically limited in this embodiment of the present application. .
以及，结合图1、图2和图4所示，图4为本申请实施例提供的一种沿第二方向扫描的时序图，驱动方法同样包括第一阶段T1、第二阶段T2和第三阶段T3，其中，与沿第一方向扫描不同的是，在沿第二方向扫描时，第一电压端DIR1输出低电平，而第二电压端DIR2输出高电平；以及，第二控制端RESET在第一阶段T1输出高电平，而第一控制端SET在第三阶段T3输出高电平，除上述不同之外，沿第二方向扫描时移位寄存单元的运行过程，与沿第一方向扫描时的运行过程相同，故本申请不作多余赘述。And, as shown in FIG. 1, FIG. 2 and FIG. 4, FIG. 4 is a timing diagram of scanning along the second direction provided by the embodiment of the present application. The driving method also includes the first stage T1, the second stage T2 and the third stage. Stage T3, wherein, unlike scanning along the first direction, when scanning along the second direction, the first voltage terminal DIR1 outputs a low level, while the second voltage terminal DIR2 outputs a high level; and, the second control terminal RESET outputs a high level in the first stage T1, and the first control terminal SET outputs a high level in the third stage T3. In addition to the above differences, the operation process of the shift register unit when scanning in the second direction is the same as that in the second direction. The operation process of scanning in one direction is the same, so this application does not repeat it redundantly.
相应的，本申请实施例还提供了一种栅极驱动电路，包括N级移位寄存单元，每级所述移位寄存单元均为上述任意一实施例提供的移位寄存单元。Correspondingly, an embodiment of the present application further provides a gate drive circuit, including N stages of shift register units, and each stage of shift register units is the shift register unit provided by any one of the above embodiments.
具体参考图5所示，为本申请实施例提供的一种栅极驱动电路的结构示意图，其中，定义相邻两级移位寄存单元为第i级移位寄存单元1i和第i+1级移位寄存单元1(i+1)，其中，Specifically refer to FIG. 5 , which is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present application, wherein two adjacent stages of shift register units are defined as shift register unit 1i of stage i and stage i+1 Shift register unit 1(i+1), wherein,
所述第i级移位寄存单元1i的级联输出端Gout_sub连接至所述第i+1级移位寄存单元1(i+1)的第一控制端SET，以及，所述第i+1级移位寄存单元1(i+1)的级联输出端Gout_sub连接至所述第i级移位寄存单元1i的第二控制端RESET。The cascade output terminal Gout_sub of the i-th shift register unit 1i is connected to the first control terminal SET of the i+1-th shift register unit 1(i+1), and the i+1-th The cascaded output terminal Gout_sub of the stage shift register unit 1(i+1) is connected to the second control terminal RESET of the i-th stage shift register unit 1i.
其中，本申请实施例优选的奇数级的移位寄存单元的时钟信号端为同一端，且偶数级的移位寄存单元的时钟信号端为同一端。Wherein, in the preferred embodiment of the present application, the clock signal terminals of the odd-numbered shift register units are the same terminal, and the clock signal terminals of the even-numbered shift register units are the same terminal.
相应的，本申请实施例还提供了一种显示装置，具体参考图6所示，为本申请实施例提供的一种显示装置的结构示意图，其中，所述显示装置包括具有上述任意一实施例提供的栅极驱动电路的显示面板10；Correspondingly, the embodiment of the present application also provides a display device, specifically referring to FIG. 6 , which is a schematic structural diagram of a display device provided in the embodiment of the present application, wherein the display device includes any one of the above-mentioned embodiments A display panel 10 provided with a gate drive circuit;
以及，在显示装置为液晶显示装置时，显示装置还包括为显示面板10提供背光源(如箭头所示)的背光源模组20。And, when the display device is a liquid crystal display device, the display device further includes a backlight module 20 that provides a backlight (as indicated by an arrow) for the display panel 10 .
需要说明的是，本申请对于提供的显示装置的类型不做具体限制，如在本申请其他实施例中，显示装置还可以为有机发光显示装置。It should be noted that the present application does not specifically limit the type of the display device provided, as in other embodiments of the present application, the display device may also be an organic light-emitting display device.
本申请实施例提供了一种移位寄存单元、栅极驱动电路及显示装置，应用于栅极驱动电路，包括：输入模块、上拉节点、上拉控制模块、第一下拉节点、第一下拉控制模块、第一下拉生成模块、第二下拉节点、第二下拉控制模块、第二下拉生成模块、扫描输出模块、扫描输出端、级联输出模块、级联输出端和电容；其中，通过各个模块之间的相互配合，使得扫描输出端输出扫描信号至与其连接的栅极线，同时，使得级联输出端输出信号至与其连接的上下级移位寄存单元。由上述内容可知，本申请实施例提供的技术方案，将移位寄存单元与栅极线连接的端口和与上下级移位寄存单元连接的端口区分，即，将扫描输出端作为连接栅极线的端口，而将级联输出端作为连接上下级移位寄存单元的端口，满足栅极驱动电路的多样性的设计。An embodiment of the present application provides a shift register unit, a gate drive circuit, and a display device, which are applied to a gate drive circuit, including: an input module, a pull-up node, a pull-up control module, a first pull-down node, a first A pull-down control module, a first pull-down generation module, a second pull-down node, a second pull-down control module, a second pull-down generation module, a scan output module, a scan output terminal, a cascade output module, a cascade output terminal, and a capacitor; wherein , through the mutual cooperation between the various modules, the scanning output terminal outputs the scanning signal to the gate line connected to it, and at the same time, the cascade output terminal outputs the signal to the upper and lower shift register units connected to it. It can be seen from the above that, in the technical solution provided by the embodiment of the present application, the port connecting the shift register unit to the gate line is distinguished from the port connected to the upper and lower shift register units, that is, the scan output terminal is used as the gate line connection port. The port of the cascaded output port is used as the port connecting the upper and lower shift register units to meet the diversity design of the gate drive circuit.
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
| Application Number | Priority Date | Filing Date | Title |
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| CN201611168533.6ACN106409213B (en) | 2016-12-16 | 2016-12-16 | A kind of shifting deposit unit, gate driving circuit and display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611168533.6ACN106409213B (en) | 2016-12-16 | 2016-12-16 | A kind of shifting deposit unit, gate driving circuit and display device |
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| CN106409213B CN106409213B (en) | 2019-06-07 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611168533.6AActiveCN106409213B (en) | 2016-12-16 | 2016-12-16 | A kind of shifting deposit unit, gate driving circuit and display device |
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|---|---|
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601208A (en)* | 2017-03-01 | 2017-04-26 | 北京京东方光电科技有限公司 | Shift register unit, driving method thereof, grid drive circuit and display device |
| CN106710513A (en)* | 2017-03-21 | 2017-05-24 | 上海中航光电子有限公司 | Gate scanning circuit and display panel |
| CN106935206A (en)* | 2017-05-09 | 2017-07-07 | 京东方科技集团股份有限公司 | Shift register cell, shift-register circuit and driving method, display panel |
| CN108520724A (en)* | 2018-04-18 | 2018-09-11 | 京东方科技集团股份有限公司 | Shift register unit, driving method, gate driving circuit and display device |
| CN109192238A (en)* | 2018-10-30 | 2019-01-11 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN109410820A (en)* | 2018-12-15 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN110808015A (en)* | 2018-03-30 | 2020-02-18 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display device and drive method |
| CN112802423A (en)* | 2021-02-05 | 2021-05-14 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113299334A (en)* | 2021-06-29 | 2021-08-24 | 上海中航光电子有限公司 | Shift register circuit and display device |
| US20220375411A1 (en)* | 2021-05-19 | 2022-11-24 | Xiamen Tianma Micro-electronics Co.,Ltd. | Shift register and driving method thereof, and display panel |
| WO2023178771A1 (en)* | 2022-03-24 | 2023-09-28 | Tcl华星光电技术有限公司 | Gate drive circuit and display panel |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110077108A (en)* | 2009-12-30 | 2011-07-07 | 엘지디스플레이 주식회사 | Shift register and display device using it |
| CN103985363A (en)* | 2013-12-05 | 2014-08-13 | 上海中航光电子有限公司 | Grid driving circuit, TTF array substrate, display panel and display apparatus |
| CN106023876A (en)* | 2016-07-29 | 2016-10-12 | 上海中航光电子有限公司 | Bidirectional scanning unit, driving method and grid driving circuit |
| CN106023874A (en)* | 2016-07-29 | 2016-10-12 | 上海中航光电子有限公司 | Bidirectional scanning unit, driving method and grid driving circuit |
| CN106157923A (en)* | 2016-09-26 | 2016-11-23 | 合肥京东方光电科技有限公司 | Shift register cell and driving method, gate driver circuit, display device |
| CN106157867A (en)* | 2016-06-24 | 2016-11-23 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driver circuit and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110077108A (en)* | 2009-12-30 | 2011-07-07 | 엘지디스플레이 주식회사 | Shift register and display device using it |
| CN103985363A (en)* | 2013-12-05 | 2014-08-13 | 上海中航光电子有限公司 | Grid driving circuit, TTF array substrate, display panel and display apparatus |
| CN106157867A (en)* | 2016-06-24 | 2016-11-23 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driver circuit and display device |
| CN106023876A (en)* | 2016-07-29 | 2016-10-12 | 上海中航光电子有限公司 | Bidirectional scanning unit, driving method and grid driving circuit |
| CN106023874A (en)* | 2016-07-29 | 2016-10-12 | 上海中航光电子有限公司 | Bidirectional scanning unit, driving method and grid driving circuit |
| CN106157923A (en)* | 2016-09-26 | 2016-11-23 | 合肥京东方光电科技有限公司 | Shift register cell and driving method, gate driver circuit, display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601208A (en)* | 2017-03-01 | 2017-04-26 | 北京京东方光电科技有限公司 | Shift register unit, driving method thereof, grid drive circuit and display device |
| US11200824B2 (en) | 2017-03-01 | 2021-12-14 | Boe Technology Group Co., Ltd. | Shift register unit, driving method thereof, gate driver circuit and display device |
| WO2018157587A1 (en)* | 2017-03-01 | 2018-09-07 | 京东方科技集团股份有限公司 | Shift register unit and driving method therefor, gate driving circuit and display device |
| CN106710513A (en)* | 2017-03-21 | 2017-05-24 | 上海中航光电子有限公司 | Gate scanning circuit and display panel |
| CN106710513B (en)* | 2017-03-21 | 2020-03-17 | 上海中航光电子有限公司 | Grid scanning circuit and display panel |
| WO2018205535A1 (en)* | 2017-05-09 | 2018-11-15 | 京东方科技集团股份有限公司 | Shift register unit, shift register circuit and drive method, and display panel |
| US10984700B1 (en) | 2017-05-09 | 2021-04-20 | Boe Technology Group Co., Ltd. | Shift register unit, shift register circuit and driving method, and display panel |
| CN106935206B (en)* | 2017-05-09 | 2019-02-26 | 京东方科技集团股份有限公司 | Shift register unit, shift register circuit and driving method, and display panel |
| CN106935206A (en)* | 2017-05-09 | 2017-07-07 | 京东方科技集团股份有限公司 | Shift register cell, shift-register circuit and driving method, display panel |
| CN110808015A (en)* | 2018-03-30 | 2020-02-18 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display device and drive method |
| CN110808015B (en)* | 2018-03-30 | 2021-10-22 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit, display device and driving method |
| CN108520724A (en)* | 2018-04-18 | 2018-09-11 | 京东方科技集团股份有限公司 | Shift register unit, driving method, gate driving circuit and display device |
| CN109192238A (en)* | 2018-10-30 | 2019-01-11 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| US11257454B2 (en) | 2018-10-30 | 2022-02-22 | Beijing Boe Display Technology Co., Ltd. | Shift register and driving method thereof, and display apparatus |
| CN109410820B (en)* | 2018-12-15 | 2020-05-22 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN109410820A (en)* | 2018-12-15 | 2019-03-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN112802423A (en)* | 2021-02-05 | 2021-05-14 | 厦门天马微电子有限公司 | Display panel and display device |
| US20220375411A1 (en)* | 2021-05-19 | 2022-11-24 | Xiamen Tianma Micro-electronics Co.,Ltd. | Shift register and driving method thereof, and display panel |
| CN113299334A (en)* | 2021-06-29 | 2021-08-24 | 上海中航光电子有限公司 | Shift register circuit and display device |
| CN113299334B (en)* | 2021-06-29 | 2023-10-20 | 上海中航光电子有限公司 | Shift register circuit and display device |
| WO2023178771A1 (en)* | 2022-03-24 | 2023-09-28 | Tcl华星光电技术有限公司 | Gate drive circuit and display panel |
| Publication number | Publication date |
|---|---|
| CN106409213B (en) | 2019-06-07 |
| Publication | Publication Date | Title |
|---|---|---|
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