Summary of the invention
Technical problem to be solved by the present invention lies in provide double edge triggering differential method peak detectors and peak detection inspectionSurvey method is realized and is detected to the peak values in real time of high-frequency input signal.
In order to solve the above-mentioned technical problem, first technical solution of the invention is: a kind of double along triggering differential method signalPeak detector, including it is differential circuit, double along trigger comparator circuit and sampling hold circuit；Its main feature is that:
The differential circuit is used to carry out differential transform processing to input signal, obtains the differential transform knot of input signalFruit, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；Processing is compared convenient for comparator；
Double output signals that differential circuit is received along trigger comparator circuit, by itself and zero-point voltage or reference voltageIt is compared, and double digital controlled signals along triggering is exported according to comparison result, sampled with controlling sampling hold circuitOr keep operation；
The sampling hold circuit includes two-stage emitter follower, high-speed switching circuit and holding capacitor；First order emitter-base bandgap gradingFollower and differential circuit receive input signal simultaneously, and output follows input signal, and the output of second level emitter follower isIt is exported for final peak detection result；High-speed switching circuit is connected to output and the second level emitter-base bandgap grading of first order emitter followerBetween the input of follower, and the input terminal of second level emitter follower is grounded by holding capacitor, high-speed switching circuitOn-off is by double along the double along triggering digital controlled signal control of trigger comparator circuit output；When high-speed switching circuit conducting,The output signal of first order emitter follower charges to holding capacitor, and when high-speed switching circuit disconnects, holding capacitor passes through theThe electric discharge of second level emitter follower；The control signal of high-speed switch is provided by double along trigger comparator circuit.
The present invention realizes the differential transform of input signal using differential circuit, when input signal is in peak value or valleyWhen, obtained differential transform output signal is exactly in zero point or reference voltage value, realizes to the high-precision of input signal peak valueDegree judgement；It is obtained along trigger comparator circuit for controlling the double along triggering digital control letter of sampling hold circuit using doubleNumber.Differential transform output signal is compared with zero-point voltage or reference voltage value along trigger comparator circuit by using doubleCompared with when input signal is also not up to peak value, differential transform output signal is higher than zero-point voltage or reference voltage value, then double along touchingIt sends out comparator circuit and exports high level.When input signal reaches peak value, differential transform output signal is equal to zero-point voltage or ginsengExamine voltage value, then it is double to be jumped by high level to low level along trigger comparator circuit output.In next cycle, when input is believedNumber be in rising edge when, differential transform output signal be higher than zero-point voltage or reference voltage value, then output again jumped by low levelTo high level.To obtain in double along triggering digital controlled signals, the real-time control to the high-speed switch of sampling hold circuit is realized.The present invention is sampled to input signal and is kept two kinds of operations using sampling hold circuit, when double along trigger comparator circuitWhen double edge triggering digital controlled signals of output are high level, high-speed switch conducting, output signal follows input signal to change, isSample states.When double double edge triggering digital controlled signals along trigger comparator circuit output are low level, high-speed switch is closedDisconnected, output voltage values when output signal is held off within a certain period of time are hold mode.When the present invention turns applied to A/DWhen changing circuit, corresponding Analog-digital Converter can be carried out within the retention time.
Double preferred embodiments along triggering differential method peak detector according to the present invention, it is described double along trigger comparatorIt include comparator core circuit and digital control signal generating circuit in circuit；The comparator core circuit is in open loop shapeThe operational amplifier of state, when the output signal of differential circuit reaches zero-point voltage or reference voltage, operational amplifier output electricityPressure is high level, and when the output signal of differential circuit is lower than zero-point voltage or reference voltage, op-amp output voltage isLow level；The output signal of operational amplifier is converted into digital level by digital controlled signal generation circuit.
Since in practical work process, op-amp output voltage is limited by operational amplifier open-loop gain, noSupply voltage or ground level can be reached, it is therefore desirable to which digital controlled signal generation circuit is converted, and output signal is amplified toMains voltage level, so that the square wave control signal of standard is obtained, for controlling the switching of sampling hold circuit.
Double preferred embodiments along triggering differential method peak detector according to the present invention, comparator core circuit includePMOS tube MP1~MP13 and NMOS tube MN1~MN10；PMOS tube MP1 grid and drain electrode connection, are current input terminal, the source of MP1Pole connects power supply；The grid of PMOS tube MP1, MP2, MP3 are connected with each other, and the source electrode of MP2, MP3 connect power supply；PMOS tube MP4, MP5Grid grade is connected with each other, and the grid of PMOS tube MP5 is connected with drain electrode, and the source level of PMOS tube MP4, MP5 connects power supply；PMOS tube MP6,MP7 constitutes input stage, and the grid of MP6 connects input anode, and the grid of MP7 connects input negative terminal, and the source level of PMOS tube MP6, MP7 connectsThe drain electrode of MP3；The drain of MP7 connects the drain electrode of MN13；The grid of PMOS tube MP8 and drain electrode are connected with each other, and the source electrode of MP8 meets MP9Drain electrode, the grid of PMOS tube MP8, MP9 is connected with each other, and the source electrode of MP9 connects power supply；The grid of PMOS tube MP10, MP11 is mutualConnection, the source electrode of MP10 connect the drain electrode of MP11, and the source electrode of MP11 connects power supply；The grid of PMOS tube MP12, MP13 is connected with each other,The source electrode of MP12 connects the drain electrode of MP13, and the source electrode of MP13 connects power supply, and the drain electrode of MP12 connects the source electrode of MP10；The grid of NMOS tube MN1Pole is connected with drain electrode, and is connected to the drain electrode of PMOS tube MP2, and the grid of NMOS tube MN1, MN2 is connected with each other, NMOS tube MN2'sDrain electrode is connected to the source electrode of NMOS tube MN7, MN8, the source electrode ground connection of NMOS tube MN1, MN2；The grid of NMOS tube MN3, MN4 is mutualConnection, the grid grade of NMOS tube MN3 and drain electrode are connected with each other, and are connected to the drain electrode of PMOS tube MP4 and MP6, the source of NMOS tube MN4Pole ground connection；The grid of NMOS tube MN5, MN6 is connected with each other, and the drain electrode of NMOS tube MN5 is connected to the drain electrode of PMOS tube MP10, NMOSThe source electrode of pipe MN6 is grounded；The grid of NMOS tube MN13, MN14 is connected with each other, and the grid of NMOS tube MN13 and drain electrode are connected with each other,And it is connected to the drain electrode of PMOS tube MP7, the source electrode ground connection of NMOS tube MN6；NMOS tube MN7, MN8 constitutes input stage, the grid of MN7Input negative terminal is connect, the grid of MN8 connects input anode, and the drain electrode of MN7 connects the drain electrode of PMOS tube MP5, and the drain electrode of MN8 connects PMOS tubeThe drain electrode of MP8 and the drain electrode of NMOS tube MN14；The source electrode of NMOS tube MN13, MN14 is grounded；The grid phase of NMOS tube MN9, MN10It connects, and is connected to the grid of PMOS tube MP12 and MP13, the source electrode of NMOS tube MN9 is connected to the drain electrode of MN10, MN10'sSource electrode ground connection.
Double preferred embodiments along triggering differential method peak detector according to the present invention, the digital controlled signal produceRaw circuit includes sign-changing amplifier and output buffer；Sign-changing amplifier is by PMOS tube MP14, NMOS tube MN11 and resistance R1 structureAt output buffer is made of NMOS tube MN12 and PMOS tube MP15；PMOS tube MP14 is mutually interconnected with the grid of NMOS tube MN11It connects, and is connected to comparator core circuit；The drain electrode of PMOS tube MP14 is connected with the drain electrode of NMOS tube MN11, and is connected to resistanceThe one end R1, the source electrode of PMOS tube MP14 connect power supply, the source electrode ground connection of NMOS tube MN11, another termination PMOS tube MP14 of resistance R1 withThe grid of NMOS tube MN11；The drain electrode of PMOS tube MP15 is connected with the drain electrode of NMOS tube MN12, and the source electrode of PMOS tube MP15 connects electricitySource, the source electrode ground connection of NMOS tube MN12, the drain electrode of PMOS tube MP15 is connected with the grid of NMOS tube MN12, and is connected to PMOS tubeThe drain electrode of MP14 and the drain electrode of NMOS tube MN11.
Second technical solution of the invention is, a kind of to utilize the differential method and double sides that signal peak detection is carried out along triggeringMethod, its main feature is that:
Be arranged differential method signal peak detector, including differential circuit, it is double along trigger comparator circuit and sampling keep electricityRoad；
The differential circuit is used to carry out differential transform processing to input signal, obtains the differential transform knot of input signalFruit, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；Processing is compared convenient for comparator；
Double output signals that differential circuit is received along trigger comparator circuit, by itself and zero-point voltage or reference voltageIt is compared, it is described double along trigger comparator circuit when the output signal of differential circuit reaches zero-point voltage or reference voltageHigh level digital signal is exported, high-speed switch is connected, when the output signal of differential circuit is lower than zero-point voltage or reference voltageWhen, it is described double along trigger comparator circuit output low level digital signal, disconnect high-speed switch；
The sampling hold circuit is for sampling input signal and being kept to operate；When high-speed switch conducting, instituteThe output signal for stating sampling hold circuit follows input signal to change, and is sample states；When high-speed switch shutdown, the samplingThe output voltage values when output signal of holding circuit is held off are hold mode.
Preferred embodiment according to the present invention using the differential method and double methods for carrying out signal peak detection along triggering,The sampling hold circuit includes two-stage emitter follower, high-speed switch and holding capacitor；
First order emitter follower and differential circuit receive input signal simultaneously, and output follows input signal, the second levelThe output of emitter follower is final peak detection result output；High-speed switch is connected to the defeated of first order emitter followerOut between the input of second level emitter follower, and the input terminal of second level emitter follower is grounded by holding capacitor；When high-speed switch conducting, the output signal of first order emitter follower charges to holding capacitor, when high-speed switch disconnects, protectsIt holds capacitor to discharge by second level emitter follower, the on-off of high-speed switching circuit is by double along the double of trigger comparator circuit outputAlong triggering digital controlled signal control.
Double beneficial effects along triggering differential method peak detector and peak-value detection method of the present invention are: the present inventionDifferential transform is carried out to input signal by using differential circuit, realizes the high-precision judgement to input signal peak value, and lead toDouble edge triggering digital controlled signals control sampling hold circuits are crossed, Self-resetting mechanism is introduced, is not required to additional reset unit and answersPosition logic；The present invention compared with traditional diode-type latches peak detector, have working frequency is high, detection accuracy is high, fromThe advantages that reset, realizes the high-precision peak detection of high-frequency, can be widely used in various sophisticated signal sampling systems.
Specific embodiment
It is a kind of double along triggering differential method signal peak detectors referring to Fig. 1 including differential circuit 1, double along trigger comparatorCircuit 2 and sampling hold circuit 3；Wherein:
The differential circuit 1 is used to carry out differential transform processing to input signal, obtains the differential transform knot of input signalFruit, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；
Double output signals that differential circuit 1 is received along trigger comparator circuit 2, by it with zero-point voltage or with reference to electricityPressure is compared, and exports double digital controlled signals along triggering according to comparison result, and control sampling hold circuit 3 is sampledOr keep operation；
The sampling hold circuit 3 includes two-stage emitter follower, high-speed switching circuit 5 and holding capacitor C4；The first orderEmitter follower 4 and differential circuit 1 receive input signal simultaneously, and output follows input signal, second level emitter followerOutput is final peak detection result output；High-speed switching circuit 5 is connected to the output of first order emitter follower 4 and theBetween the input of second level emitter follower 6, and the input terminal of second level emitter follower is grounded by holding capacitor, is opened at a high speedThe on-off on powered-down road 5 is controlled by double along trigger comparator circuit 2；When high-speed switching circuit 5 is connected, first order emitter follower4 output signal to holding capacitor C4 charge, when high-speed switching circuit 5 disconnect when, holding capacitor C4 by second level emitter-base bandgap grading withIt discharges with device 6；The control signal of high-speed switch 5 is provided by double along trigger comparator circuit 2；Two-stage emitter follower is all made of phaseThe unit gain follow-up amplifier that output end and negative input end are connected to form by same operational amplifier is constituted.
In a particular embodiment, the differential circuit 1 includes operational amplifier 10, capacitor C1, C2 and resistance R1；Capacitor C1For ac coupling capacitor, a termination input signal, the input negative terminal of another termination operational amplifier 10；Resistance R1 is bridging electricityResistance, the input negative terminal of a termination operational amplifier 10, the output end of another termination operational amplifier 10；Capacitor C2 is bridging electricityHold, the input negative terminal of a termination operational amplifier, the output end of another termination operational amplifier.The positive termination of operational amplifier 10Receive the reference voltage for connecing the generation of reference circuit 7.The differential circuit 1 can carry out differential transform to input signal, work as input signalWhen in peak value or valley, obtained differential transform output signal is exactly in reference voltage value.
The working principle of differential circuit is: when input signal is in rising edge, level is height by low jump, is equivalent toSuddenly switched on high level in the circuit R1C1, since the voltage at the both ends capacitor C1 cannot be mutated, i.e., the voltage on capacitor needsIt is just gradually increasing by a charging process, then capacitor C1 both end voltage is 0 at this time, and input voltage fully falls in bridging resistance R1On, output voltage reaches highest at this time.Hereafter input signal starts to charge to capacitor C1, and capacitor C1 both end voltage is exponentiallyRise, and resistance R1 both end voltage exponentially declines, when input signal reaches peak value, output voltage drop is as low as zero.WhenWhen input signal is in failing edge, level by height jump be it is low, be equivalent to and removed high level suddenly in the circuit R1C1, equallySince the voltage at the both ends capacitor C1 cannot be mutated, need to discharge by bridging resistance R1, therefore capacitor C1 both end voltageThe both ends resistance R1 are fallen in, and since discharge current and charging current are reversed, so output voltage reaches minimum.When input signal reachesWhen to valley, capacitor C1 electric discharge closes to an end, so that output voltage gos up to zero.In conclusion when input signal reachesWhen peak value or valley, output voltage is zero, to realize the effect for carrying out differential transform to input signal.In practical electricityIn the application of road, in order not to joined reference voltage value using the input anode of negative supply, operational amplifier, so that differential becomesZero in changing is converted to reference voltage value, is compared convenient for comparator.
As shown in Figure 4, horizontal axis is the time to differential circuit implementation result, and the longitudinal axis is voltage.It include two curves, input in figureSignal curve and differential transform curve of output, as seen from Figure 4, when input signal reaches peak value, differential transform output letterNumber reach reference voltage value；When input signal reaches valley, differential transform output signal reaches reference voltage value.Fig. 4 shows:Differential transform output may be implemented in the differential circuit.
The present invention using high-gain operational amplifier constitute differential circuit, it is double along trigger comparator and sampling keep electricityRoad, while high-speed switch is constituted using NMOS tube, as long as design forms the operational amplifier of high frequency high-bandwidth high-gain, so that it mayIt realizes high-frequency work characteristic, breaches the working frequency limitation of conventional diode structure.
The sampling hold circuit is by two-stage emitter follower 4,6, high-speed switching circuit 5 and holding capacitor C4, exchange couplingIt closes capacitor C3 to constitute, high-speed switching circuit 5 is connected to output and the second level emitter follower 6 of first order emitter follower 4Between input, two-stage emitter follower is by identical operational amplifier, and the list that output end and negative input end are connected to formPosition gain follow-up amplifier is constituted；One end of capacitor C3 receives input signal, the input of another termination first order emitter follower 4Anode；The input terminal of second level emitter follower also passes through holding capacitor C4 and is grounded, and the control signal of high-speed switching circuit 5 is by doubleIt is provided along trigger comparator circuit 2；The output end of second level emitter follower is final peak detection result output.
The working principle of sampling hold circuit is: when being in sample states, the output signal of sampling hold circuit is followedInput signal changes and changes, and when being in hold mode, the output signal of sampling hold circuit, which remains, is connected to holding orderMoment input signal level values.When circuit is in sample states, high-speed switching circuit 5 is connected, and at this moment holding capacitor chargesC4, if capacitance very little, capacitor C4 can complete charge and discharge in a short period of time, and at this moment output end output signal follows defeatedEnter signal intensity and changes；When circuit is in hold mode, high-speed switching circuit 5 disconnect, at this moment due to second level emitter-base bandgap grading withInput terminal with device is in high-impedance state, and capacitor C4 electric discharge is slow, so output signal remains essentially as disconnecting the signal electricity of momentLevel values.
In a particular embodiment, the operational amplifier of the operational amplifier and emitter follower that constitute differential circuit can wrapEnlarged structure containing two-stage, the open-loop gain for effectively increasing operational amplifier is amplified at the two poles of the earth, convenient for forming the differential of high-frequency workCircuit and emitter follower circuit, while cascode structure is used, it can make circuit work under lower operating voltage.
Referring to fig. 2, high-speed switching circuit 5 is mainly made of NMOS tube 5MN1 and resistance 5R1,5R2, the leakage of NMOS tube 5MN1Pole is as input terminal, and the source electrode of NMOS tube 5MN1 is as output end, one end of the grid connection resistance 5R1 of NMOS tube 5MN1, electricityThe other end of 5R1 is hindered as control signal input；One end of resistance 5R2 is connected to the substrate of NMOS tube 5MN1, and the other end connectsIt is connected to ground.
The working principle of high-speed switching circuit 5 is that, when controlling signal is high level, the gate source voltage of NMOS tube 5MN1 is poorValue is greater than its threshold voltage, NMOS tube 5MN1 conducting switchs in the conductive state.When controlling signal is low level, NMOSThe gate source voltage difference of pipe 5MN1 is less than its threshold voltage, and NMOS tube 5MN1 cut-off, i.e. switch are in an off state.Resistance 5R1,The grid and source-drain electrode that 5R2 can effectively reduce NMOS tube 5MN1 reduce signal when high-frequency operation to the parasitic capacitance on groundLoss, to improve Peak detection accuracy.
It is double to include comparator core circuit 8 and digital control signal generating circuit 9 along trigger comparator circuit referring to Fig. 3；The comparator core circuit 8 is the operational amplifier in open loop situations, when the output signal of differential circuit 1 reaches zero point electricityPressure or when reference voltage, op-amp output voltage is high level, when differential circuit 1 output signal lower than zero-point voltage orWhen reference voltage, op-amp output voltage is low level；Digital controlled signal generation circuit 9 is by the output of operational amplifierSignal is converted into digital level.
In a particular embodiment, the comparator core circuit 8 include PMOS tube MP1~MP13 and NMOS tube MN1~MN10；PMOS tube MP1 grid and drain electrode connection, are current input terminal, the source electrode of MP1 connects power supply；PMOS tube MP1, MP2, MP3'sGrid is connected with each other, and the source electrode of MP2, MP3 connect power supply；The grid grade of PMOS tube MP4, MP5 is connected with each other, the grid of PMOS tube MP5It is connected with drain electrode, the source level of PMOS tube MP4, MP5 connects power supply；PMOS tube MP6, MP7 constitutes input stage, and the grid of MP6 connects inputAnode, the grid of MP7 connect input negative terminal, and the source level of PMOS tube MP6, MP7 connects the drain electrode of MP3；The drain of MP7 connects the leakage of MN13Pole；The grid of PMOS tube MP8 and drain electrode are connected with each other, and the source electrode of MP8 connects the drain electrode of MP9, and the grid of PMOS tube MP8, MP9 is mutualConnection, the source electrode of MP9 connect power supply；The grid of PMOS tube MP10, MP11 is connected with each other, and the source electrode of MP10 connects the drain electrode of MP11,The source electrode of MP11 connects power supply；The grid of PMOS tube MP12, MP13 is connected with each other, and the source electrode of MP12 connects the drain electrode of MP13, MP13'sSource electrode connects power supply, and the drain electrode of MP12 connects the source electrode of MP10；The grid of NMOS tube MN1 is connected with drain electrode, and is connected to PMOS tube MP2Drain electrode, the grid of NMOS tube MN1, MN2 is connected with each other, and the drain electrode of NMOS tube MN2 is connected to the source electrode of NMOS tube MN7, MN8,The source electrode of NMOS tube MN1, MN2 is grounded；The grid of NMOS tube MN3, MN4 is connected with each other, and the grid grade of NMOS tube MN3 and drain electrode are mutualConnection, and it is connected to the drain electrode of PMOS tube MP4 and MP6, the source electrode ground connection of NMOS tube MN4；The grid of NMOS tube MN5, MN6 is mutualConnection, the drain electrode of NMOS tube MN5 are connected to the drain electrode of PMOS tube MP10, the source electrode ground connection of NMOS tube MN6；NMOS tube MN13,The grid of MN14 is connected with each other, and the grid of NMOS tube MN13 and drain electrode are connected with each other, and are connected to the drain electrode of PMOS tube MP7,The source electrode of NMOS tube MN6 is grounded；NMOS tube MN7, MN8 constitutes input stage, and the grid of MN7 connects input negative terminal, and the grid of MN8 connects defeatedEnter anode, the drain electrode of MN7 connects the drain electrode of PMOS tube MP5, and the drain electrode of MN8 connects the drain electrode of PMOS tube MP8 and the leakage of NMOS tube MN14Pole；The source electrode of NMOS tube MN13, MN14 is grounded；The grid of NMOS tube MN9, MN10 is connected with each other, and is connected to PMOS tube MP12And the grid of MP13, the source electrode of NMOS tube MN9 are connected to the drain electrode of MN10, the source electrode ground connection of MN10.
The digital controlled signal generation circuit 9 includes sign-changing amplifier and output buffer；Sign-changing amplifier is by PMOSPipe MP14, NMOS tube MN11 and resistance R1 are constituted, and output buffer is made of NMOS tube MN12 and PMOS tube MP15；PMOS tubeThe grid of MP14 and NMOS tube MN11 are connected with each other, and are connected to comparator core circuit 8, i.e., PMOS tube MP12, MP13 andThe grid of NMOS tube MN9, MN10；The drain electrode of PMOS tube MP14 is connected with the drain electrode of NMOS tube MN11, and is connected to resistance R1 mono-End, the source electrode of PMOS tube MP14 meet power supply, the source electrode ground connection of NMOS tube MN11, another termination PMOS tube MP14 and NMOS of resistance R1The grid of pipe MN11；The drain electrode of PMOS tube MP15 is connected with the drain electrode of NMOS tube MN12, and the source electrode of PMOS tube MP15 connects power supply,The source electrode of NMOS tube MN12 is grounded, and the drain electrode of PMOS tube MP15 is connected with the grid of NMOS tube MN12, and is connected to PMOS tubeThe drain electrode of MP14 and the drain electrode of NMOS tube MN11.
Due to inverting amplifier gain with higher and voltage margin, output signal can be amplified to supply voltage electricityIt is flat, so that the square wave control signal of standard is obtained, for controlling the switching of sampling hold circuit.
Double working principles along trigger comparator circuit 2 are: double be in along trigger comparator circuit comprising one is openedThe operational amplifier of ring status and one for comparison result to be converted to the digital controlled signal generation circuit of digital level, whenWhen the output signal of differential circuit 1 reaches reference voltage value, output voltage is height, when the output signal of differential circuit 1 is lower than ginsengWhen examining voltage value, output voltage be it is low,
A kind of to utilize the differential method and double methods for carrying out signal peak detection along triggering, including setting differential method signal peakIt is worth detector, including differential circuit 1, double along trigger comparator circuit 2 and sampling hold circuit 3；
The differential circuit 1 is used to carry out differential transform processing to input signal, obtains the differential transform knot of input signalFruit, and when input signal is in peak value or valley, obtained differential transform output signal is exactly in zero point or reference voltage；Processing is compared convenient for comparator；
Double output signals that differential circuit 1 is received along trigger comparator circuit 2, by it with zero-point voltage or with reference to electricityPressure is compared, described double along trigger comparator electricity when the output signal of differential circuit 1 reaches zero-point voltage or reference voltageRoad 2 exports high level digital signal, and high-speed switch 5 is connected, when the output signal of differential circuit 1 is lower than zero-point voltage or referenceIt is described double along the output low level digital signal of trigger comparator circuit 2 when voltage, disconnect high-speed switching circuit 5；
The sampling hold circuit 3 is for sampling input signal and being kept to operate；When high-speed switch conducting, instituteThe output signal for stating sampling hold circuit 3 follows input signal to change, and is sample states；It is described to adopt when high-speed switch shutdownThe output voltage values when output signal of sample holding circuit 3 is held off are hold mode.
In a particular embodiment, the sampling hold circuit 3 includes two-stage emitter follower, high-speed switch 5 and keeps electricHold C4；
First order emitter follower 4 and differential circuit 1 receive input signal simultaneously, export and follow input signal, and secondThe output of grade emitter follower is final peak detection result output；High-speed switching circuit 5 be connected to first order emitter-base bandgap grading withWith between the output of device 4 and the input of second level emitter follower 6, and the input terminal of second level emitter follower passes through holdingCapacitor C4 ground connection；When high-speed switching circuit 5 is connected, the output signal of first order emitter follower 4 charges to holding capacitor C4,When high-speed switching circuit 5 disconnects, holding capacitor C4 is discharged by second level emitter follower 6, the on-off of high-speed switching circuit 5By double double edge triggering digital controlled signal controls exported along trigger comparator circuit 2.
As shown in Figure 5, horizontal axis is the time to double edge touching method differential method peak detection circuit implementation results, and the longitudinal axis is voltage.FigureIn include three curves, input signal curve, it is double along triggering digital controlled signal curve, output signal curve, can be seen by Fig. 5Out, when input signal is not up to peak value, double along digital controlled signal is triggered as high level, output signal follows input signal；When input signal reaches peak value, double jumped along triggering digital controlled signal by high level is low level, and output signal keeps peakThreshold voltage is constant, the retention time >=0.5* input signal cycle, can carry out data conversion to output signal at this time；Then double edgesIt is high level that digital controlled signal, which is triggered, by low level jump, completes to automatically reset, output signal continues to follow input signal straightPeak value to next period arrives.Fig. 5 shows: peak may be implemented in double edge touching method differential method peak detection circuits proposed by the present inventionValue detection output.
Result of implementation above shows: one kind of the invention it is double along touching method differential method peak detectors have high-frequency work,The features such as high-precision detects.The technology of the present invention can be applied to the fields such as high-speed AD/DA, complex parameters acquisition system.