A kind of frequency scan circuit for LC type phaselocked loopTechnical field
The invention belongs to microelectronics technologies, are related to a kind of LC type phaselocked loop, especially a kind of to be used for LC type phaselocked loopFrequency scan circuit.
Background technique
Phaselocked loop is straight applied to fields, performance superiority and inferiority such as Digital Frequency Synthesize, wireless receiving and dispatchings as a common partConnect the work quality for influencing entire circuit system.Under the conditions of high band operation, LC type phaselocked loop is due to its superior making an uproar property of phaseThe features such as energy, frequency stability, is used widely in wireless communication field.Since the LC oscillator frequency range of single size is relatively narrow,It needs different size LC groups being combined into array application in practical applications, to meet broadband requirement.Conventional method is joined according to inputFrequency, frequency calculating output frequency are examined, chooses LC array in conjunction with operating temperature, calculating process and configuration are cumbersome.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the existing defects, provides a kind of frequency band for LC type phaselocked loop and sweepsScanning circuit, the frequency scan circuit using phaselocked loop feedback loop judgement determine voltage, greatly simplifie configuration circuit andProcess can be widely applied to LC type Design of PLL, it can be achieved that for the automatic frequency scan of voltage controlled oscillator array and selection.
In order to solve the above-mentioned technical problems, the present invention provides the following technical solutions:
A kind of frequency scan circuit for LC type phaselocked loop of the present invention, which includes comparator and doorCircuit, N-bit counter and d type flip flop, the input terminal connection lower voltage limit VL and judgement voltage Vdect of comparator, AND gate circuitInput terminal connection count clock Count_clk and comparator output end, the D input terminal connection N-bit counter of d type flip flopOutput end O, the input terminal C connection count period Count_period of N-bit counter, the connection of C input terminal and the door electricity of d type flip flopThe Q output of the output end on road, d type flip flop connects VCOsel selection signal, for controlling voltage controlled oscillator array switch SW < 0:2N-1>。
Further, the input of frequency scan circuit determines that voltage Vdect is exported by charge pump, and voltage value is equal to voltage-controlled electricityPress Vctrl；Frequency scan circuit output VCOsel selection signal selects array to voltage controlled oscillator.
Further, the counting period Count_period and counting clock Count_clk of frequency scan circuit, which exist, dividesFrequency relationship, Count_period=Count_clk/2N.
Further, the N value of the N-bit counter of frequency scan circuit is determined by the voltage controlled oscillator quantity of required controlFixed, 2N is greater than voltage controlled oscillator quantity.
Further, frequency scan circuit output 2N control code.
Beneficial effects of the present invention:
Whether the feedback loop of phaselocked loop is utilized in frequency scan circuit of the invention, judge to determine voltage Vdect mostIn excellent control area, voltage controlled oscillator antenna array control selection signal VCOsel is obtained；When judgement voltage Vdect is more than optimum controlWhen the lower voltage limit VL of region, the output valve VCOsel of the current d type flip flop of lockable.Circuit of the present invention can be realized for voltage controlled oscillationThe automatic frequency scan of device VCO array and selection, circuit simplify frequency band calculating compared with the circuit of conventional manual selection frequency bandProcess and circuit configuration can be widely applied in LC type phase-locked loop circuit.
Detailed description of the invention
Fig. 1 is LC type principle of phase lock loop figure of the invention；
Fig. 2 is frequency scan circuit diagram of the invention；
Fig. 3 is the frequency scan circuit diagram of the N=5 of one embodiment of the invention；
Fig. 4 is the LC array circuit figure of one embodiment of the invention.
Specific embodiment
A specific embodiment of the invention is illustrated below in conjunction with drawings and concrete examples.
Fig. 1 is the present invention applied LC type phase-locked loop circuit schematic diagram in specific implementation, which is typical LCType phaselocked loop, voltage controlled oscillator 2 is using 32 sections of array structures as shown in figure 4, the output of voltage controlled oscillator 2 is through N1 frequency divider 3, N2 pointsFrequency device 4 is supplied to frequency discrimination phase-sensitive detector PFD 5 and input reference clock Refclk frequency discrimination phase-detecting after dividing twice.Frequency scan circuit1 among charge pump 6 and voltage controlled oscillator 2, obtains 32 selection signal VCOset by comparing judgement voltage Vdect and is used forControl 2 array switch SW<0:31>of voltage controlled oscillator.
The lower limit value of the optimal voltage-controlled voltage range of voltage controlled oscillator 2 is VL, upper limit value VH in the example, in this voltageLC voltage controlled oscillator 2 all in array has the linear convergent rate optimized in range, which can guarantee entire voltage controlled oscillationDevice 2 is exported with continuous frequency band.
Fig. 2 is frequency scan circuit diagram, which includes comparator CMP111, AND gate circuit AND12, N positionThe input terminal connection lower voltage limit VL and judgement electricity of counter N_Counter 13 and d type flip flop DFF 14, comparator CMP111Press Vdect, the output end of input terminal the connection count clock Count_clk and comparator CMP111 of AND gate circuit AND 12, D touchingThe output end O of the D input terminal connection N-bit counter N_Counter13 of device DFF 14 is sent out, N-bit counter N_Counter's 13The C input terminal connection AND gate circuit AND's 12 of input terminal C connection count period Count_period, d type flip flop DFF 14 is defeatedOutlet, the Q output of d type flip flop DFF 14 connect VCOsel selection signal, for control 2 array switch SW of voltage controlled oscillator <0:2N-1>。
Fig. 3 is a kind of exemplary embodiments of Fig. 2, which includes comparator 11, AND gate circuit 12, N-bit counter 13 and DTrigger 14, since LC array is 32 sections, so the N value of N-bit counter 13 is 5 in the example.Wherein, period Count_ is countedThere are frequency dividing relationship, Count_period=31.25KHz, 32ms, Count_clk=with counting clock Count_clk by period1MHz, 1000ns, N-bit counter 13 is added up with the clock interval of 32ms, and (the time interval design value should be locked much larger than phaselocked loopIt fixes time).
Fig. 4 is LC array circuit figure, since frequency scan terminates since low-frequency band BAND-0 to high frequency band BAND-31,Voltage-controlled voltage Vctrl and determine that voltage Vdect is from low toward high before the unlocked selection of the circuit, Vdect is lower than optimal voltage-controlledWhen voltage lower limit value VL, AND gate circuit 12 can provide the 1MHz clock transfer of Count_clk to the C input terminal of d type flip flop 14Clock extension signal, at this time d type flip flop 14 will using 32ms as the period export Continuous accumulation VCOsel selection signal, from 00000 to11111；When the LC segment frequence that VCOsel selection signal is selected meets current frequency setting, by feeding back obtained voltage-controlled electricityPressure Vctrl and judgement voltage Vdect will be greater than optimal voltage-controlled voltage lower limit value VL, and AND gate circuit 12 will export perseverance 0 at this time, at this timeD type flip flop 14 can lock current VCOsel selection signal, and be allocated to array switch signal SW<0:31>.So far, the LC typePhaselocked loop completes automatic frequency scan and selection.
Embodiment cited by the present invention, is merely used to help understand the present invention, should not be construed as protecting model to the present inventionThe restriction enclosed for those skilled in the art without departing from the inventive concept of the premise, can also be rightThe present invention makes improvements and modifications, these improvement and modification are also fallen into the range of the claims in the present invention protection.