This application claims the French patent application number 15/56621 that on July 10th, 2015 submits toBenefit of priority, entire contents law admissible to the full extent by quoting mergingIn this.
Content of the invention
The purpose of embodiment of the disclosure is to solve one of the prior art at least in partOr multiple needs.
According on one side, there is provided a kind of circuit for protecting storage address data, shouldCircuit is adapted to be: receives the write number of memory devices to be written on input data busAccording to, and corresponding writing address is received on address bus；Address is generated based on writing addressProtection value；And the write data of modification, the write of this modification are generated on output data busData includes writing data and address protection value, and wherein, the width of output data bus is more than defeatedEnter the width of data/address bus.
According to an embodiment, circuit is further adapted to the number generating based on write dataAccording to protection value, the write data changed further includes data protection value.
According to an embodiment, this circuit further includes address generating circuit, and address generates electricityRoad is adapted to be the write ground generating the modification in the OPADD bus to memory devicesLocation.
According to an embodiment, address generating circuit be adapted to be by by writing address to moving to leftOne bit in position is generating the writing address of modification.
According to an embodiment, the bit number n writing data is less than the width of input data busDegree m, and address protection value is the n based on the write data in the width with address busThe position of individual bit corresponding subaddressing is generating.
According to an embodiment, the width m of input data bus is equal to the bit number of write dataThe multiple p of mesh n, circuit includes p address scrambler, and each is adapted to be based on son groundIn location corresponding one is generating address protection value.
According to an embodiment, data generation circuitry is protected to be adapted to be by entering to writing addressRow coding to generate address protection value to generate y- bit value, and wherein y is less than writing addressBit number.
According to an embodiment, this circuit further includes address realm filtering circuit, address modelEnclose filtering circuit and be adapted to be determination writing address whether in address realm to be protected, whereinOnly when address is in address realm to be protected, generate address protection value.
According to an embodiment, this circuit further includes bypass path, if for write groundWrite data not in address realm to be protected, is then provided directly to write data defeated by locationGo out bus, bypass path includes bridge circuit, be adapted to be the write data conversion of n bitBecome the write data of at least n+y bit.
According on the other hand, there is provided a kind of circuit for verifying memory address date, shouldCircuit is adapted to be: receives on address bus and reads address；Based on the address next life readBecome reference address protection value；Receive receive data from memory devices on reading data input bus (DIB)According to the address protection value reading from memory devices；And by reading from memory devicesAddress protection value and reference address protection value make comparisons verifying memory address date.
According to an embodiment, the bit number n reading data is less than reading data input bus (DIB)Reading data division width m, and based on read data input bus (DIB) reading dataThe corresponding subaddressing in the position of the reading data of n bit in partial width is generatingReference address protection value.
According to an embodiment, read width m of reading data division of data input bus (DIB) etc.In the multiple p of the bit number n reading data, this circuit includes p address scrambler, oftenOne is adapted to be and generates address protection value based on the corresponding address scrambler of subaddressing.
According on the other hand, there is provided a kind of address protection/checking circuit, deposit including for protectionThe foregoing circuit of memory address data and the foregoing circuit for verifying memory address date.
According to another aspect, there is provided a kind of method of protection storage address data, comprising:The write data of memory devices to be written into is received on input data bus, and in addressCorresponding writing address is received on bus；Address protection value is generated based on writing address；AndThe write data of modification is generated on output data bus, the write data of this modification includes writing numberAccording to address protection value, wherein, the width of output data bus is more than the width of input data busDegree.
According to another aspect, there is provided a kind of method of verifying memory address date, comprising:Address bus receives and reads address；Generate reference address protection based on the address readValue；Set from memory devices reception reading data with from memorizer on reading data input bus (DIB)The standby address protection value reading；And by the address protection value that will read from memory devices withReference address protection value is made comparisons verifying memory address date.
Specific embodiment
Fig. 1 schematically shows integrated circuit 102 and memory devices 104.Memory devices104 is such as dram or sram equipment or other kinds of addressable memory equipment.Memory devices 104 are for example located at outside piece it means that setting in integrated circuit 102 and memorizerInput/out line 106 between standby 104 has the form of wire and/or strip conductor.?In alternate embodiment, memory devices 104 can be integrated on piece, as integrated circuit 102A part.
Integrated circuit 102 includes the circuit for docking with memory devices 104, and for exampleIncluding being coupled to the physical interface layer 108 of input/out line 106, be coupled to physical interface layer108 Memory Controller 110, address protection/checking circuit 112, soc (SOC(system on a chip))Interconnection 114 and processing equipment 116.Processing equipment 116 e.g. cpu (CPU),Gpu (Graphics Processing Unit), dma (direct memory access (DMA)) unit etc..
Processing equipment 116 is for example via soc interconnection 114 and via address protection/checking electricityRoad 112 is coupled to Memory Controller 110.However, in alternative embodiments, address is protectedShield/checking circuit 112 can be merged in Memory Controller 110 or in processing equipment 116,The advantage that circuit 112 is placed between processing equipment 116 and Memory Controller 110 is, energyEnough using existing processing equipment 116 and storage control 110, and circuit 112 can so thatObtain its mode transparent to available circuit to be implemented.
For example, circuit 112 includes address protection circuit 118 and address validation circuit 120.
Address protection circuit 118 receives writing address (write on input bus 122Addr), writing address is for example provided to address protection circuit on both paths.In pathOne be used for the modification of memory devices 104 to be fed to is generated on output bus 124Address.The address of modification for example has the address realm of increase.Another path is for example used for being based onWriting address is generating address protection value.Circuit 118 receives write also on input bus 126Data (write data), and memorizer to be written into is provided on output bus 128The data of the address of the modification in equipment 104, it includes writing data and address protection value.
Address validation circuit 120 receives reading address (read on input bus 130Addr), read address and be for example provided to address validation circuit 120 on both paths.RoadOne of footpath is used for generating repairing of memory devices 104 to be fed on output bus 124The address changing.The address of modification for example has the address realm of increase.Another path is for example used forGenerate reference address protection value based on reading address.As the result of read operation, circuit 120Receive from memory devices 104 in input bus 134 and read data, it is included with data simultaneouslyThe address protection value of write.The address read from memory devices 104 is for example protected by circuit 120Shield value is made comparisons with based on the reference address protection value reading address generation.Circuit 120 is in outputIn bus 136, data (read data) is read in output, but this data is for example only in addressIt is output during protection value coupling reference address protection value.Alternatively, read data can be alwaysIt is output, but single rub-out signal (not shown in figure 1) can be in address validation circuitIt is damaged that 120 at output is asserted to indicate address date.If it is true that writing addressDamaged, and data is mistakenly written to reading address, or damaged if reading addressBad, and therefore have read undesirable address, then the address protection reading from memory devicesValue will mismatch reference address protection value.
Each address protection/checking circuit 112 can realize section so that the beam overall of data/address busDegree is processed with the less width of n bit.For example, it is assumed that data/address bus has m bitWidth, data/address bus is for example processed with p of n bit section, wherein m=pxn.
Additionally, as represented in certain embodiments, there may be parallel work-flow in Fig. 1Multiple address protections/checking circuit 112, the list of each circuit 112 and Memory Controller 110Solely port is associated.
Fig. 2 represents the memorizer of the memory devices to be written into 104 being arranged in bus 128The example of the content of write data of address.Identical content also will be read during read operationTake.
As shown, write data includes the system data (data) of n bit, its corresponding to byThe data of the storage address to be written into of processing equipment 116 supply.N is e.g. equal at least about4 integer, and e.g. it is equal to the 2 of 8 or bigger power.In certain embodiments, nThe width m of the data input bus (DIB) 126 of the circuit 118 equal to Fig. 1.However, it is real substitutingApply in example, more accurate address validation can be real advantageous by making n be less than highway widthExisting.For example, in certain embodiments, the width of bus 126 is 64 bits, and n etc.In 8.More generally, n is for example equal to m/p, and wherein p is equal to the integer of two or more.
Write data for example also includes forming data protection value (data protection)X bit and the y bit forming address protection value (address protection).Data protection value is optional, because in certain embodiments, does not realize data protection, orThis is realized by different circuit, is such as realized by Memory Controller 110.
In certain embodiments, x+y=n is so that n+x+y=2n, wherein x etc.In zero or positive integer, and y is equal at least about 1.For generating the specific coding of address protection valueScheme is for example based on available bits and selects.The address protection value of individual bit is e.g. simpleParity values.Y for example has the upper limit of q, and wherein q corresponds to n-bit dataThe bit number of address.In this case, address is simply copied, and does not pass through to compileCode reduces bit number.
In one embodiment, n is equal to 8, x and is equal to 5, and y is equal to 3.
Fig. 3 is the protection address date illustrating to be realized by circuit 118 according to exemplary embodimentThe operation of method flow chart.
In operation 301, circuit 118 receives the data of n bit of memory devices to be writeWith corresponding writing address.
In subsequent operation 302, circuit 118 is based on this writing address and generates y bitAddress protection value.In certain embodiments, generate the derivative of writing address, and based on thisDerivative is generating address protection value.For example, if write data/address bus 126 has m ratioSpy, wherein m are multiplied by n equal to p, then be based on writing address and generate p subaddressing, andAnd generate different address protection values for each of subaddressing.Address protection value is for exampleAny value of the accuracy of address date that permission to be verified with the definitiveness of at least specified level.For example, address protection value can include one or more parity values, the entangling of such as Hamming codeError code, CRC (crc) or some or all of even in address bitCopy.
In subsequent operation 303, writing address scope is for example increased to cover at least n+yThe data block of individual bit.In fact, the address providing on address bus 122 is for example based on beingThe block of the n-bit of system data.Therefore, the size of this address space for example by circuit 118Increase so that in addition to system data, can be with storage address protection value.For example, in dataIn the case that the width of bus doubles, and suppose minimum significant bit (lsb) correspondence of addressIn byte, double address and will produce the address covering two bytes rather than single byte.However,In alternative embodiments, this may not modified address, and alternatively make each address cover existThe word of the twice of the width of each word of supply on data/address bus.
In operation 304, n+y bit is written into the write ground of the modification in memory devicesLocation.
Fig. 4 is schematically illustrated more in detail the write ground of the Fig. 1 according to exemplary embodimentLocation protection circuit 118.
Address input bus (write addr) 122 are for example coupled to address range filters(addr range filt) 402, it for example allows address protection/checking to be only provided toParticular address range in memory devices.For example, storage arrangement can be subdivided into rightIt provides the Part I of address protection/checking and it is not provided with the another of address protection/checkingA part.
The output of circuit 402 is coupled to address align circuit (addr align) 404,It for example increases writing address scope, to allow address protection value and alternatively data protection valueIt is inserted into.As simple examples, storage component part can have the addressing from 0x00 to 0xffScope (with hexadecimal representation), but processing equipment 116 can only see the half of sumAddressable scope, the scope of such as 0x00 to 0x7f.Therefore, each in these addressesIndividual two adjacent physical address being for example translated in memory devices, in address 0x7fIn the case of becoming 0xfe, address 0x01 becomes 0x02, and address 0x02 becomes 0x04 etc.Deng.These translations are corresponding to the simple shifted left of a bit of each address.On output groundThe writing address write addr' of modification is provided on location bus 124.
Writing address from address filter 402 is also for example provided to FIFO(fifo) buffer 406, it for example stores one or more addresses, and will in requestIt is supplied to address incrementer (addr inc) 408, its for example be used for based on writing addressGenerate address to be accessed during write operation.Address incrementer 408 is for example adapted to be and makesAddress increases the width corresponding with the width of write data/address bus 122.For example, if writeData/address bus 122 is the width of 8 bytes, and the minimum significant bit of address specifies a wordSection, then in the case that each new block of write data is on write data/address bus 126, groundLocation incrementer 408 is for example adapted to be makes address increase increment 8.
The output of address incrementer 408 is provided to address scrambler (addr enc) 410,It for example generates the address protection value of y bit based on address value, and by this y bitValue is supplied to cascade circuit 412.Address scrambler 410 is for example based on corresponding n-bit dataThe address of value is generating address protection value.In the case that data-bus width m is equal to n,Address scrambler 410 to generate ground by being based simply on the address being provided by address incrementer 408Location protection value.However, if m is equal to pxn, wherein p is the integer of two or more, thenAddress scrambler for example generates p different protection value, a width being used for across data/address busN bit each block.
For example, in the case that this data-bus width is equal to 2n, address scrambler 408As generated a n for writing data based on the address being provided by address incrementer 408First address protection value of bit, and be then based on being increased by 1 institute by address incrementer 408The second address protection value to generate the 2nd n bit for writing data for the address providing.
Cascade circuit 412 also receives the n bit providing on input write data/address bus 126System data.In the example of fig. 4, bus 126 is additionally coupled to data encoder circuit 414(data enc), it is for example encoded to data to generate the data protection value of x bit,It is also provided to cascade circuit 412.
Circuit 412 cascades the value of n, x and y bit, to form memory devices to be writeWrite data.The input of multiplexer 416 is for example coupled in the output of cascade circuit 412, itsIts at output provides the write data (write data') on data/address bus 128.Multiplexer416 another input is for example coupled to receive write data from input bus 126, and does not addPlus address protection value or data protection value.For example, via bridge circuit (bridge) 418There is provided write data, bridge circuit 418 will be in signal storage by two memory access cyclesThe write data conversion of the n bit providing in access cycle becomes the write number of 2n bitAccording to.For example, in first circulation, n bit of write data is stored by bridge 418, andIn subsequent circulation, when having been received by other n bit, bus 128 exports2n bit.For example, multiplexer 416 is adapted to be, if write operation considers do not haveThe address realm of the address data protection added, then select the path with bridge 418.
In certain embodiments, address protection/checking circuit 112 realizes section so that data is totalThe different piece of line width is processed in parallel.In this case, based on section number LaiSuch as instantiation address scrambler 410, connection circuit 412 data encoder 414 in multiple timesEach of.The element 410,412,414 of each section for example processes the number of n bitRelevant block according to bus.Each of example of address scrambler 410 is for example to expression dataThe corresponding constant offset of the address of the position of n bit data in the width of bus is graspedMake.Additionally, in certain embodiments, read or the granularity of write access is less than data/address busWidth, and for example correspond to byte, and data/address bus has the width equal to multiple bytes.Therefore, read or write operation can point to specific beginning byte across the width of data/address bus.
As a specific example, in one embodiment, m is equal to 2n, and n is equal to 8.There are such as 2 sections it means that address scrambler 410, cascade circuit 412 dataEach of encoder 414 is instantiated twice.In such embodiments, following table providesThere is provided and by first in address scrambler by address incrementer (addr inc) 408Individual (addr enc#1) 410 and by second (addr enc#2) in address scramblerThe example of the continuation address of coding:
Fig. 5 is the flow process of the operation in the method illustrating according to the checking address of exemplary embodimentFigure.
In operation 501, receive and read address.
In subsequent operation 502, process and read address to generate y bit reference address protectionValue.The identical encryption algorithm applied in the operation 302 of application and Fig. 3 in operation 502.
In subsequent operation 503, the address realm reading access is increased to cover at leastThe block of n+y bit.This is related to the identical modification with operation 303 description with regard to Fig. 3,Except it is applied to read address, rather than writing address.
In subsequent operation 504, execute memory access, and read from memory devicesN+y bit.
In subsequent operation 505, by the y reading from memory devices bit addresses protection valueMake comparisons with reference address protection value.If there is coupling, then for example think and address does not occurDamage.However, if there is mismatch, then for example generating alarm, and it be permissible to read dataIt is dropped.
Fig. 6 is illustrated more in detail the address validation circuit of the Fig. 1 according to exemplary embodiment120.
As illustrated, the reading address (read addr) of address path 130 is for example carriedSupply address range filters (addr range filt) 602, it is for example similar to Fig. 4Circuit 402.
The output of address range filters 602 is for example provided to address align circuit (addrAlign) 604, this also for example passes through to increase the address realm reading address with covering system numberAccording to both corresponding address protection values, grasped in the circuit 404 identical mode with Fig. 4Make.Circuit 604 provides reading address read addr' in OPADD bus 132.
The output of address range filters 602 is also for example provided to fifo 606, and it is via multipleIt is coupled to address incrementer (addr inc) 610 with device (mux) 608.Address incrementThe output of device 610 is coupled to address scrambler (addr enc) 612, and it is based on and readsAddress is generating reference address protection value (ref addr prot).Address incrementer 610 HeAddress scrambler 612 is for example with the side similar with address incrementer 408 and address scrambler 410Formula is operated.
Multiplexer 608 is for example by the signal read data id from memory devices 104To control, it for example indicates provides which to read data so that multiplexer 608 in bus 134Corresponding reading address is selected from fifo 606.Address incrementer 610 for example receives oneOr multiple phase tracking signal (pahse track), and it is used for guaranteeing by incrementer 610The address generating corresponds to the reading data occurring in bus 134.With memory devicesDocking is that in the case that axi connects, one or more phase tracking signal for example include signalRvalid, rready and rlast, these signals are known to the skilled person.
Circuit 120 also includes splitter circuit 614, and it is in bus 134 from memory devicesReceive the data reading from address read addr', and extract address protection value.This addressProtection value (addr prot) is provided to comparator (compare) 616, its also fromAddress scrambler 612 receives reference address protection value.Comparator 616 is by address protection value and ginsengExamine address protection value to make comparisons, and generate the rub-out signal on the output lead 618 of comparator(error).If address protection value is mated, rub-out signal is not activated.However, such asFruit has differences between value, then rub-out signal is activated.In certain embodiments, circuit 618It is coupled to the processing equipment 116 of execution memory access, and in view of damage to address signalBad, rub-out signal indicates that to processing equipment 116 reading data cannot be relied on.
In certain embodiments, data check/correcting circuit (dataChecking/correcting) 620 also it is provided, it connects from splitter circuit 614Receive by separator 614 from read extracting data system data (data) and from by pointFrom device 614 from x bit data protection value (data prot) reading extracting data.ElectricityData multiplexer (data mux) 622 is for example coupled in the output on road 620, and its offer is defeatedGo out the reading data in bus 136.
Multiplexer 622 also receives from input bus 134 via bridge circuit (bridge) 624Read data, if it allows the address of read operation not correspond to shielded address realm,Then around oversampling circuit 614,616 and 620.For example, bridge circuit 624 passes through two memory accessThe reading data of the 2n bit providing on single memory storage cycle is converted into by the cycleThe reading data of n bit.For example, on the period 1, from the 2n ratio of bus 134Special reading data is stored by bridge 624, and defeated in bus 136 by two cyclesGo out.Multiplexer 622 is for example adapted to be, if read operation is related to not add address sumAccording to the address realm of protection, then select the path with bridge 624.
In certain embodiments, section can in address validation circuit 120 with above with respect toThe similar mode of Fig. 4 description is implemented.In the embodiment in fig 6, element 612,614,616 and 620 are for example replicated so that each instantiation of these elements processes corresponding n ratioSpecial block.
Embodiment described herein advantage be, in a relatively simple manner provide address protection,Keep docking with the standard of memory devices simultaneously.It is true that for example, by its width that doubles,Only change and be for example used for increasing the width of the data/address bus to memory devices.
Therefore have been described with least one illustrative embodiment, those skilled in the art are comeSay, various replacements, modification and improvement will be susceptible to.
Specifically, although it have been described that the y of the x bit of data protection value and address protection valueThe example of bit number n that is bit and being equal to system data, but a lot of other form is canCan.For instance, it is possible to make x+y be equal to n/2 or n/4.