CN106328702B - 填充半导体元件间隙的方法及其形成的半导体元件 - Google Patents
填充半导体元件间隙的方法及其形成的半导体元件Download PDFInfo
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Abstract
Description
技术领域
本发明涉及一种半导体元件的制造方法及其形成的半导体元件，且特别是涉及一种填充半导体元件间隙的方法及形成的具绝缘间隙的半导体元件。
背景技术
近年来半导体元件尺寸日益减小。对半导体科技来说，持续缩小半导体元件的结构尺寸、改善速率、增进效能、提高密度及降低每单位集成电路的成本，都是重要的发展目标。随着半导体元件尺寸的缩小，元件的电子特性也必须维持甚至是加以改善，以符合市场上对应用电子产品的要求。
一般来说，缩小半导体元件的结构尺寸会增加图案间隙(或沟槽)的宽深比，因而增加间隙填充的困难度。在间隙填充后，半导体元件的相关膜层和部件是否仍具有完整的构型和未褪化的性质，例如在一鳍式场效晶体管(Fin Field-Effect Transistor，FinFET)元件中其鳍部是否有硅耗损(silicon consumption)和鳍部倾斜或弯曲等缺陷产生，都是制造半导体元件需注意的重要问题之一。
发明内容
本发明的目的在于提供一种填充半导体元件间隙的方法及形成的具绝缘间隙的半导体元件，可有效增进元件的电子特性和延长使用寿命。
根据一实施例，提出一种填充半导体元件间隙的方法。首先，提供具有多个突出部的一硅基板，且突出部之间有具预定深度的间隙而彼此相隔。形成一含氮层于硅基板上方以覆盖突出部和间隙的表面，以形成一氮化物衬垫。形成一非晶硅层于含氮层上。形成一绝缘层于非晶硅层上方，且绝缘层填满间隙。
根据一实施例，提出一种具绝缘间隙的半导体元件，包括：具有多个突出部的一硅基板，且突出部之间有具预定深度的间隙而彼此相隔；一含氮层， 形成于硅基板上方以覆盖突出部和间隙的表面而形成一氮化物衬垫；一非晶硅层形成于含氮层上；和一绝缘层形成于非晶硅层并填满间隙。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附的附图，作详细说明如下。然而，本发明的保护范围当附上的权利要求所界定的为准。
附图说明
图1A至图1F为本发明第一实施例的填充半导体元件间隙的方法的示意图；
图2A至图2D为本发明第二实施例的填充半导体元件间隙的方法的示意图。
符号说明
10、20：硅基板
101、201：突出部
102、202：间隙
103：ISSG氧化物
104、204：图案化硬质掩模层
11：氧化物衬垫
13、23：含氮层
15、25：非晶硅层
17、27：绝缘层
17’：致密化绝缘层
具体实施方式
以下所揭露的实施例内容中，配合附图以详细说明本发明所提出的一种填充半导体元件间隙的方法及形成的具绝缘间隙的半导体元件。实施例中，至少一含氮层(nitride-containing layer)形成于硅基板的突出部(例如鳍式场效晶体管的鳍部)上方，之后形成一非晶硅层(amorphous silicon layer)于含氮层上，由此可有效防止硅耗损(siliconconsumption)和突出部弯曲或倾斜等缺陷的产生。实施例提出的方法精简，适合量产程序，可应用于任何具有间隙的半导体元件，特别是具有高宽深比间隙的半导体元件。实施例中，以具有多 个鳍部且鳍部之间以间隙相距的鳍式场效晶体管为例作说明。然而，技术领域者当知本发明并不仅限于鳍式场效晶体管的间隙填充制作工艺，也可应用于其他不同半导体元件态样的间隙填充制作工艺。
以下提出多个实施例，配合附图以详细说明本发明的相关制作工艺和结构。然而本发明并不仅限于此，本发明并非显示出所有可能的实施例。相同和/或相似元件沿用相同和/或相似元件符号。注意，未于本发明提出的其他实施态样也可能可以应用。可实施的细部结构和步骤可能有些不同，可在不脱离本发明的精神和范围内根据实际应用的需要而加以变化与修饰。再者，附图上的尺寸比例并非按照实物等比例绘制。因此，说明书和附图内容仅作叙述实施例之用，而非作为限缩本发明保护范围之用。
<第一实施例>
图1A至图1F绘示根据本发明第一实施例的填充半导体元件间隙的方法。如图1A所示，提供具有多个突出部(protruding portions)101的一硅基板(silicon substrate)10，且突出部101之间以具有预定深度的间隙102而彼此相距。通过硅基板10上方的一图案化硬质掩模层104对硅基板10进行蚀刻可以定义和形成间隙102。图案化硬质掩模层104可以是单层例如一垫氧化层(pad oxide)，或是多层堆叠例如氧化层/氮化层/氧化层的堆叠。可选择性地(非限制性地)应用一临场蒸气产生技术(in-situ steam generation，以下简称ISSG)进行氧化，以于硅基板10上形成一ISSG氧化物103。这些间隙102可以是沟槽(trenches)填充绝缘物后形成浅沟槽隔离(Shallow trench isolation，STI)。再者，由间隙102所定义的突出部101可以是鳍式场效晶体管(Fin Field-Effect Transistor，FinFET)的鳍部。
第一实施例中，一氧化物衬垫(liner oxide)11形成于硅基板10上以覆盖突出部101和间隙102的表面，如图1B所示。一实施例中，可利用一高宽深比制作工艺技术(highaspect ratio process，HARP)形成氧化物衬垫11于硅基板10上。
之后，如图1C所示，一含氮层(nitride-containing layer)13形成于氧化物衬垫11上以形成一氮化物衬垫(liner nitride)。含氮层13例如是氮氧化硅(siliconoxynitride，SiON)，可经由一氮化处理(nitridation process)而形成于氧化物衬垫11上。氮化处理可以是在一退火炉管(annealing furnace)中或是以一快速热处理制作工艺(rapid thermal process，RTP)进行，以形成氮化物衬垫， 其中可使用(N2O)、一氧化氮(NO)或氨(NH3)做为氮化处理中的气体来源，且氮化处理进行的温度在650℃到900℃范围之间。一实施例中，氮化处理是使用氨做为气体来源，并在650℃到900℃之间进行。值得注意的是，实施例中所提出的温度数值和相关材料是做为说明之用，并非用以限制本发明的范围。
氮化处理后，形成一非晶硅层(amorphous silicon layer)15于含氮层13上，如图1D所示。以一应力缓冲膜(stress buffer film，以下简称SBF)制作工艺沿着含氮层13形成非晶硅层15。SBF制作工艺可在温度约350℃到约550℃范围之间进行以形成非晶硅层15。一实施例中，SBF制作工艺可以在一炉管中以约380℃温度进行以形成非晶硅层15。再者，一实施例中，非晶硅层15的厚度约为
形成非晶硅层15后，形成一绝缘层(insulating layer)17于非晶硅层15上，且绝缘层17填满间隙102，如图1E所示。实施例中若间隙102具有高宽深比，则可利用一可流动式化学气相沉积(flowable chemical vapor deposition，以下简称FCVD)制作工艺以形成绝缘层17(例如包括绝缘材料SiO2)于非晶硅层15上并填充间隙102并且进行一致密化制作工艺(densification process)以固化和强化绝缘层17，形成如图1F所示的一致密化绝缘层17’。致密化制作工艺可以是，但不限制是，以一蒸气退火(steam annealing)方式执行(图1E)。例如，在一含氧环境下进行高温退火处理，以致密化绝缘层17。
在FCVD和致密化制作工艺后，可进行其他后续制作工艺以符合实际应用所需，例如可进行平坦化制作工艺(planarization process)，以使致密化绝缘层17’平坦化。后续制作工艺的细节为此领域的技术者所熟知，在此不再赘述。本发明对于后续制作工艺也不多作限制。
<第二实施例>
图2A至图2D绘示根据本发明第二实施例的填充半导体元件间隙的方法。第一实施例和第二实施例的主要区别在于氧化物衬垫11的存在与否。第二实施例中，省略了氧化物衬垫。
如图2A所示，提供具有多个突出部201的一硅基板20，且突出部201之间以具有预定深度的间隙202而彼此相距。类似的，通过硅基板20上方的一图案化硬质掩模层204对硅基板20进行蚀刻可以定义和形成间隙202。第二实施例中，具间隙202的硅基板20经由一氮化处理(nitridation process) 而形成含氮层23例如是氮化硅(silicon nitrite，SiN)，如图2B所示。类似第一实施例的步骤，氮化处理后，以一SBF制作工艺形成一非晶硅层25于含氮层23(ex:SiN)上，如图2C所示。形成非晶硅层25后，例如是利用可流动式化学气相沉积(FCVD)制作工艺形成一绝缘层27于非晶硅层25上和进行致密化制作工艺(固化和强化绝缘层27)，其中绝缘层27填满间隙202，如图2D所示。请参照第一实施例中相关制作工艺的细节说明，相同内容在此不再赘述。
根据上述，含氮层包括例如是第一实施例中叙述的至少沿着氧化物衬垫11形成的氮氧化硅(SiON)，或是如第二实施例中叙述的至少沿着间隙202形成的氮化硅(SiN)，视受到氮化处理的材料而定。实施例的含氮层13/23至少具有可有效阻止氧气渗入硅基板10/20，以及对于硅基板10/20的突出部101/201如同形成“限制框”(“restraining frame”)的作用等优点。
在半导体元件的制造过程中，例如对绝缘层17/27进行致密化(densification)制作工艺，氧气可能会渗入绝缘层，甚至进入绝缘层底下的膜层。根据实施例，含氮层13/23可以是，但不限制是，如第一实施例中所述的氮氧化硅(SiON)或是如第二实施例中所述的氮化硅(SiN)；含氮层13/23如同阻挡层的作用，可以阻止氧气渗入，因而得以有效防止氧气对硅基板10/20造成硅耗损缺陷的产生。
再者，根据实施例，硅基板10/20与绝缘层17/27之间至少有含氮层13/23和非晶硅层15/25形成。形成于含氮层13/23上方的非晶硅层15/25也可以提供硅与渗透的氧进行反应。若致密化制作工艺时在高温退火过程中(如高温蒸汽以固化和强化绝缘层17/27)氧气渗入了绝缘层17/27，则非晶硅层15/25如同防止硅耗损的第一阻挡层(first barrier)。即使非晶硅层15/25被较严重的破坏而氧气继续渗入下方的膜层，在非晶硅层15/25和硅基板10/20之间的含氮层13/23(ex:SiON或SiN)也可提供一个可以支撑的屏障足以阻止氧气渗入，避免对硅基板10/20造成硅耗损。因此，含氮层13/23如同保护硅基板10/20的第二阻挡层(second barrier)。
再者，虽然以FCVD制作工艺形成的绝缘层17/27通过致密化制作工艺可达到绝缘材料的固化和强化的作用，但致密化制作工艺也同时产生应力(stress)。在传统制作工艺中，具有鳍部(以间隙相隔)的元件，特别是具有高宽深比的鳍部，容易产生鳍部弯曲的问题，特别是靠近鳍部区边缘的鳍部更 容易受到应力的拉引而弯曲。根据实施例，硅基板10/20的突出部101/201被多层膜覆盖，这些多层膜至少包括含氮层13/23和非晶硅层15/25，且多层膜与硅基板10/20的突出部101/201和间隙102/202共形。实施例的含氮层13/23例如第一实施例的氮氧化硅(SiON)或是第二实施例的氮化硅(SiN)形成一氮化物衬垫(linernitride)，得以限制突出部101/201的构型使其在制作工艺过程中避免出现侧弯或倾斜等状况，因而解决了传统突出部弯曲缺陷(如鳍部弯曲/侧倾)的问题。应用时，具有高宽深比鳍部的半导体元件尤其受益于本发明实施例提出的内容。
根据上述，实施例的半导体元件制造方法及其形成结构具有多项特点，例如，非晶硅层和/或含氮层可以阻止氧气渗入硅基板，有效防止硅耗损的产生。再者，含氮层形成的一氮化物衬垫对于硅基板的突出部(例如鳍式场效晶体管的鳍部)如同形成了“限制框”(“restraining frame”)，因而有效避免突出部弯曲。因此，应用实施例结构的产品在电子特性和使用寿命上都有明显增进，极具市场竞争力。再者，实施例提出的方法精简且与现有制作工艺相容，十分适合量产。
其他不同构型的实施例，例如不同图案的ISSG氧化物103、氧化物衬垫11、含氮层13/23和非晶硅层15/25等，也可应用，并可视应用时半导体元件的实际状况与需求而作适当改变。因此，如图中所示的结构仅作说明之用，并非用以限制本发明欲保护的范围。因此，相关技术者当知，实施例中所提出的构成元素的形状和位置并不局限于附图所绘，而是可根据实际应用时的需求和/或制造步骤作相应调整。
虽然结合以上实施例公开了发明，然而其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (20)
1.一种填充半导体元件间隙的方法，包括：
提供具有多个突出部的一硅基板，且该些突出部之间具有预定深度的间隙而彼此相隔；
形成一含氮层于该硅基板上方以覆盖该些突出部的顶部和侧壁以及覆盖该些间隙的表面，以形成一氮化物衬垫；
直接且共形地形成一非晶硅层于该含氮层上；和
形成一绝缘层于该非晶硅层上方，且该绝缘层填满该些间隙。
2.如权利要求1所述的方法，其中该含氮层经由一氮化处理形成。
3.如权利要求2所述的方法，其中该氮化处理在温度650℃到900℃范围之间进行。
4.如权利要求1所述的方法，其中该非晶硅层以一应力缓冲膜制作工艺而形成于该含氮层上。
5.如权利要求4所述的方法，其中该应力缓冲膜制作工艺在温度350℃到550℃范围之间进行以形成该非晶硅层。
6.如权利要求1所述的方法，其中该非晶硅层的厚度为
7.如权利要求1所述的方法，其中该绝缘层以一可流动式化学气相沉积制作工艺填充该些间隙。
8.如权利要求1所述的方法，其中形成该绝缘层和填满该些间隙的步骤还包括：
进行一致密化制作工艺以固化和强化该绝缘层。
9.如权利要求8所述的方法，其中该致密化制作工艺以一蒸气退火方式执行。
10.如权利要求1所述的方法，还包括：
形成一氧化物衬垫于该硅基板上以覆盖该些突出部和该些间隙的表面，其中该含氮层形成于该氧化物衬垫上以形成该氮化物衬垫。
11.如权利要求10所述的方法，其中该含氮层包括至少沿着该氧化物衬垫形成的氮氧化硅。
12.如权利要求1所述的方法，其中该含氮层包括至少沿着该些间隙形成的氮化硅。
13.如权利要求1所述的方法，其中具有该些突出部的该硅基板被多层膜覆盖，该些多层膜至少包括该含氮层和该非晶硅层，且该些多层膜与该硅基板的该些突出部与该些间隙共形。
14.一种具绝缘间隙的半导体元件，包括：
具有多个突出部的硅基板，且该些突出部之间具有预定深度的间隙而彼此相隔；
含氮层，形成于该硅基板上方以覆盖该些突出部的顶部和侧壁以及覆盖该些间隙的表面而形成一氮化物衬垫；
非晶硅层，直接且共形地形成于该含氮层上；和
绝缘层，形成于该非晶硅层上方并填满该些间隙。
15.如权利要求14所述的半导体元件，其中该硅基板与该绝缘层之间至少有该含氮层和该非晶硅层形成。
16.如权利要求14所述的半导体元件，其中该含氮层为氮化硅至少沿着该些间隙形成。
17.如权利要求14所述的半导体元件，还包括：
氧化物衬垫，形成于该硅基板上以覆盖该些突出部和该些间隙的表面，其中该含氮层形成于该氧化物衬垫上以形成该氮化物衬垫。
18.如权利要求17所述的半导体元件，其中该含氮层为氮氧化硅至少沿着该氧化物衬垫形成而形成该氮化物衬垫。
19.如权利要求14所述的半导体元件，其中该含氮层与该硅基板的该些突出部与该些间隙共形。
20.如权利要求14所述的半导体元件，其中该硅基板的该些突出部为一鳍式场效晶体管元件的鳍部。
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