技术领域technical field
本发明涉半导体器件的制造方法，尤其涉及垂直双扩散MOS器件的制作方法。The invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a vertical double-diffused MOS device.
背景技术Background technique
垂直双扩散金属氧化物半导体器件(VDMOS，vertical double-diffusedMetal Oxide Semiconductor)由于具有高输入阻抗、低驱动功率、以及优越的频率特性和热稳定性等特点，广泛地被应用于开关电源，汽车电子，马达驱动，高频振荡器等多个领域。Vertical double-diffused metal oxide semiconductor devices (VDMOS, vertical double-diffused Metal Oxide Semiconductor) are widely used in switching power supplies, automotive electronics due to their high input impedance, low drive power, and superior frequency characteristics and thermal stability. , Motor drives, high frequency oscillators and many other fields.
垂直双扩散MOS器件的开启电压直接决定了器件输出特性曲线中截止区以及线性区的电压范围，是器件应用中非常重要的参数。而开启电压直接受沟道长度和浓度的直接影响。The turn-on voltage of the vertical double-diffused MOS device directly determines the voltage range of the cut-off region and the linear region in the output characteristic curve of the device, which is a very important parameter in the application of the device. The turn-on voltage is directly affected by the channel length and concentration.
现有技术中，垂直双扩散MOS器件的制造方法中通常包括分别进行体区扩散和源区扩散，扩散后的源区与体区的差值即为沟道长度。In the prior art, the manufacturing method of the vertical double diffused MOS device usually includes performing body region diffusion and source region diffusion separately, and the difference between the source region and the body region after diffusion is the channel length.
但是，体区扩散和源区扩散通常是通过热过程形成的，即扩散后的体区或源区存在浮动误差，而上述制造方法中经过了两次扩散过程，会使浮动误差增大，进而导致沟道的长度以及浓度不易控制，从而直接影响到器件的开启电压，严重影响垂直双扩散MOS器件的性能。However, body region diffusion and source region diffusion are usually formed through a thermal process, that is, there is a floating error in the diffused body region or source region, and the above-mentioned manufacturing method has undergone two diffusion processes, which will increase the floating error, and then As a result, the length and concentration of the channel are not easy to control, which directly affects the turn-on voltage of the device and seriously affects the performance of the vertical double-diffused MOS device.
发明内容Contents of the invention
本发明提供一种垂直双扩散MOS器件的制作方法，以克服现有的制造方法沟道的长度以及浓度不易控制，进而影响到器件的开启电压的技术问题。The invention provides a method for manufacturing a vertical double-diffused MOS device to overcome the technical problem that the length and concentration of the channel in the existing manufacturing method are difficult to control, thereby affecting the turn-on voltage of the device.
本发明提供一种垂直双扩散MOS器件的制作方法，包括：The invention provides a method for manufacturing a vertical double-diffused MOS device, comprising:
提供衬底，所述衬底上依次形成有外延层、栅氧化层和多晶栅极，去除预设区域内的多晶栅极和部分栅氧化层，以保留预设厚度的栅氧化层，形成凹槽；providing a substrate, on which an epitaxial layer, a gate oxide layer, and a polycrystalline gate are sequentially formed, and removing the polycrystalline gate and part of the gate oxide layer in a predetermined area to retain a predetermined thickness of the gate oxide layer, form grooves;
通过进行体区注入，形成位于所述凹槽下方的所述外延层表面内的第一注射区；forming a first injection region in the surface of the epitaxial layer below the groove by performing body region implantation;
在整个器件的表面上沉积第一氮化硅层；depositing a first silicon nitride layer over the surface of the device;
通过刻蚀，去除位于所述多晶栅极上方和位于所述凹槽底部的第一氮化硅层，保留形成于所述凹槽侧壁上的第一氮化硅层侧墙；removing the first silicon nitride layer located above the polycrystalline gate and at the bottom of the groove by etching, and retaining the sidewalls of the first silicon nitride layer formed on the sidewalls of the groove;
通过进行源区注入，形成位于所述第一注射区内的第二注射区；forming a second injection region located in the first injection region by performing source region implantation;
对整个器件进行加热，以对所述第一注射区和所述第二注射区进行驱入，以形成源区和体区。The entire device is heated to drive in the first injection region and the second injection region to form source and body regions.
进一步地，所述预设厚度为200埃。Further, the preset thickness is 200 angstroms.
进一步地，所述体区注入的注入能量为50KeV-150KeV，剂量为1×1013-5×1013ions/cm2，注入元素为硼元素。Further, the implantation energy of the body region implantation is 50KeV-150KeV, the dose is 1×1013 -5×1013 ions/cm2 , and the implanted element is boron.
进一步地，所述第一氮化硅层的厚度为500埃-1500埃。Further, the thickness of the first silicon nitride layer is 500 Å-1500 Å.
进一步地，所述进行源区注入的注入方式为自对准注入。Further, the implantation method for performing source region implantation is self-aligned implantation.
进一步地，所述源区注入的注入能量为80KeV-150KeV，注入剂量为1×1015-8×1015ions/cm2，注入元素为砷元素。Further, the implantation energy of the source region implantation is 80KeV-150KeV, the implantation dose is 1×1015 -8×1015 ions/cm2 , and the implanted element is arsenic.
进一步地，所述对整个器件进行加热的加热温度为1100℃-1200℃，加热时间为120min-200min。Further, the heating temperature for heating the entire device is 1100°C-1200°C, and the heating time is 120min-200min.
进一步地，所述方法还包括：Further, the method also includes:
在整个器件的表面上沉积介质层，对位于所述源区中央的预设区域及其上方的区域进行刻蚀，直至将源区刻穿，露出所述体区的表面，形成第二凹槽和位于所述第二凹槽外围的源区。Depositing a dielectric layer on the surface of the entire device, etching the preset region located in the center of the source region and the region above it until the source region is etched through, exposing the surface of the body region, and forming a second groove and a source region located on the periphery of the second groove.
进一步地，所述方法还包括：Further, the method also includes:
通过注入，形成位于所述第二凹槽外围的源区之间的区域下方，且位于所述体区内的注入区，所述注入区扩散至所述源区的下方；forming an implanted region located under a region between the source regions on the periphery of the second groove and located in the body region by implanting, and the implanted region diffuses below the source region;
形成位于整个器件表面上的金属层。A metal layer is formed over the entire device surface.
本发明的技术效果是：在已形成的多晶栅极、预设厚度的栅氧化层和凹槽上进行体区注入，以形成位于所述凹槽下方的所述外延层表面内的第一注射区；在整个器件的表面上沉积第一氮化硅层；通过刻蚀，去除位于所述多晶栅极上方和位于所述凹槽底部的第一氮化硅层，保留形成于所述凹槽侧壁上的第一氮化硅层侧墙；进行源区注入，以形成位于所述第一注射区内的第二注射区；对整个器件进行加热，对所述第一注射区和所述第二注射区进行驱入，以形成源区和体区。本发明通过注入后采用一次热扩散形成体区和源区，降低了扩散过程中的浮动误差，使沟道长度精确并且可以控制，有效解决了现有技术中沟道的长度以及浓度不易控制的问题，同时大大降低了器件的生产成本。The technical effect of the present invention is: body region implantation is performed on the formed polycrystalline gate, the gate oxide layer with a preset thickness and the groove, so as to form the first epitaxial layer located under the groove Injection area; depositing a first silicon nitride layer on the surface of the entire device; removing the first silicon nitride layer above the polycrystalline gate and at the bottom of the groove by etching, leaving the layer formed on the the sidewall of the first silicon nitride layer on the sidewall of the groove; perform source region implantation to form a second injection region located in the first injection region; heat the entire device, and perform injection on the first injection region and the first injection region The second injection region is driven in to form a source region and a body region. The present invention adopts one-time thermal diffusion to form the body region and the source region after implantation, which reduces the floating error in the diffusion process, makes the channel length accurate and controllable, and effectively solves the difficulty in controlling the channel length and concentration in the prior art. problem, while greatly reducing the production cost of the device.
附图说明Description of drawings
图1为本发明垂直双扩散MOS器件的制作方法实施例的流程图；Fig. 1 is the flowchart of the manufacturing method embodiment of vertical double diffused MOS device of the present invention;
图2为执行步骤101后形成的器件的主视图；Fig. 2 is the front view of the device formed after performing step 101;
图3为执行步骤102后形成的器件的主视图；Fig. 3 is the front view of the device formed after performing step 102;
图4为执行步骤103后形成的器件的主视图；Fig. 4 is the front view of the device formed after performing step 103;
图5为执行步骤104后形成的器件的主视图；Fig. 5 is the front view of the device formed after performing step 104;
图6为执行步骤105后形成的器件的主视图；Fig. 6 is the front view of the device formed after performing step 105;
图7为执行步骤106后形成的器件的主视图；Fig. 7 is the front view of the device formed after performing step 106;
图8为本发明实施例形成第二凹槽和位于第二凹槽外围的源区后的所述器件的主视图；8 is a front view of the device after forming a second groove and a source region located on the periphery of the second groove according to an embodiment of the present invention;
图9为本发明实施例形成第三注入区和金属层后的所述器件的主视图。FIG. 9 is a front view of the device after forming a third injection region and a metal layer according to an embodiment of the present invention.
具体实施方式detailed description
图1为本发明垂直双扩散MOS器件的制作方法实施例的流程图，如图1所示，本实施例提供的一种垂直双扩散MOS器件的制作方法可以包括：Fig. 1 is a flowchart of an embodiment of a method for manufacturing a vertical double-diffused MOS device of the present invention. As shown in Fig. 1, a method for manufacturing a vertical double-diffused MOS device provided in this embodiment may include:
步骤101，提供衬底，所述衬底上依次形成有外延层、栅氧化层和多晶栅极，去除预设区域内的多晶栅极和部分栅氧化层，以保留预设厚度的栅氧化层，形成凹槽；Step 101, providing a substrate on which an epitaxial layer, a gate oxide layer, and a polycrystalline gate are sequentially formed, and removing the polycrystalline gate and part of the gate oxide layer in a predetermined area to retain a gate with a predetermined thickness. oxide layer, forming grooves;
具体的，执行步骤101后，形成的器件的主视图如图2所示，其中，所述衬底用标号1表示，所述外延层用标号2表示，所述栅氧化层用标号3表示，所述多晶栅极用标号4表示。Specifically, after step 101 is performed, the front view of the formed device is shown in FIG. 2 , wherein the substrate is denoted by reference numeral 1, the epitaxial layer is denoted by reference numeral 2, and the gate oxide layer is denoted by reference numeral 3. The polycrystalline gate is denoted by reference numeral 4 .
其中，衬底1表面形成有外延层2，外延层2表面形成有栅氧化层3，栅氧化层3表面形成有多晶栅极4。可以通过光刻技术，对预设区域内的多晶栅极4和部分栅氧化层3进行刻蚀，以形成凹槽。Wherein, an epitaxial layer 2 is formed on the surface of the substrate 1 , a gate oxide layer 3 is formed on the surface of the epitaxial layer 2 , and a polycrystalline gate 4 is formed on the surface of the gate oxide layer 3 . The polycrystalline gate 4 and part of the gate oxide layer 3 in the predetermined area may be etched by photolithography technology to form grooves.
其中，所述衬底可以为半导体元素，例如单晶硅、多晶硅或非晶结构的硅或硅锗(SiGe)，也可以为混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合。本实施例在此不对其进行限制。Wherein, the substrate can be a semiconductor element, such as monocrystalline silicon, polycrystalline silicon or silicon or silicon germanium (SiGe) with an amorphous structure, or a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, Indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof. This embodiment does not limit it here.
进一步地，栅氧化层3厚度可以为根据器件的开启电压范围设定。优选的厚度为多晶栅极厚度为优选为Further, the thickness of the gate oxide layer 3 can be Set according to the turn-on voltage range of the device. The preferred thickness is The poly gate thickness is preferably
可选的，所述预设厚度的栅氧化层中的预设厚度可以为在不会对影响注入的前提下，保护外延层表面。Optionally, the preset thickness in the gate oxide layer with the preset thickness may be On the premise of not affecting the implantation, the surface of the epitaxial layer is protected.
步骤102，通过进行体区注入，形成位于所述凹槽下方的所述外延层表面内的第一注射区。Step 102 , forming a first injection region in the surface of the epitaxial layer below the groove by performing body region implantation.
具体的，执行步骤102后，形成的器件的主视图如图3所示，其中，所述第一注射区用标号5表示。Specifically, after step 102 is performed, the front view of the formed device is shown in FIG. 3 , wherein the first injection region is denoted by reference numeral 5 .
可选的，所述体区注入的注入能量为50KeV-150KeV，剂量为1×1013-5×1013ions/cm2，注入元素为硼元素。注入时使用掩膜版对预设区域进行注入。Optionally, the implantation energy of the body region implantation is 50KeV-150KeV, the dose is 1×1013-5×1013 ions/cm2, and the implanted element is boron. During injection, a mask is used to inject the preset area.
步骤103，在整个器件的表面上沉积第一氮化硅层；Step 103, depositing a first silicon nitride layer on the entire surface of the device;
具体的，执行步骤103后，形成的器件的主视图如图4所示，其中，所述第一氮化硅层用标号6表示。Specifically, after step 103 is performed, the front view of the formed device is shown in FIG. 4 , wherein the first silicon nitride layer is denoted by reference numeral 6 .
可选的，所述第一氮化硅层的厚度可以为所述第一氮化硅层的厚度可以根据想要获得的沟道长度来确定。优选的第一氮化硅层的厚度可以为Optionally, the thickness of the first silicon nitride layer can be The thickness of the first silicon nitride layer can be determined according to the desired channel length. The preferred thickness of the first silicon nitride layer can be
实际应用中，所述第一氮化硅层可以通过低压化学气相沉积工艺(LowPressure Chemical Vapor Deposition，简称LPCVD)形成。低压化学气相沉积工艺沉积过程简单，不消耗硅衬底，温度低，不会对下面的离子区造成扩散。In practical applications, the first silicon nitride layer may be formed by a low pressure chemical vapor deposition process (Low Pressure Chemical Vapor Deposition, LPCVD for short). The deposition process of the low-pressure chemical vapor deposition process is simple, does not consume the silicon substrate, and the temperature is low, which will not cause diffusion to the ion region below.
步骤104，通过刻蚀，去除位于所述多晶栅极上方和位于所述凹槽底部的第一氮化硅层，保留形成于所述凹槽侧壁上的第一氮化硅层侧墙；Step 104, removing the first silicon nitride layer above the polysilicon gate and at the bottom of the groove by etching, leaving the first silicon nitride layer sidewalls formed on the sidewalls of the groove ;
具体的，执行步骤104后，形成的器件的主视图如图5所示。Specifically, after step 104 is performed, the front view of the formed device is shown in FIG. 5 .
步骤105，通过进行源区注入，形成位于所述第一注射区内的第二注射区；Step 105, forming a second injection region located in the first injection region by performing source region implantation;
具体的，执行步骤105后，形成的器件的主视图如图6所示，其中，所述第二注射区用标号7表示。Specifically, after step 105 is performed, the front view of the formed device is shown in FIG. 6 , wherein the second injection region is denoted by reference numeral 7 .
其中，所述进行源区注入的注入方式可以为自对准注入，即在预设区域整片注入，节省注入成本。Wherein, the implantation method of performing source region implantation may be self-aligned implantation, that is, whole-chip implantation in a predetermined area, so as to save implantation cost.
可选的，所述源区注入的注入能量为80KeV-150KeV，优选的注入能量为120KeV。注入剂量为1×1015-8×1015ions/cm2，优选的注入剂量为6×1015ions/cm2。注入元素为砷元素。Optionally, the implantation energy of the source region implantation is 80KeV-150KeV, and the preferred implantation energy is 120KeV. The injection dose is 1×1015-8×1015 ions/cm2, and the preferred injection dose is 6×1015 ions/cm2. The implanted element is arsenic.
步骤106，对整个器件进行加热，以对所述第一注射区和所述第二注射区进行驱入，以形成源区和体区。Step 106 , heating the entire device to drive into the first injection region and the second injection region to form a source region and a body region.
具体的，执行步骤106后，形成的器件的主视图如图7所示，其中，所述源区用标号8表示，所述体区用标号9表示。Specifically, after step 106 is performed, a front view of the formed device is shown in FIG. 7 , wherein the source region is indicated by a reference number 8 , and the body region is indicated by a reference number 9 .
其中，所述对整个器件进行加热的加热温度可以为1100℃-1200℃，优选温度为1150℃。加热时间可以为120min-200min，优选加热时间为140min。Wherein, the heating temperature for heating the entire device may be 1100°C-1200°C, preferably 1150°C. The heating time can be 120min-200min, preferably 140min.
本实施例，在已形成的多晶栅极、预设厚度的栅氧化层和凹槽上进行体区注入，以形成位于所述凹槽下方的所述外延层表面内的第一注射区；在整个器件的表面上沉积第一氮化硅层；通过刻蚀，去除位于所述多晶栅极上方和位于所述凹槽底部的第一氮化硅层，保留形成于所述凹槽侧壁上的第一氮化硅层侧墙；进行源区注入，以形成位于所述第一注射区内的第二注射区；对整个器件进行加热，对所述第一注射区和所述第二注射区进行驱入，以形成源区和体区。本实施例通过注入后采用一次热扩散形成体区和源区，降低了扩散过程中的浮动误差，使沟道长度精确并且可以控制，有效解决了现有技术中沟道的长度以及浓度不易控制的问题，同时大大降低了器件的生产成本。In this embodiment, body region implantation is performed on the formed polycrystalline gate, the gate oxide layer with a preset thickness and the groove, so as to form a first injection region in the surface of the epitaxial layer below the groove; A first silicon nitride layer is deposited on the surface of the entire device; by etching, the first silicon nitride layer located above the polycrystalline gate and at the bottom of the groove is removed, and the first silicon nitride layer formed on the side of the groove remains the sidewall of the first silicon nitride layer on the wall; implant the source region to form a second injection region located in the first injection region; heat the entire device, and inject the first injection region and the second injection region Two injection regions are driven in to form a source region and a body region. In this embodiment, the body region and the source region are formed by one-time thermal diffusion after implantation, which reduces the floating error in the diffusion process, makes the channel length accurate and controllable, and effectively solves the difficulty in controlling the channel length and concentration in the prior art. problem, while greatly reducing the production cost of the device.
进一步地，垂直双扩散MOS器件的制作方法还可以包括：Further, the manufacturing method of the vertical double-diffused MOS device may also include:
在整个器件的表面上沉积介质层，对位于所述源区中央的预设区域及其上方的区域进行刻蚀，直至将源区刻穿，露出所述体区的表面，形成第二凹槽和位于所述第二凹槽外围的源区。Depositing a dielectric layer on the surface of the entire device, etching the preset region located in the center of the source region and the region above it until the source region is etched through, exposing the surface of the body region, and forming a second groove and a source region located on the periphery of the second groove.
具体的，形成所述第二凹槽和位于所述第二凹槽外围的源区后，所述器件的主视图如图8所示，其中，所述介质层用标号10表示。Specifically, after forming the second groove and the source region located on the periphery of the second groove, the front view of the device is shown in FIG. 8 , wherein the dielectric layer is denoted by reference numeral 10 .
更为具体的，在整个器件的表面上沉积介质层后，首先通过光刻，对位于所述预设区域上方的介质层进行刻蚀，然后对所述源区中央的预设区域进行刻蚀，直至将源区刻穿露出所述体区的表面，以形成位于第二凹槽外围的源区。More specifically, after depositing the dielectric layer on the surface of the entire device, the dielectric layer located above the predetermined region is firstly etched by photolithography, and then the predetermined region in the center of the source region is etched , until the source region is carved through the surface exposing the body region, so as to form a source region located on the periphery of the second groove.
更进一步地，垂直双扩散MOS器件的制作方法还可以包括：Furthermore, the fabrication method of the vertical double-diffused MOS device may also include:
通过注入，形成位于所述第二凹槽外围的源区之间的区域下方，且位于所述体区内的第三注入区，所述第三注入区扩散至所述源区的下方；形成位于整个器件表面上的金属层。By implanting, a third implanted region located under the region between the source regions on the periphery of the second groove and located in the body region is formed, and the third implanted region diffuses to below the source region; forming Metal layer over the entire device surface.
具体的，形成第三注入区和金属层后，所述器件的主视图如图9所示，其中，所述金属层用标号11表示，所述第三注入区用标号12表示。通过对第二凹槽外围的源区之间的区域下方的第三注入区进行注入，并且在整个器件表面上的金属层，可以形成深体区，以提升器件的参数性能。Specifically, after the third injection region and the metal layer are formed, the front view of the device is shown in FIG. 9 , wherein the metal layer is denoted by reference numeral 11 , and the third injection region is denoted by reference numeral 12 . By implanting the third implantation region below the region between the source regions on the periphery of the second groove and the metal layer on the entire surface of the device, a deep body region can be formed to improve the parameter performance of the device.
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510330440.8ACN106328524A (en) | 2015-06-15 | 2015-06-15 | Manufacturing method of vertical double-diffused MOS device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510330440.8ACN106328524A (en) | 2015-06-15 | 2015-06-15 | Manufacturing method of vertical double-diffused MOS device |
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| CN106328524Atrue CN106328524A (en) | 2017-01-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510330440.8APendingCN106328524A (en) | 2015-06-15 | 2015-06-15 | Manufacturing method of vertical double-diffused MOS device |
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| CN (1) | CN106328524A (en) |
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