技术领域technical field
本发明涉及显示技术领域，特别涉及一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。The invention relates to the field of display technology, in particular to a shift register unit, a driving method, a gate driving circuit and a display device.
背景技术Background technique
显示装置在显示图像时，需要利用移位寄存器(栅极驱动电路)对像素单元进行扫描，移位寄存器包括多个移位寄存器单元，每个移位寄存器单元对应一行像素单元，由多个移位寄存器单元实现对显示装置的各行像素单元的逐行扫描驱动，以显示图像。When the display device displays an image, it is necessary to use a shift register (gate drive circuit) to scan the pixel units. The shift register includes a plurality of shift register units, and each shift register unit corresponds to a row of pixel units. The bit register unit implements row-by-row scan driving of each row of pixel units of the display device to display images.
为了提高显示装置的显示灵活性，相关技术中有一种能够实现双向扫描的移位寄存器，该移位寄存器能够实现对显示装置的各行像素单元的正向扫描和反相扫描，该移位寄存器中每个移位寄存器单元通常通过多个晶体管和电容器来控制输出信号的电位的高低。In order to improve the display flexibility of the display device, there is a shift register capable of bidirectional scanning in the related art, and the shift register can realize forward scanning and reverse scanning of each row of pixel units of the display device. Each shift register unit usually controls the potential level of the output signal through a plurality of transistors and capacitors.
但是，该具有双向扫描功能的移位寄存器中，每个移位寄存器单元包含的晶体管个数较多，电路结构较为复杂，移位寄存器的功耗较高。However, in the shift register with bidirectional scanning function, each shift register unit contains a large number of transistors, the circuit structure is relatively complicated, and the power consumption of the shift register is relatively high.
发明内容Contents of the invention
为了解决相关技术中移位寄存器单元电路结构复杂，功耗较高的问题，本发明提供了一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。所述技术方案如下：In order to solve the problem of complex circuit structure and high power consumption of the shift register unit in the related art, the present invention provides a shift register unit, a driving method, a gate driving circuit and a display device. Described technical scheme is as follows:
一方面，提供了一种移位寄存器单元，所述移位寄存器单元包括：In one aspect, a shift register unit is provided, and the shift register unit includes:
输入模块、复位模块、上拉模块、下拉模块和降噪模块；Input module, reset module, pull-up module, pull-down module and noise reduction module;
所述输入模块分别与第一电源信号端、输入信号端和上拉节点连接，所述输入模块用于在来自所述输入信号端的输入信号的控制下，向所述上拉节点输出来自所述第一电源信号端的第一电源信号；The input module is respectively connected to the first power signal terminal, the input signal terminal and the pull-up node, and the input module is used to output the signal from the pull-up node to the pull-up node under the control of the input signal from the input signal terminal. a first power signal at the first power signal terminal;
所述复位模块分别与第二电源信号端、复位信号端和所述上拉节点连接，所述复位模块用于在来自所述复位信号端的复位信号的控制下，向所述上拉节点输出来自所述第二电源信号端的第二电源信号；The reset module is respectively connected to the second power supply signal terminal, the reset signal terminal and the pull-up node, and the reset module is used to output the signal from the pull-up node to the pull-up node under the control of the reset signal from the reset signal terminal. a second power signal at the second power signal terminal;
所述上拉模块分别与第一时钟信号端、所述上拉节点和输出端连接，用于在所述上拉节点的控制下，向所述输出端输出来自所述第一时钟信号端的第一时钟信号；The pull-up module is respectively connected to the first clock signal terminal, the pull-up node and the output terminal, and is used to output the first clock signal from the first clock signal terminal to the output terminal under the control of the pull-up node. a clock signal;
所述下拉模块分别与第二时钟信号端、第三电源信号端、所述上拉节点和下拉节点连接，用于在来自所述第二时钟信号端的第二时钟信号和所述上拉节点的控制下，向所述下拉节点输出来自所述第三电源信号端的第三电源信号或所述第二时钟信号；The pull-down module is respectively connected to the second clock signal end, the third power signal end, the pull-up node and the pull-down node, and is used to transmit the second clock signal from the second clock signal end to the pull-up node. Under control, output a third power signal from the third power signal terminal or the second clock signal to the pull-down node;
所述降噪模块分别与所述下拉节点、所述上拉节点、第三电源信号端和所述输出端连接，用于在所述下拉节点的控制下，分别向所述上拉节点和所述输出端输出所述第三电源信号。The noise reduction module is respectively connected to the pull-down node, the pull-up node, the third power supply signal terminal and the output terminal, and is used to send signals to the pull-up node and the The output terminal outputs the third power signal.
可选的，所述输入模块，包括：第一晶体管；所述复位模块，包括：第二晶体管；Optionally, the input module includes: a first transistor; the reset module includes: a second transistor;
所述第一晶体管的第一极与所述第一电源信号端连接，所述第一晶体管的第二极与所述上拉节点连接，所述第一晶体管的栅极与所述输入信号端连接；The first pole of the first transistor is connected to the first power signal terminal, the second pole of the first transistor is connected to the pull-up node, the gate of the first transistor is connected to the input signal terminal connect;
所述第二晶体管的第一极与所述第二电源信号端连接，所述第二晶体管的第二极与所述上拉节点连接，所述第二晶体管的栅极与所述复位信号端连接。The first pole of the second transistor is connected to the second power signal terminal, the second pole of the second transistor is connected to the pull-up node, the gate of the second transistor is connected to the reset signal terminal connect.
可选的，所述输入模块，包括：第二晶体管；所述复位模块，包括：第一晶体管；Optionally, the input module includes: a second transistor; the reset module includes: a first transistor;
所述第二晶体管的第一极与所述第一电源信号端连接，所述第二晶体管的第二极与所述上拉节点连接，所述第二晶体管的栅极与所述输入信号端连接；The first pole of the second transistor is connected to the first power signal terminal, the second pole of the second transistor is connected to the pull-up node, the gate of the second transistor is connected to the input signal terminal connect;
所述第一晶体管的第一极与所述第二电源信号端连接，所述第一晶体管的第二极与所述上拉节点连接，所述第一晶体管的栅极与所述复位信号端连接。The first pole of the first transistor is connected to the second power signal terminal, the second pole of the first transistor is connected to the pull-up node, the gate of the first transistor is connected to the reset signal terminal connect.
可选的，所述上拉模块，包括：第三晶体管和第一电容器；Optionally, the pull-up module includes: a third transistor and a first capacitor;
所述第三晶体管的第一极与所述第一时钟信号端连接，所述第三晶体管的第二极与所述输出端连接，所述第三晶体管的栅极与所述上拉节点连接；The first pole of the third transistor is connected to the first clock signal terminal, the second pole of the third transistor is connected to the output terminal, and the gate of the third transistor is connected to the pull-up node ;
所述第一电容器的一端与所述上拉节点连接，所述第一电容器的另一端与所述输出端连接。One end of the first capacitor is connected to the pull-up node, and the other end of the first capacitor is connected to the output end.
可选的，所述下拉模块包括：第四晶体管、第五晶体管和第二电容器；Optionally, the pull-down module includes: a fourth transistor, a fifth transistor and a second capacitor;
所述第四晶体管的第一极和栅极与所述第二时钟信号端连接，所述第四晶体管的第二极与所述下拉节点连接；The first electrode and the gate of the fourth transistor are connected to the second clock signal terminal, and the second electrode of the fourth transistor is connected to the pull-down node;
所述第五晶体管的第一极与所述第三电源信号端连接，所述第五晶体管的第二极与所述下拉节点连接，所述第五晶体管的栅极与所述上拉节点连接；The first pole of the fifth transistor is connected to the third power signal terminal, the second pole of the fifth transistor is connected to the pull-down node, and the gate of the fifth transistor is connected to the pull-up node ;
所述第二电容器的一端与所述第三电源信号端连接，所述第二电容器的另一端与所述下拉节点连接。One end of the second capacitor is connected to the third power signal end, and the other end of the second capacitor is connected to the pull-down node.
可选的，所述降噪模块包括：第六晶体管和第七晶体管；Optionally, the noise reduction module includes: a sixth transistor and a seventh transistor;
所述第六晶体管的第一极与所述第三电源信号端连接，所述第六晶体管的第二极与所述上拉节点连接，所述第六晶体管的栅极与所述下拉节点连接；The first pole of the sixth transistor is connected to the third power signal terminal, the second pole of the sixth transistor is connected to the pull-up node, and the gate of the sixth transistor is connected to the pull-down node ;
所述第七晶体管的第一极与所述第三电源信号端连接，所述第七晶体管的第二极与所述输出端连接，所述第七晶体管的栅极与所述下拉节点连接。A first pole of the seventh transistor is connected to the third power signal terminal, a second pole of the seventh transistor is connected to the output terminal, and a gate of the seventh transistor is connected to the pull-down node.
可选的，所述晶体管均为N型晶体管。Optionally, the transistors are all N-type transistors.
第二方面，提供了一种移位寄存器单元的驱动方法，所述移位寄存器单元包括：输入模块、复位模块、上拉模块、下拉模块和降噪模块，所述驱动方法包括：In a second aspect, a driving method of a shift register unit is provided, the shift register unit includes: an input module, a reset module, a pull-up module, a pull-down module, and a noise reduction module, and the driving method includes:
输入阶段：第一电源信号端输入的第一电源信号为第一电位，输入信号端输入的输入信号为第一电位，所述输入模块控制上拉节点的电位为第一电位；Input stage: the first power signal input by the first power signal terminal is the first potential, the input signal input by the input signal terminal is the first potential, and the input module controls the potential of the pull-up node to be the first potential;
输出阶段：所述上拉节点保持第一电位，第一时钟信号端输入的第一时钟信号为第一电位，所述上拉模块在所述上拉节点的控制下，向输出端输出所述第一时钟信号；Output stage: the pull-up node maintains the first potential, the first clock signal input by the first clock signal terminal is the first potential, and the pull-up module outputs the first clock signal;
复位阶段：复位信号端输入的复位信号为第一电位，第二电源信号端输入的第二电源信号为第二电位，所述复位模块控制所述上拉节点的电位为第二电位；Reset stage: the reset signal input by the reset signal terminal is the first potential, the second power signal input by the second power signal terminal is the second potential, and the reset module controls the potential of the pull-up node to be the second potential;
保持阶段：所述第一时钟信号为第一电位，第二时钟信号端输入的第二时钟信号为第二电位，所述上拉节点保持第二电位；Holding stage: the first clock signal is at the first potential, the second clock signal input from the second clock signal terminal is at the second potential, and the pull-up node maintains the second potential;
降噪阶段：所述第二时钟信号为第一电位，第三电源信号端输入的第三电源信号为第二电位，所述下拉模块控制所述下拉节点为第一电位，所述降噪模块在所述下拉节点的控制下，分别向所述上拉节点和所述输出端输出所述第三电源信号。Noise reduction stage: the second clock signal is at the first potential, the third power signal input from the third power signal terminal is at the second potential, the pull-down module controls the pull-down node to be at the first potential, and the noise reduction module Under the control of the pull-down node, output the third power supply signal to the pull-up node and the output terminal respectively.
可选的，在正向扫描时，所述输入模块包括：第一晶体管；所述复位模块包括：第二晶体管；所述上拉模块包括：第三晶体管和第一电容器；所述下拉模块包括：第四晶体管、第五晶体管和第二电容器；所述降噪模块包括：第六晶体管和第七晶体管；Optionally, during forward scanning, the input module includes: a first transistor; the reset module includes: a second transistor; the pull-up module includes: a third transistor and a first capacitor; the pull-down module includes : a fourth transistor, a fifth transistor and a second capacitor; the noise reduction module includes: a sixth transistor and a seventh transistor;
所述输入阶段中，所述输入信号端输入的所述输入信号为第一电位，所述第一晶体管开启，所述第一电源信号端向所述上拉节点输出所述第一电源信号；In the input phase, the input signal input by the input signal terminal is a first potential, the first transistor is turned on, and the first power signal terminal outputs the first power signal to the pull-up node;
所述输出阶段中，所述上拉节点保持第一电位，所述第三晶体管和所述第五晶体管开启，所述第一时钟信号端向所述输出端输出所述第一时钟信号，所述第三电源信号端向所述下拉节点输出所述第三电源信号，所述第六晶体管和所述第七晶体管关断；In the output stage, the pull-up node maintains a first potential, the third transistor and the fifth transistor are turned on, and the first clock signal terminal outputs the first clock signal to the output terminal, so The third power signal terminal outputs the third power signal to the pull-down node, and the sixth transistor and the seventh transistor are turned off;
所述复位阶段中，所述复位信号端输入的复位信号为第一电位，所述第二晶体管开启，所述第二电源信号端向所述上拉节点输出所述第二电源信号；In the reset phase, the reset signal input by the reset signal terminal is a first potential, the second transistor is turned on, and the second power signal terminal outputs the second power signal to the pull-up node;
所述保持阶段中，所述第一时钟信号为第一电位，所述第二时钟信号为第二电位，所述第四晶体管关断，所述上拉节点保持第二电位，所述第三晶体管关断；In the holding phase, the first clock signal is at a first potential, the second clock signal is at a second potential, the fourth transistor is turned off, the pull-up node maintains a second potential, and the third Transistor off;
所述降噪阶段中，所述第二时钟信号为第一电位，所述第三电源信号为第二电位，所述第四晶体管开启，所述第二时钟信号端向所述下拉节点输出所述第二时钟信号，所述第六晶体管和所述第七晶体管开启，所述第三电源信号端分别向所述上拉节点和所述输出端输出所述第三电源信号。In the noise reduction stage, the second clock signal is at the first potential, the third power signal is at the second potential, the fourth transistor is turned on, and the second clock signal terminal outputs the The second clock signal, the sixth transistor and the seventh transistor are turned on, and the third power signal terminal outputs the third power signal to the pull-up node and the output terminal respectively.
可选的，在反向扫描时，所述输入模块包括：第二晶体管；所述复位模块包括：第一晶体管；所述上拉模块包括：第三晶体管和第一电容器；所述下拉模块包括：第四晶体管、第五晶体管和第二电容器；所述降噪模块包括：第六晶体管和第七晶体管；Optionally, during reverse scanning, the input module includes: a second transistor; the reset module includes: a first transistor; the pull-up module includes: a third transistor and a first capacitor; the pull-down module includes : a fourth transistor, a fifth transistor and a second capacitor; the noise reduction module includes: a sixth transistor and a seventh transistor;
所述输入阶段中，所述输入信号端输入的所述输入信号为第一电位，所述第二晶体管开启，所述第一电源信号端向所述上拉节点输出所述第一电源信号；In the input stage, the input signal input by the input signal terminal is a first potential, the second transistor is turned on, and the first power signal terminal outputs the first power signal to the pull-up node;
所述输出阶段中，所述上拉节点保持第一电位，所述第三晶体管和所述第五晶体管开启，所述第一时钟信号端向所述输出端输出所述第一时钟信号，所述第三电源信号端向所述下拉节点输出所述第三电源信号，所述第六晶体管和所述第七晶体管关断；In the output stage, the pull-up node maintains a first potential, the third transistor and the fifth transistor are turned on, and the first clock signal terminal outputs the first clock signal to the output terminal, so The third power signal terminal outputs the third power signal to the pull-down node, and the sixth transistor and the seventh transistor are turned off;
所述复位阶段中，所述复位信号端输入的复位信号为第一电位，所述第一晶体管开启，所述第二电源信号端向所述上拉节点输出所述第二电源信号；In the reset phase, the reset signal input by the reset signal terminal is a first potential, the first transistor is turned on, and the second power signal terminal outputs the second power signal to the pull-up node;
所述保持阶段中，所述第一时钟信号为第一电位，所述第二时钟信号为第二电位，所述第四晶体管关断，所述上拉节点保持第二电位，所述第三晶体管关断；In the holding phase, the first clock signal is at a first potential, the second clock signal is at a second potential, the fourth transistor is turned off, the pull-up node maintains a second potential, and the third Transistor off;
所述降噪阶段中，所述第二时钟信号为第一电位，所述第三电源信号为第二电位，所述第四晶体管开启，所述第二时钟信号端向所述下拉节点输出所述第二时钟信号，所述第六晶体管和所述第七晶体管开启，所述第三电源信号端分别向所述上拉节点和所述输出端输出所述第三电源信号。In the noise reduction stage, the second clock signal is at the first potential, the third power signal is at the second potential, the fourth transistor is turned on, and the second clock signal terminal outputs the The second clock signal, the sixth transistor and the seventh transistor are turned on, and the third power signal terminal outputs the third power signal to the pull-up node and the output terminal respectively.
可选的，所述晶体管均为N型晶体管，所述第一电位相对于所述第二电位为高电位。Optionally, the transistors are all N-type transistors, and the first potential is a higher potential than the second potential.
第三方面，提供了一种栅极驱动电路，所述栅极驱动电路包括至少两个级联的如第一方面所述的移位寄存器单元。In a third aspect, a gate driving circuit is provided, and the gate driving circuit includes at least two cascaded shift register units as described in the first aspect.
第四方面，提供了一种显示装置，所述显示装置包括如第三方面所述的栅极驱动电路。In a fourth aspect, a display device is provided, and the display device includes the gate driving circuit as described in the third aspect.
本发明提供的技术方案带来的有益效果是：The beneficial effects brought by the technical scheme provided by the invention are:
本发明提供了一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。该移位寄存器单元包括：输入模块、复位模块、上拉模块、下拉模块和降噪模块，其中，输入模块用于向上拉节点输出第一电源信号，复位模块用于向上拉节点输出第二电源信号，上拉模块用于在上拉节点的控制下，向输出端输出第一时钟信号，下拉模块用于在第二时钟信号和上拉节点的控制下，向下拉节点输出第三电源信号或第二时钟信号，降噪模块用于在下拉节点的控制下，分别向上拉节点和输出端输出第三电源信号。本发明提供的移位寄存器单元的电路结构和控制过程均较为简单，降低了移位寄存器的功耗，解决了相关技术中移位寄存器单元电路结构复杂的问题。The invention provides a shift register unit, a driving method, a gate driving circuit and a display device. The shift register unit includes: an input module, a reset module, a pull-up module, a pull-down module and a noise reduction module, wherein the input module is used to output the first power signal to the pull-up node, and the reset module is used to output the second power supply to the pull-up node signal, the pull-up module is used to output the first clock signal to the output terminal under the control of the pull-up node, and the pull-down module is used to output the third power signal to the pull-up node under the control of the second clock signal and the pull-up node or The second clock signal, the noise reduction module is used to output the third power signal to the pull-up node and the output end respectively under the control of the pull-down node. The circuit structure and control process of the shift register unit provided by the invention are relatively simple, which reduces the power consumption of the shift register and solves the problem of complex circuit structure of the shift register unit in the related art.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.
图1是本发明实施例提供的一种移位寄存器单元的结构示意图；FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present invention;
图2-1是本发明实施例提供的另一种移位寄存器单元的结构示意图；Fig. 2-1 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention;
图2-2是本发明实施例提供的又一种移位寄存器单元的结构示意图；Fig. 2-2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention;
图3-1是本发明实施例提供的一种移位寄存器单元的驱动方法的流程图；Fig. 3-1 is a flowchart of a driving method for a shift register unit provided by an embodiment of the present invention;
图3-2是本发明实施例提供的一种移位寄存器单元的正向扫描的时序图；Fig. 3-2 is a timing diagram of forward scanning of a shift register unit provided by an embodiment of the present invention;
图3-3是本发明实施例提供的一种移位寄存器单元的反向扫描的时序图；Fig. 3-3 is a timing diagram of reverse scanning of a shift register unit provided by an embodiment of the present invention;
图4是本发明实施例提供的一种栅极驱动电路的结构示意图。FIG. 4 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.
本发明所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本发明的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中源极称为第一极，漏极称为第二极，因此，晶体管的栅极也可以称为第三极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。本发明实施例所采用的开关晶体管为N型开关晶体管，N型开关晶体管为在栅极为高电位时导通，在栅极为低电位时截止。在本发明实施例中，第一电位为高电位，第二电位为低电位。此外，本发明各个实施例中的多个信号都对应有第一电位和第二电位。第一电位和第二电位仅代表该信号的电位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值。The transistors used in all the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present invention are mainly switching transistors according to their functions in circuits. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, the source is called the first pole, and the drain is called the second pole. Therefore, the gate of the transistor can also be called the third pole. According to the form in the accompanying drawings, it is stipulated that the middle terminal of the transistor is the gate, the signal input terminal is the source terminal, and the signal output terminal is the drain terminal. The switch transistor used in the embodiment of the present invention is an N-type switch transistor, and the N-type switch transistor is turned on when the gate is at a high potential, and is turned off when the gate is at a low potential. In the embodiment of the present invention, the first potential is a high potential, and the second potential is a low potential. In addition, the multiple signals in each embodiment of the present invention correspond to the first potential and the second potential. The first potential and the second potential only mean that the potential of the signal has two state quantities, and it does not mean that the first potential or the second potential has a specific value in the full text.
图1是本发明实施例提供的一种移位寄存器单元的结构示意图，如图1所示，该移位寄存器单元可以包括：输入模块10、复位模块20、上拉模块30、下拉模块40和降噪模块50。Fig. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present invention. As shown in Fig. 1, the shift register unit may include: an input module 10, a reset module 20, a pull-up module 30, a pull-down module 40 and Noise reduction module 50.
该输入模块10分别与第一电源信号端VDD、输入信号端INPUT和上拉节点PU连接，该输入模块10用于在来自该输入信号端INPUT的输入信号的控制下，向该上拉节点PU输出来自该第一电源信号端VDD的第一电源信号。The input module 10 is respectively connected to the first power signal terminal VDD, the input signal terminal INPUT and the pull-up node PU. Outputting a first power signal from the first power signal terminal VDD.
该复位模块20分别与第二电源信号端VSS、复位信号端RST和该上拉节点PU连接，该复位模块20用于在来自该复位信号端RST的复位信号的控制下，向该上拉节点PU输出来自该第二电源信号端VSS的第二电源信号。The reset module 20 is respectively connected to the second power supply signal terminal VSS, the reset signal terminal RST and the pull-up node PU. The PU outputs a second power signal from the second power signal terminal VSS.
该上拉模块30分别与第一时钟信号端CLK、该上拉节点PU和输出端OUTPUT连接，用于在该上拉节点PU的控制下，向该输出端OUTPUT输出来自该第一时钟信号端CLK的第一时钟信号。The pull-up module 30 is respectively connected to the first clock signal terminal CLK, the pull-up node PU and the output terminal OUTPUT, and is used to output the clock signal from the first clock signal terminal to the output terminal OUTPUT under the control of the pull-up node PU. CLK is the first clock signal.
该下拉模块40分别与第二时钟信号端CLKB、第三电源信号端VGL、该上拉节点PU和下拉节点PD连接，用于在来自该第二时钟信号端CLKB的第二时钟信号和该上拉节点PU的控制下，向该下拉节点PD输出来自该第三电源信号端VGL的第三电源信号或该第二时钟信号。The pull-down module 40 is respectively connected with the second clock signal terminal CLKB, the third power signal terminal VGL, the pull-up node PU and the pull-down node PD, and is used for receiving the second clock signal from the second clock signal terminal CLKB and the upper Under the control of the pull-down node PU, the third power signal or the second clock signal from the third power signal terminal VGL is output to the pull-down node PD.
该降噪模块50分别与该下拉节点PD、该上拉节点PU、第三电源信号端VGL和该输出端OUTPUT连接，用于在该下拉节点PD的控制下，分别向该上拉节点PU和该输出端OUTPUT输出该第三电源信号。The noise reduction module 50 is respectively connected with the pull-down node PD, the pull-up node PU, the third power signal terminal VGL and the output terminal OUTPUT, and is used to provide the pull-up node PU and the The output terminal OUTPUT outputs the third power signal.
综上所述，本发明实施例提供了一种移位寄存器单元，该移位寄存器单元包括：输入模块、复位模块、上拉模块、下拉模块和降噪模块，该移位寄存器单元能够实现对显示装置中各行像素单元的双向扫描，并且该移位寄存器单元的电路结构和控制过程均较为简单，不仅降低了移位寄存器的功耗，而且通过降噪模块减小了移位寄存器单元中上拉节点和输出端的噪音，改善了移位寄存器单元的输出效果。To sum up, the embodiment of the present invention provides a shift register unit, the shift register unit includes: an input module, a reset module, a pull-up module, a pull-down module and a noise reduction module, the shift register unit can realize Bi-directional scanning of pixel units in each row in the display device, and the circuit structure and control process of the shift register unit are relatively simple, which not only reduces the power consumption of the shift register, but also reduces the upper and lower power consumption of the shift register unit through the noise reduction module. Noise at the pull node and output improves the output of the shift register unit.
图2-1是本发明实施例提供的另一种移位寄存器单元的结构示意图，如图2-1所示，该输入模块10可以包括：第一晶体管M1；该复位模块20可以包括：第二晶体管M2。Fig. 2-1 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention. As shown in Fig. 2-1, the input module 10 may include: a first transistor M1; the reset module 20 may include: a second Two transistors M2.
该第一晶体管M1的第一极与该第一电源信号端VDD连接，该第一晶体管M1的第二极与该上拉节点PU连接，该第一晶体管M1的栅极与该输入信号端INPUT连接。The first pole of the first transistor M1 is connected to the first power signal terminal VDD, the second pole of the first transistor M1 is connected to the pull-up node PU, the gate of the first transistor M1 is connected to the input signal terminal INPUT connect.
该第二晶体管M2的第一极与该第二电源信号端VSS连接，该第二晶体管M2的第二极与该上拉节点PU连接，该第二晶体管M2的栅极与该复位信号端RST连接。The first pole of the second transistor M2 is connected to the second power signal terminal VSS, the second pole of the second transistor M2 is connected to the pull-up node PU, the gate of the second transistor M2 is connected to the reset signal terminal RST connect.
图2-2是本发明实施例提供的另一种移位寄存器单元的结构示意图，如图2-2所示，该输入模块10可以包括：第二晶体管M2；该复位模块20可以包括：第一晶体管M1。Fig. 2-2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present invention. As shown in Fig. 2-2, the input module 10 may include: a second transistor M2; the reset module 20 may include: a first A transistor M1.
该第二晶体管M2的第一极与该第一电源信号端VDD连接，该第二晶体管M2的第二极与该上拉节点PU连接，该第二晶体管M2的栅极与该输入信号端INPUT连接。The first pole of the second transistor M2 is connected to the first power signal terminal VDD, the second pole of the second transistor M2 is connected to the pull-up node PU, the gate of the second transistor M2 is connected to the input signal terminal INPUT connect.
该第一晶体管M1的第一极与该第二电源信号端VSS连接，该第一晶体管M1的第二极与该上拉节点PU连接，该第一晶体管M1的栅极与该复位信号端RST连接。The first pole of the first transistor M1 is connected to the second power signal terminal VSS, the second pole of the first transistor M1 is connected to the pull-up node PU, the gate of the first transistor M1 is connected to the reset signal terminal RST connect.
可选的，参考图2-1以及图2-2，该上拉模块30可以包括：第三晶体管M3和第一电容器C1。Optionally, referring to FIG. 2-1 and FIG. 2-2, the pull-up module 30 may include: a third transistor M3 and a first capacitor C1.
该第三晶体管M3的第一极与该第一时钟信号端CLK连接，该第三晶体管M3的第二极与该输出端OUTPUT连接，该第三晶体管M3的栅极与该上拉节点PU连接。The first pole of the third transistor M3 is connected to the first clock signal terminal CLK, the second pole of the third transistor M3 is connected to the output terminal OUTPUT, and the gate of the third transistor M3 is connected to the pull-up node PU .
该第一电容器C1的一端与该上拉节点PU连接，该第一电容器C1的另一端与该输出端OUTPUT连接。One end of the first capacitor C1 is connected to the pull-up node PU, and the other end of the first capacitor C1 is connected to the output terminal OUTPUT.
可选的，该下拉模块40包括：第四晶体管M4、第五晶体管M5和第二电容器C2。Optionally, the pull-down module 40 includes: a fourth transistor M4, a fifth transistor M5 and a second capacitor C2.
该第四晶体管M4的第一极和栅极与该第二时钟信号端CLKB连接，该第四晶体管M4的第二极与该下拉节点PD连接。The first electrode and the gate of the fourth transistor M4 are connected to the second clock signal terminal CLKB, and the second electrode of the fourth transistor M4 is connected to the pull-down node PD.
该第五晶体管M5的第一极与该第三电源信号端VGL连接，该第五晶体管M5的第二极与该下拉节点PD连接，该第五晶体管M5的栅极与该上拉节点PU连接；The first pole of the fifth transistor M5 is connected to the third power signal terminal VGL, the second pole of the fifth transistor M5 is connected to the pull-down node PD, and the gate of the fifth transistor M5 is connected to the pull-up node PU ;
该第二电容器C2的一端与该第三电源信号端VGL连接，该第二电容器C2的另一端与该下拉节点PD连接。One end of the second capacitor C2 is connected to the third power signal terminal VGL, and the other end of the second capacitor C2 is connected to the pull-down node PD.
可选的，该降噪模块50包括：第六晶体管M6和第七晶体管M7。Optionally, the noise reduction module 50 includes: a sixth transistor M6 and a seventh transistor M7.
该第六晶体管M6的第一极与该第三电源信号端VGL连接，该第六晶体管M6的第二极与该上拉节点PU连接，该第六晶体管M6的栅极与该下拉节点PD连接；The first pole of the sixth transistor M6 is connected to the third power signal terminal VGL, the second pole of the sixth transistor M6 is connected to the pull-up node PU, and the gate of the sixth transistor M6 is connected to the pull-down node PD ;
该第七晶体管M7的第一极与该第三电源信号端VGL连接，该第七晶体管M7的第二极与该输出端OUTPUT连接，该第七晶体管M7的栅极与该下拉节点PD连接。A first pole of the seventh transistor M7 is connected to the third power signal terminal VGL, a second pole of the seventh transistor M7 is connected to the output terminal OUTPUT, and a gate of the seventh transistor M7 is connected to the pull-down node PD.
综上所述，本发明实施例提供了一种移位寄存器单元，该移位寄存器单元包括：输入模块、复位模块、上拉模块、下拉模块和降噪模块，该移位寄存器单元能够实现对显示装置中各行像素单元的双向扫描，并且该移位寄存器单元的中仅包括七个晶体管和两个电容器，该移位寄存器单元的电路结构和控制过程均较为简单，不仅降低了移位寄存器的功耗，而且可以通过降噪模块减小移位寄存器单元中上拉节点和输出端的噪音，改善了移位寄存器单元的输出效果。To sum up, the embodiment of the present invention provides a shift register unit, the shift register unit includes: an input module, a reset module, a pull-up module, a pull-down module and a noise reduction module, the shift register unit can realize Bi-directional scanning of pixel units in each row in the display device, and the shift register unit only includes seven transistors and two capacitors, the circuit structure and control process of the shift register unit are relatively simple, which not only reduces the Power consumption, and the noise of the pull-up node and the output terminal in the shift register unit can be reduced by the noise reduction module, and the output effect of the shift register unit is improved.
图3-1是本发明实施例提供的一种移位寄存器单元的驱动方法的流程图，如图1所示，该移位寄存器单元可以包括：输入模块10、复位模块20、上拉模块30、下拉模块40和降噪模块50，参考图3-1，该驱动方法可以包括：Fig. 3-1 is a flowchart of a driving method of a shift register unit provided by an embodiment of the present invention. As shown in Fig. 1, the shift register unit may include: an input module 10, a reset module 20, and a pull-up module 30 , pull-down module 40 and noise reduction module 50, with reference to Fig. 3-1, this driving method can comprise:
步骤301、输入阶段：第一电源信号端VDD输入的第一电源信号为第一电位，输入信号端INPUT输入的输入信号为第一电位，该输入模块10控制上拉节点PU的电位为第一电位。Step 301, input stage: the first power signal input by the first power signal terminal VDD is the first potential, the input signal input by the input signal terminal INPUT is the first potential, and the input module 10 controls the potential of the pull-up node PU to be the first potential.
步骤302、输出阶段：该上拉节点PU保持第一电位，第一时钟信号端CLK输入的第一时钟信号为第一电位，该上拉模块30在该上拉节点PU的控制下，向输出端OUTPUT输出该第一时钟信号。Step 302, output stage: the pull-up node PU maintains the first potential, the first clock signal input by the first clock signal terminal CLK is the first potential, and the pull-up module 30 outputs to the output voltage under the control of the pull-up node PU The terminal OUTPUT outputs the first clock signal.
步骤303、复位阶段：复位信号端RST输入的复位信号为第一电位，第二电源信号端VSS输入的第二电源信号为第二电位，该复位模块20控制该上拉节点PU的电位为第二电位。Step 303, reset phase: the reset signal input by the reset signal terminal RST is the first potential, the second power signal input by the second power signal terminal VSS is the second potential, and the reset module 20 controls the potential of the pull-up node PU to be the second potential two potentials.
步骤304、保持阶段：该第一时钟信号为第一电位，第二时钟信号端CLKB输入的第二时钟信号为第二电位，该上拉节点PU保持第二电位。Step 304 , holding stage: the first clock signal is at the first potential, the second clock signal input from the second clock signal terminal CLKB is at the second potential, and the pull-up node PU maintains the second potential.
步骤305、降噪阶段：该第二时钟信号为第一电位，第三电源信号端VGL输入的第三电源信号为第二电位，该下拉模块40控制该下拉节点PD为第一电位，该降噪模块50在该下拉节点PD的控制下，分别向该上拉节点PU和该输出端OUTPUT输出该第三电源信号。Step 305, noise reduction stage: the second clock signal is at the first potential, the third power signal input from the third power signal terminal VGL is at the second potential, the pull-down module 40 controls the pull-down node PD to be at the first potential, the drop-down Under the control of the pull-down node PD, the noise module 50 outputs the third power signal to the pull-up node PU and the output terminal OUTPUT respectively.
综上所述，本发明实施例提供了一种移位寄存器单元的驱动方法，该移位寄存器单元包括：输入模块、复位模块、上拉模块、下拉模块和降噪模块，该移位寄存器单元能够实现对显示装置中各行像素单元的双向扫描，并且该移位寄存器单元的电路结构和控制过程均较为简单。In summary, the embodiment of the present invention provides a driving method for a shift register unit, the shift register unit includes: an input module, a reset module, a pull-up module, a pull-down module and a noise reduction module, the shift register unit The bidirectional scanning of pixel units in each row in the display device can be realized, and the circuit structure and control process of the shift register unit are relatively simple.
图3-2是本发明实施例提供的一种移位寄存器单元的正向扫描的时序图，参考图2-1，在正向扫描时，该输入模块10可以包括：第一晶体管M1；该复位模块20可以包括：第二晶体管M2；该上拉模块30可以包括：第三晶体管M3和第一电容器C1；该下拉模块40可以包括：第四晶体管M4、第五晶体管M5和第二电容器C2；该降噪模块50可以包括：第六晶体管M6和第七晶体管M7。参考图3-2，该方法可以包括：Fig. 3-2 is a timing diagram of forward scanning of a shift register unit provided by an embodiment of the present invention. Referring to Fig. 2-1, during forward scanning, the input module 10 may include: a first transistor M1; The reset module 20 may include: a second transistor M2; the pull-up module 30 may include: a third transistor M3 and a first capacitor C1; the pull-down module 40 may include: a fourth transistor M4, a fifth transistor M5, and a second capacitor C2 ; The noise reduction module 50 may include: a sixth transistor M6 and a seventh transistor M7. Referring to Figure 3-2, the method may include:
以第n级移位寄存器单元为例，在上述步骤301中，该输入阶段中T1，该第n级移位寄存器单元的输入信号端INPUT输入的该输入信号(即第n-1级移位寄存器单元的输出信号)为第一电位，该第一晶体管M1开启，该第一电源信号端VDD向该上拉节点PU输出该第一电源信号，该第一电源信号能够给第一电容器C1充电，从而使得该上拉节点PU的电位被拉高。同时，由于该输入阶段T1中，第二时钟信号端CLKB输入的第二时钟信号为第二电位，第四晶体管M4关断，该上拉节点PU的高电位使得第五晶体管M5开启，第三电源信号端VGL向下拉节点PD和第二电容器C2输出第三电源信号，该第三电源信号为第二电位，此时第六晶体管M6和第七晶体管M7关断，从而保证了信号的稳定输出。Taking the nth stage shift register unit as an example, in the above-mentioned step 301, in the input stage T1, the input signal input by the input signal terminal INPUT of the n stage shift register unit (i.e. n-1 stage shift The output signal of the register unit) is the first potential, the first transistor M1 is turned on, the first power signal terminal VDD outputs the first power signal to the pull-up node PU, and the first power signal can charge the first capacitor C1 , so that the potential of the pull-up node PU is pulled high. At the same time, because in the input phase T1, the second clock signal input by the second clock signal terminal CLKB is at the second potential, the fourth transistor M4 is turned off, and the high potential of the pull-up node PU makes the fifth transistor M5 turn on, and the third The power signal terminal VGL outputs a third power signal to the pull-down node PD and the second capacitor C2, and the third power signal is at the second potential. At this time, the sixth transistor M6 and the seventh transistor M7 are turned off, thus ensuring the stable output of the signal .
在上述步骤302中，该输出阶段T2中，该上拉节点PU的电压由于自举效应(英文：bootstrapping)被进一步放大，该第三晶体管M3和第五晶体管M5开启，该第一时钟信号端CLK向该输出端OUTPUT输出驱动信号，该驱动信号即为该第一时钟信号，此时该第一时钟信号为第一电位；该第三电源信号端VGL向该下拉节点PD和第二电容器C2输出该第三电源信号，该第三电源信号为第二电位，从而实现对该下拉节点PD和第二电容器C2的放电，此时该第六晶体管M6和该第七晶体管M7关断，从而可以保证输出端OUTPUT稳定的输出该第一时钟信号。In the above step 302, in the output stage T2, the voltage of the pull-up node PU is further amplified due to the bootstrapping effect (English: bootstrapping), the third transistor M3 and the fifth transistor M5 are turned on, and the first clock signal terminal CLK outputs a driving signal to the output terminal OUTPUT, and the driving signal is the first clock signal, and the first clock signal is at the first potential at this time; the third power signal terminal VGL supplies the pull-down node PD and the second capacitor C2 Outputting the third power supply signal, the third power supply signal is the second potential, so as to discharge the pull-down node PD and the second capacitor C2, at this time, the sixth transistor M6 and the seventh transistor M7 are turned off, so that It is ensured that the output terminal OUTPUT outputs the first clock signal stably.
在上述步骤303中，该复位阶段T3中，该复位信号端RST输入的复位信号(即第n+1级移位寄存器单元的输出信号)为第一电位，该第二晶体管M2开启，该第二电源信号端VSS向该上拉节点PU输出该第二电源信号，该第二电源信号为第二电位，此时第三晶体管M3和第五晶体管M5关断。In the above step 303, in the reset phase T3, the reset signal input by the reset signal terminal RST (that is, the output signal of the n+1th stage shift register unit) is the first potential, the second transistor M2 is turned on, and the second transistor M2 is turned on. The second power signal terminal VSS outputs the second power signal to the pull-up node PU, the second power signal is at the second potential, and at this time the third transistor M3 and the fifth transistor M5 are turned off.
在上述步骤304中，该保持阶段T4中，该第一时钟信号为第一电位，第二时钟信号端CLKB输入的第二时钟信号为第二电位，该第四晶体管M4关断，因此不会对该下拉节点PD和第二电容器C2充电，该上拉节点PU保持第二电位，该第三晶体管M3关断，从而保证输出端OUTPUT的低压输出，保证了信号输出的稳定性。In the above step 304, in the holding phase T4, the first clock signal is at the first potential, the second clock signal input from the second clock signal terminal CLKB is at the second potential, and the fourth transistor M4 is turned off, so there will be no The pull-down node PD and the second capacitor C2 are charged, the pull-up node PU maintains the second potential, and the third transistor M3 is turned off, thereby ensuring the low-voltage output of the output terminal OUTPUT and ensuring the stability of signal output.
在上述步骤305中，该降噪阶段T5中，该第二时钟信号为第一电位，该第四晶体管M4开启，该第二时钟信号端CLKB向该下拉节点PD输出该第二时钟信号，此时该下拉节点PD的电位为第一电位，该第六晶体管M6和该第七晶体管M7开启，该第三电源信号端VGL分别向该上拉节点PU、该输出端OUTPUT输出该第三电源信号，由于该第三电源信号为第二电位，因此可以对该上拉节点PU点及输出端OUTPUT进行放噪，使得该输出端OUTPUT由第一时钟信号端CLK产生的耦合(英文：Coupling)噪声电压得以消除，从而保证输出端OUTPUT的低压输出，保证了信号输出的稳定性。In the above step 305, in the noise reduction stage T5, the second clock signal is at the first potential, the fourth transistor M4 is turned on, and the second clock signal terminal CLKB outputs the second clock signal to the pull-down node PD, thus When the potential of the pull-down node PD is the first potential, the sixth transistor M6 and the seventh transistor M7 are turned on, and the third power signal terminal VGL outputs the third power signal to the pull-up node PU and the output terminal OUTPUT respectively. , since the third power supply signal is at the second potential, it is possible to release noise on the pull-up node PU and the output terminal OUTPUT, so that the coupling (English: Coupling) noise generated by the first clock signal terminal CLK on the output terminal OUTPUT The voltage is eliminated, thereby ensuring the low-voltage output of the output terminal OUTPUT and ensuring the stability of the signal output.
需要说明的是，在下一帧扫描开始之前，该移位寄存器单元可以一直重复降噪阶段T5，在该降噪阶段T5中，该上拉节点PU一直保持第二电位，该下拉节点PD一直保持第一电位，因此该第六晶体管M6和第七晶体管M7一直保持开启状态，不断对上拉节点PU和输出端OUTPUT进行降噪。下一帧扫描开始后，当第n-1级移位寄存器单元输出的输出信号为第一电位时，该第n级移位寄存器单元即可再次执行该输入阶段T1。It should be noted that, before the start of the next frame scan, the shift register unit can always repeat the noise reduction stage T5. In the noise reduction stage T5, the pull-up node PU always maintains the second potential, and the pull-down node PD always maintains The first potential, therefore, the sixth transistor M6 and the seventh transistor M7 are always kept on to reduce the noise of the pull-up node PU and the output terminal OUTPUT. After the next frame scan starts, when the output signal output by the shift register unit of the n-1th stage is the first potential, the shift register unit of the nth stage can execute the input stage T1 again.
参考图2-2，在反向扫描时，该输入模块10可以包括：第二晶体管M2；该复位模块20可以包括：第一晶体管M1；该上拉模块30可以包括：第三晶体管M3和第一电容器C1；该下拉模块40可以包括：第四晶体管M4、第五晶体管M5和第二电容器C2；该降噪模块50可以包括：第六晶体管M6和第七晶体管M7，该方法可以包括：Referring to FIG. 2-2, during reverse scanning, the input module 10 may include: a second transistor M2; the reset module 20 may include: a first transistor M1; the pull-up module 30 may include: a third transistor M3 and a second transistor M2. A capacitor C1; the pull-down module 40 may include: a fourth transistor M4, a fifth transistor M5, and a second capacitor C2; the noise reduction module 50 may include: a sixth transistor M6 and a seventh transistor M7, and the method may include:
以第n级移位寄存器单元为例，在上述步骤301中，该输入阶段T1中，该第n级移位寄存器单元的输入信号端INPUT输入的该输入信号(即第n+1级移位寄存器单元的输出信号)为第一电位，该第二晶体管M2开启，该第一电源信号端VDD向该上拉节点PU输出该第一电源信号。Taking the nth stage shift register unit as an example, in the above-mentioned step 301, in the input stage T1, the input signal input by the input signal terminal INPUT of the nth stage shift register unit (that is, the n+1 stage shift The output signal of the register unit ) is the first potential, the second transistor M2 is turned on, and the first power signal terminal VDD outputs the first power signal to the pull-up node PU.
在上述步骤302中，该输出阶段T2中，该上拉节点PU保持第一电位，该第三晶体管M3和第五晶体管M5开启，该第一时钟信号端CLK向该输出端OUTPUT输出该第一时钟信号，该第三电源信号端VGL向该下拉节点PD输入该第三电源信号，该第六晶体管M6和该第七晶体管M7关断。In the above step 302, in the output phase T2, the pull-up node PU maintains the first potential, the third transistor M3 and the fifth transistor M5 are turned on, and the first clock signal terminal CLK outputs the first clock signal terminal CLK to the output terminal OUTPUT. clock signal, the third power signal terminal VGL inputs the third power signal to the pull-down node PD, and the sixth transistor M6 and the seventh transistor M7 are turned off.
在上述步骤303中，该复位阶段T3中，该复位信号端RST输入的复位信号(即第n-1级移位寄存器单元的输出信号)为第一电位，该第一晶体管M1开启，该第二电源信号端VSS向该上拉节点PU输出该第二电源信号。In the above step 303, in the reset phase T3, the reset signal input by the reset signal terminal RST (that is, the output signal of the n-1th stage shift register unit) is the first potential, the first transistor M1 is turned on, and the first transistor M1 is turned on. The second power signal terminal VSS outputs the second power signal to the pull-up node PU.
在上述步骤304中，该保持阶段T4中，该第一时钟信号为第一电位，第二时钟信号端CLKB输入的第二时钟信号为第二电位，该第四晶体管M4关断，该上拉节点PU保持第二电位，该第三晶体管M3关断；In the above step 304, in the holding phase T4, the first clock signal is at the first potential, the second clock signal input from the second clock signal terminal CLKB is at the second potential, the fourth transistor M4 is turned off, and the pull-up The node PU maintains the second potential, and the third transistor M3 is turned off;
在上述步骤305中，该降噪阶段T5中，该第二时钟信号为第一电位，第三电源信号端VGL输入的第三电源信号为第二电位，该第四晶体管M4开启，该第二时钟信号端CLKB向该下拉节点PD输出该第二时钟信号，该第六晶体管M6和该第七晶体管M7开启，该第三电源信号端VGL分别向该上拉节点PU、该输出端OUTPUT输出该第三电源信号。In the above step 305, in the noise reduction stage T5, the second clock signal is at the first potential, the third power signal input from the third power signal terminal VGL is at the second potential, the fourth transistor M4 is turned on, and the second The clock signal terminal CLKB outputs the second clock signal to the pull-down node PD, the sixth transistor M6 and the seventh transistor M7 are turned on, and the third power signal terminal VGL outputs the second clock signal to the pull-up node PU and the output terminal OUTPUT respectively. third power signal.
需要说明的是，在下一帧扫描开始之前，该第n级移位寄存器单元可以一直重复降噪阶段T5，在该降噪阶段T5中，该上拉节点PU一直保持第二电位，该下拉节点PD一直保持第一电位，因此该第六晶体管M6和第七晶体管M7一直保持开启状态，不断对上拉节点PU和输出端OUTPUT进行降噪。下一帧扫描开始后，当第n+1级移位寄存器单元输出的输出信号为第一电位时，该第n级移位寄存器单元即可开始执行该输入阶段T1。It should be noted that, before the start of the next frame scan, the shift register unit of the nth stage can always repeat the noise reduction stage T5, and in the noise reduction stage T5, the pull-up node PU always maintains the second potential, and the pull-down node The PD always maintains the first potential, so the sixth transistor M6 and the seventh transistor M7 are always turned on, and constantly reduce the noise of the pull-up node PU and the output terminal OUTPUT. After the next frame scan starts, when the output signal output by the n+1th shift register unit is the first potential, the nth shift register unit can start to execute the input phase T1.
上述反向扫描的具体驱动过程可以参考正向扫描的驱动流程，本发明实施例对此不再赘述。For the specific driving process of the above-mentioned reverse scanning, reference may be made to the driving process of the forward scanning, which will not be repeated in this embodiment of the present invention.
需要说明的是，在反向扫描时，该第一晶体管M1的第一极还可以继续与该第一电源信号端VSS相连，该第二晶体管M2的第一极可以继续与该第二电源信号端VDD相连，且该第三晶体管M3的第一极可以与该第二时钟信号端CLKB相连，该第四晶体管M4的第一极可以与该第一时钟信号端CLK相连，则在反向扫描的过程中，参考图3-2，该第一电源信号端VSS输入的第一电源信号可以为第二电位，该第二电源信号端VDD输入的第二电源信号为第一电位。也即是，在该移位寄存器在正向扫描和反向扫描之间切换时，可以不改变每个移位寄存器单元与各个电源信号端之间的连接关系，仅需调整每个电源信号端输入信号的电平高低，因此提高了该移位寄存器驱动时的灵活性。It should be noted that during reverse scanning, the first pole of the first transistor M1 can continue to be connected to the first power signal terminal VSS, and the first pole of the second transistor M2 can continue to be connected to the second power signal terminal VSS. The terminal VDD is connected, and the first pole of the third transistor M3 can be connected with the second clock signal terminal CLKB, and the first pole of the fourth transistor M4 can be connected with the first clock signal terminal CLK, then in reverse scanning During the process, referring to FIG. 3-2 , the first power signal input to the first power signal terminal VSS may be a second potential, and the second power signal input to the second power signal terminal VDD may be a first potential. That is to say, when the shift register is switched between forward scanning and reverse scanning, the connection relationship between each shift register unit and each power signal terminal may not be changed, and only each power signal terminal needs to be adjusted. The level of the input signal is high or low, thus improving the flexibility when the shift register is driven.
还需要说明的是，在上述实施例中，均是以第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管M7为N型晶体管，且第一电位为高电位，第二电位为低电位为例进行的说明。当然，该第一至第七晶体管还可以采用P型晶体管，当该第一至第十晶体管采用P型晶体管时，该第一电位为低电位，该第二电位为高电位，且该第一时钟信号端CLK和第二时钟信号端CLKB的电位变化可以与图3-2或图3-3所示的电位变化相反(即二者的相位差为180度)。It should also be noted that, in the above embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are used as An N-type transistor, where the first potential is a high potential and the second potential is a low potential, will be described as an example. Of course, the first to seventh transistors may also be P-type transistors. When the first to tenth transistors are P-type transistors, the first potential is a low potential, the second potential is a high potential, and the first The potential changes of the clock signal terminal CLK and the second clock signal terminal CLKB can be opposite to the potential changes shown in FIG. 3-2 or FIG. 3-3 (that is, the phase difference between the two is 180 degrees).
综上所述，本发明实施例提供了一种移位寄存器单元的驱动方法，该移位寄存器单元包括：输入模块、复位模块、上拉模块、下拉模块和降噪模块，该移位寄存器单元能够实现对显示装置中各行像素单元的双向扫描，并且该移位寄存器单元的中仅包括七个晶体管和两个电容器，电路结构和控制过程均较为简单，不仅降低了移位寄存器的功耗，而且降噪过程中可以通过降噪模块减小该移位寄存器单元中上拉节点和输出端的噪音，改善了移位寄存器单元的输出效果。In summary, the embodiment of the present invention provides a driving method for a shift register unit, the shift register unit includes: an input module, a reset module, a pull-up module, a pull-down module and a noise reduction module, the shift register unit It can realize bidirectional scanning of pixel units in each row in the display device, and the shift register unit only includes seven transistors and two capacitors, and the circuit structure and control process are relatively simple, which not only reduces the power consumption of the shift register, Moreover, the noise of the pull-up node and the output end of the shift register unit can be reduced by the noise reduction module during the noise reduction process, thereby improving the output effect of the shift register unit.
图4是本发明实施例提供的一种栅极驱动电路的结构示意图，如图4所示，该栅极驱动电路可以包括至少两个级联移位寄存器单元，其中每个移位寄存器单元可以为如图1、图2-1或图2-2所示的移位寄存器单元。从图4中可以看出，每一级移位寄存器单元的输入信号端INPUT输入的输入信号为上一级移位寄存器单元的输出端OUTPUT输出的输出信号；每一级移位寄存器单元的复位信号端RST输入的复位信号为下一级移位寄存器单元的输出端OUTPUT输出的输出信号。此外，当第n级移位寄存器单元的上拉模块所连接的时钟信号端为第一时钟信号端CLK时，第n-1级和第n级的移位寄存器单元的上拉模块所连接的时钟信号端可以为第二时钟信号端CLKB。因此，当移位寄存器需要从正向扫描切换至反向扫描时，可以通过改变每个移位寄存器单元中上拉模块所连接的时钟信号端，以及改变第一电源信号端和第二电源信号端的电平，实现该移位寄存器双向扫描的切换。Fig. 4 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present invention. As shown in Fig. 4, the gate drive circuit may include at least two cascaded shift register units, wherein each shift register unit may It is a shift register unit as shown in Fig. 1, Fig. 2-1 or Fig. 2-2. As can be seen from Figure 4, the input signal input by the input signal terminal INPUT of each stage of shift register unit is the output signal output by the output terminal OUTPUT of the previous stage of shift register unit; the reset of each stage of shift register unit The reset signal input by the signal terminal RST is the output signal output by the output terminal OUTPUT of the shift register unit of the next stage. In addition, when the clock signal terminal connected to the pull-up module of the shift register unit of the nth stage is the first clock signal terminal CLK, the pull-up modules connected to the shift register units of the n-1 and nth stages The clock signal end may be the second clock signal end CLKB. Therefore, when the shift register needs to switch from forward scanning to reverse scanning, it can be changed by changing the clock signal terminal connected to the pull-up module in each shift register unit, and changing the first power signal terminal and the second power signal The level of the terminal realizes the switching of the bidirectional scanning of the shift register.
另外，本发明实施例还提供一种显示装置，该显示装置可以包括如图4所示的栅极驱动电路，该栅极驱动电路可以包括至少两个级联的如图1、图2-1或图2-2所示的移位寄存器单元。该显示装置可以为：液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。In addition, an embodiment of the present invention also provides a display device. The display device may include a gate drive circuit as shown in FIG. 4, and the gate drive circuit may include at least two cascaded Or the shift register cell shown in Figure 2-2. The display device can be any product or component with a display function such as a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, or a navigator.
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610550989.2ACN106228927A (en) | 2016-07-13 | 2016-07-13 | Shift register cell, driving method, gate driver circuit and display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610550989.2ACN106228927A (en) | 2016-07-13 | 2016-07-13 | Shift register cell, driving method, gate driver circuit and display device |
| Publication Number | Publication Date |
|---|---|
| CN106228927Atrue CN106228927A (en) | 2016-12-14 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610550989.2APendingCN106228927A (en) | 2016-07-13 | 2016-07-13 | Shift register cell, driving method, gate driver circuit and display device |
| Country | Link |
|---|---|
| CN (1) | CN106228927A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106548747A (en)* | 2017-02-06 | 2017-03-29 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driver circuit and display device |
| CN106601181A (en)* | 2017-03-08 | 2017-04-26 | 京东方科技集团股份有限公司 | Shift register, gate drive circuit, display panel, and driving method |
| CN106710546A (en)* | 2016-12-27 | 2017-05-24 | 武汉华星光电技术有限公司 | Gate driving circuit and display device |
| CN106782282A (en)* | 2017-02-23 | 2017-05-31 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display panel and driving method |
| WO2017197917A1 (en)* | 2016-05-16 | 2017-11-23 | 京东方科技集团股份有限公司 | Shift register and operation method therefor |
| CN107610737A (en)* | 2017-10-26 | 2018-01-19 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN107945762A (en)* | 2018-01-03 | 2018-04-20 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| WO2018126691A1 (en)* | 2017-01-03 | 2018-07-12 | 京东方科技集团股份有限公司 | Shift register unit, driving method therefor, shift register and display device |
| CN108470535A (en)* | 2018-06-11 | 2018-08-31 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method and gate driving circuit, display device |
| CN108962148A (en)* | 2018-08-16 | 2018-12-07 | 北京华镁钛科技有限公司 | For the drive element of the grid of antenna or display panel, driving method and driving circuit |
| CN109785805A (en)* | 2017-11-14 | 2019-05-21 | 夏普株式会社 | Scan line drive circuit and the display device for having it |
| WO2019200967A1 (en)* | 2018-04-18 | 2019-10-24 | 京东方科技集团股份有限公司 | Shift register unit, drive method, gate drive circuit, and display device |
| CN110648638A (en)* | 2019-09-25 | 2020-01-03 | 合肥京东方卓印科技有限公司 | Gate drive circuits, pixel circuits, display panels and display devices |
| CN113990378A (en)* | 2021-10-29 | 2022-01-28 | 福州京东方光电科技有限公司 | Shift register and driving method thereof, gate drive circuit and display device |
| WO2024130672A1 (en)* | 2022-12-23 | 2024-06-27 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and display apparatus |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103226981A (en)* | 2013-04-10 | 2013-07-31 | 京东方科技集团股份有限公司 | Shift register unit and gate driving circuit |
| US20140086379A1 (en)* | 2011-11-25 | 2014-03-27 | Hefei Boe Optoelectronics Technology Co., Ltd. | Driving circuit, shifting register, gate driver, array substrate and display device |
| CN204102544U (en)* | 2014-11-07 | 2015-01-14 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit and display device |
| CN104485086A (en)* | 2015-01-04 | 2015-04-01 | 京东方科技集团股份有限公司 | Shifting register unit, drive method, grid drive circuit and display device |
| CN205050536U (en)* | 2015-10-23 | 2016-02-24 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
| CN105632451A (en)* | 2016-04-08 | 2016-06-01 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, gate drive circuit and display device |
| CN105632446A (en)* | 2016-03-30 | 2016-06-01 | 京东方科技集团股份有限公司 | GOA unit, driving method thereof, GOA circuit and display device |
| CN105679229A (en)* | 2016-04-20 | 2016-06-15 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid electrode driving circuit and display device |
| CN105702222A (en)* | 2016-04-18 | 2016-06-22 | 京东方科技集团股份有限公司 | Shift register unit, grid drive unit, display apparatus and driving method |
| CN105702196A (en)* | 2016-04-29 | 2016-06-22 | 京东方科技集团股份有限公司 | Gate driving circuit, driving method thereof, and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140086379A1 (en)* | 2011-11-25 | 2014-03-27 | Hefei Boe Optoelectronics Technology Co., Ltd. | Driving circuit, shifting register, gate driver, array substrate and display device |
| CN103226981A (en)* | 2013-04-10 | 2013-07-31 | 京东方科技集团股份有限公司 | Shift register unit and gate driving circuit |
| CN204102544U (en)* | 2014-11-07 | 2015-01-14 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit and display device |
| CN104485086A (en)* | 2015-01-04 | 2015-04-01 | 京东方科技集团股份有限公司 | Shifting register unit, drive method, grid drive circuit and display device |
| CN205050536U (en)* | 2015-10-23 | 2016-02-24 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
| CN105632446A (en)* | 2016-03-30 | 2016-06-01 | 京东方科技集团股份有限公司 | GOA unit, driving method thereof, GOA circuit and display device |
| CN105632451A (en)* | 2016-04-08 | 2016-06-01 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, gate drive circuit and display device |
| CN105702222A (en)* | 2016-04-18 | 2016-06-22 | 京东方科技集团股份有限公司 | Shift register unit, grid drive unit, display apparatus and driving method |
| CN105679229A (en)* | 2016-04-20 | 2016-06-15 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid electrode driving circuit and display device |
| CN105702196A (en)* | 2016-04-29 | 2016-06-22 | 京东方科技集团股份有限公司 | Gate driving circuit, driving method thereof, and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017197917A1 (en)* | 2016-05-16 | 2017-11-23 | 京东方科技集团股份有限公司 | Shift register and operation method therefor |
| CN106710546B (en)* | 2016-12-27 | 2019-05-07 | 武汉华星光电技术有限公司 | Gate driving circuit and display device |
| CN106710546A (en)* | 2016-12-27 | 2017-05-24 | 武汉华星光电技术有限公司 | Gate driving circuit and display device |
| US10204587B2 (en) | 2017-01-03 | 2019-02-12 | Boe Technology Group Co., Ltd. | Shift register unit and drive method thereof, shift register and display apparatus |
| WO2018126691A1 (en)* | 2017-01-03 | 2018-07-12 | 京东方科技集团股份有限公司 | Shift register unit, driving method therefor, shift register and display device |
| CN106548747A (en)* | 2017-02-06 | 2017-03-29 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driver circuit and display device |
| CN106782282A (en)* | 2017-02-23 | 2017-05-31 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display panel and driving method |
| WO2018161527A1 (en)* | 2017-03-08 | 2018-09-13 | 京东方科技集团股份有限公司 | Shift register, gate-driver circuit, display panel, and driving method |
| US10825371B2 (en) | 2017-03-08 | 2020-11-03 | Boe Technology Group Co., Ltd. | Shift register, gate driving circuit, display panel and driving method |
| CN106601181A (en)* | 2017-03-08 | 2017-04-26 | 京东方科技集团股份有限公司 | Shift register, gate drive circuit, display panel, and driving method |
| CN107610737A (en)* | 2017-10-26 | 2018-01-19 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN107610737B (en)* | 2017-10-26 | 2023-07-21 | 京东方科技集团股份有限公司 | Shift register unit, driving method thereof, gate driving circuit and display device |
| CN109785805A (en)* | 2017-11-14 | 2019-05-21 | 夏普株式会社 | Scan line drive circuit and the display device for having it |
| CN107945762A (en)* | 2018-01-03 | 2018-04-20 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| US10892028B2 (en) | 2018-01-03 | 2021-01-12 | Boe Technology Group Co., Ltd. | Shift register and method of driving the same, gate driving circuit and display device |
| WO2019200967A1 (en)* | 2018-04-18 | 2019-10-24 | 京东方科技集团股份有限公司 | Shift register unit, drive method, gate drive circuit, and display device |
| US11417256B2 (en) | 2018-04-18 | 2022-08-16 | Ordos Yuansheng Optoelectronics Co., Ltd. | Shift register unit and driving method thereof, gate drive circuit and display device |
| US11263943B2 (en) | 2018-06-11 | 2022-03-01 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register and driving method therefor, gate drive circuit, and display device |
| CN108470535A (en)* | 2018-06-11 | 2018-08-31 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method and gate driving circuit, display device |
| CN108962148A (en)* | 2018-08-16 | 2018-12-07 | 北京华镁钛科技有限公司 | For the drive element of the grid of antenna or display panel, driving method and driving circuit |
| CN110648638A (en)* | 2019-09-25 | 2020-01-03 | 合肥京东方卓印科技有限公司 | Gate drive circuits, pixel circuits, display panels and display devices |
| US11200861B2 (en) | 2019-09-25 | 2021-12-14 | Hefei Boe Joint Technology Co., Ltd. | Shift register unit, gate drive circuit, display panel and display device |
| CN113990378A (en)* | 2021-10-29 | 2022-01-28 | 福州京东方光电科技有限公司 | Shift register and driving method thereof, gate drive circuit and display device |
| CN113990378B (en)* | 2021-10-29 | 2022-09-09 | 福州京东方光电科技有限公司 | Shift register and driving method thereof, gate driving circuit, and display device |
| WO2024130672A1 (en)* | 2022-12-23 | 2024-06-27 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and display apparatus |
| Publication | Publication Date | Title |
|---|---|---|
| CN106228927A (en) | Shift register cell, driving method, gate driver circuit and display device | |
| CN106057147B (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN108281124B (en) | Shift register unit and driving method thereof, gate driving circuit and display device | |
| TWI433459B (en) | Bi-directional shift register | |
| CN105632446B (en) | GOA unit and driving method thereof, GOA circuit, display device | |
| CN104809979B (en) | A kind of phase inverter and driving method, GOA unit, GOA circuits and display device | |
| CN106157874B (en) | Shift register unit, driving method, gate driving circuit and display device | |
| CN105679229A (en) | Shifting register unit, driving method, grid electrode driving circuit and display device | |
| CN104867438B (en) | Shift register cell and its driving method, shift register and display device | |
| CN106409207A (en) | Shifting register unit, driving method, gate electrode driving circuit and display device | |
| CN106128364B (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN205595037U (en) | Shifting register, grid driving circuit and display device | |
| CN109243351B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| CN104992662B (en) | GOA unit and its driving method, GOA circuits, display device | |
| CN107039017A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN107093414B (en) | A shift register, its driving method, gate driving circuit and display device | |
| CN104835475A (en) | Shift register unit and driving method thereof, grid electrode drive circuit and display device | |
| CN108573668A (en) | Shift register unit, driving method thereof, gate driving circuit and display device | |
| CN108806628A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN107564458A (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN105654991B (en) | Shift register and its driving method, GOA circuit and display device | |
| CN104464600A (en) | Shifting register unit, driving method of shifting register unit, shifting register circuit and display device | |
| CN107958649A (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN107564459B (en) | Shift register unit, grid driving circuit, display device and driving method | |
| CN108182905A (en) | Switching circuit, control unit, display device, gate driving circuit and method |
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication | Application publication date:20161214 |