技术领域technical field
本发明涉及电力通讯行业领域，具体为一种基于FPGA的合并单元秒脉冲同步输出系统及方法。The invention relates to the field of electric power communication industry, in particular to an FPGA-based merging unit second pulse synchronous output system and method.
背景技术Background technique
用以对来自二次转换器的电流和/或电压数据进行时间相关组合的物理单元叫作合并单元。合并单元可以是互感器的一个组件，也可以是一个分立单元。行业中对于合并单元的技术规范中要求，合并单元采样频率为4kHz，且采样离散时间小于10微秒，再加上对采样数据的同步要求，使得同步守时成为合并单元的一项关键技术。现有技术中，合并单元在同步过程中会产生发送频率抖动的问题；即采样值离散时间超过10微秒，导致采样的准确性降低。The physical unit used to time-dependently combine the current and/or voltage data from the secondary converter is called a merging unit. The merging unit can be a component of the transformer or a discrete unit. The technical specifications for the merging unit in the industry require that the sampling frequency of the merging unit is 4 kHz, and the sampling discrete time is less than 10 microseconds. Coupled with the synchronization requirements for the sampling data, synchronization and punctuality have become a key technology of the merging unit. In the prior art, the merging unit may generate the problem of sending frequency jitter during the synchronization process; that is, the discrete time of the sampling value exceeds 10 microseconds, which reduces the sampling accuracy.
发明内容SUMMARY OF THE INVENTION
针对现有技术中存在的问题，本发明提供一种基于FPGA的合并单元秒脉冲同步输出系统及方法，简单方便，解析简单，基于FPGA实现，具有良好的扩展性和实时性。Aiming at the problems existing in the prior art, the present invention provides an FPGA-based merging unit second pulse synchronous output system and method, which is simple and convenient, simple in analysis, realized based on FPGA, and has good scalability and real-time performance.
本发明是通过以下技术方案来实现：The present invention is achieved through the following technical solutions:
一种合并单元秒脉冲同步输出方法，包括如下步骤，A method for synchronously outputting a second pulse of a merging unit, comprising the steps of:
步骤1，采用外接秒脉冲对合并单元的内部秒脉冲进行计数；根据合并单元数据输出频率，对其输出数据序号进行循环计数；两计数均在秒脉冲上升沿时刻清零；Step 1, using an external second pulse to count the internal second pulse of the merging unit; according to the data output frequency of the merging unit, cyclically count the output data serial number; both counts are cleared at the rising edge of the second pulse;
步骤2，标记接收到外接秒脉冲上升沿时刻的秒计数值和数据序号计数值，计算出内外时钟在周期输出数据之外的时间差，即为同步输出时要调整的时间差，并得到时间差值；Step 2: Mark the second count value and data serial number count value at the time of receiving the rising edge of the external second pulse, and calculate the time difference between the internal and external clocks outside the periodic output data, which is the time difference to be adjusted during synchronous output, and obtain the time difference value ;
步骤3，当接收到外接秒脉冲后内部秒脉冲的下一个周期开始进入预同步阶段；在预同步阶段中，内部秒脉冲第一个周期为调整阶段；将时间差值补偿到调整阶段时间内的前若干个脉冲中，每个脉冲补偿到的时间在±10毫秒内；在调整阶段结束之后，合并单元正常输出脉冲信号，当下一个外部秒脉冲上升沿到来时，内部秒脉冲同时输出，数据计数值清零，进入同步阶段，实现将同步输出时要调整的时间差在合并单元同步前调整入合并单元数据输出脉冲，且输出脉冲的误差不超过±10微秒，完成合并单元同步输出。Step 3: After receiving the external second pulse, the next cycle of the internal second pulse begins to enter the pre-synchronization phase; in the pre-synchronization phase, the first cycle of the internal second pulse is the adjustment phase; the time difference is compensated to the adjustment phase time. In the first several pulses, the compensation time of each pulse is within ±10 milliseconds; after the end of the adjustment phase, the merging unit outputs the pulse signal normally, and when the next rising edge of the external second pulse arrives, the internal second pulse is output at the same time, and the data The count value is cleared to zero, and the synchronization stage is entered. The time difference to be adjusted during synchronization output is adjusted into the data output pulse of the merging unit before the merging unit is synchronized, and the error of the output pulse does not exceed ±10 microseconds, and the synchronous output of the merging unit is completed.
优选的，步骤1中，外接秒脉冲能够采用程序主时钟或经转换为秒脉冲的B码或1588时钟作为外部时钟秒脉冲。Preferably, in step 1, the external second pulse can use the program master clock or the B code or 1588 clock converted into the second pulse as the external clock second pulse.
优选的，步骤1中，采用外部的程序主时钟作为外接秒脉冲的信号源，主时钟为50MHz，周期为20纳秒，其计数值范围在0～500000000，数据输出的频率为4kHz，其计数值范围在0～3999。Preferably, in step 1, an external program master clock is used as the signal source of the external second pulse, the master clock is 50MHz, the period is 20 nanoseconds, the count value ranges from 0 to 500000000, the frequency of data output is 4kHz, and the count value is 4kHz. The value ranges from 0 to 3999.
进一步，步骤2中，当检测到外接秒脉冲信号上升沿时，标记秒计数值为C1，数据序号计数值为C2，时间差计数值为(C1-12500*C2)。Further, in step 2, when the rising edge of the external second pulse signal is detected, the marked second count value is C1, the data serial number count value is C2, and the time difference count value is (C1-12500*C2).
进一步，步骤3中，合并单元数据输出的频率为4kHz，则周期为250微秒，对应主时钟计数为12500，在合并单元同步输出前，需调整输出脉冲数据序号计数值将时间差值(C1-12500*C2)补偿进去。Further, in step 3, the frequency of merging unit data output is 4kHz, the cycle is 250 microseconds, and the corresponding master clock count is 12500. Before the merging unit synchronously outputs, it is necessary to adjust the output pulse data serial number count value to the time difference value (C1 -12500*C2) to compensate.
进一步，步骤3中，需调整输出脉冲数据序号计数值的范围为12000～13000。Further, in step 3, the range of the count value of the serial number of the output pulse data needs to be adjusted to be 12000-13000.
一种基于FPGA的合并单元秒脉冲同步输出系统，包括均由FPGA实现的计数模块，差值计算模块和数据输出使能模块；An FPGA-based merging unit second pulse synchronous output system, comprising a counting module, a difference calculation module and a data output enabling module all implemented by the FPGA;
计数模块用于标记外接秒脉冲与合并单元内部秒脉冲；The counting module is used to mark the external second pulse and the internal second pulse of the merging unit;
差值计算模块用于计算合并单元内部秒脉冲与外接秒脉冲同步输出时需要调整的时间差；The difference calculation module is used to calculate the time difference that needs to be adjusted when the internal second pulse of the merging unit and the external second pulse are output synchronously;
数据输出使能模块用于生成数据输出使能信号。The data output enable module is used to generate the data output enable signal.
优选的，输出使能信号包括三种使能信号生成状态，分别为不同步状态、预同步状态和同步状态。Preferably, the output enable signal includes three enable signal generation states, which are an asynchronous state, a pre-synchronized state, and a synchronized state, respectively.
与现有技术相比，本发明具有以下有益的技术效果：Compared with the prior art, the present invention has the following beneficial technical effects:
本发明所述的方法通过采用外接秒脉冲对合并单元的同步输出进行同步，将超出误差范围的时间差分在误差范围内分摊到多个脉冲当中，满足其采样离散时间小于10微秒的要求，简单方便；避免了采用时标法同步输出，在解析时标的算法过于复杂的问题。The method of the invention uses an external second pulse to synchronize the synchronous output of the merging unit, and allocates the time difference that exceeds the error range to multiple pulses within the error range, so as to meet the requirement that the sampling discrete time is less than 10 microseconds, Simple and convenient; avoids the problem that the time-scale method is used for synchronous output and the algorithm for analyzing the time-scale is too complicated.
本发明所述的方法基于FPGA进行实现，具有良好的扩展性和实时性、结构简单、功耗低和开发周期短、成本低；通过模块化的设置易于调试查找问题，具有较强的可移植性。The method of the invention is implemented based on FPGA, and has good scalability and real-time performance, simple structure, low power consumption, short development cycle and low cost; it is easy to debug and find problems through the modular setting, and has strong portability. sex.
附图说明Description of drawings
图1为本发明实例中所述系统的原理模块示意图。FIG. 1 is a schematic diagram of the principle modules of the system described in the example of the present invention.
图2为本发明实例中内部秒脉冲与外接秒脉冲差值计数示意图。FIG. 2 is a schematic diagram of counting the difference between the internal second pulse and the external second pulse in the example of the present invention.
图3为本发明实例中输出脉冲同步示意图。FIG. 3 is a schematic diagram of output pulse synchronization in an example of the present invention.
具体实施方式Detailed ways
下面结合具体的实施例对本发明做进一步的详细说明，所述是对本发明的解释而不是限定。The present invention will be further described in detail below in conjunction with specific embodiments, which are to explain rather than limit the present invention.
本发明一种基于FPGA的合并单元秒脉冲同步输出系统，如图1所示，其包括计数模块，差值计算模块和数据输出使能模块；计数模块用于标记外接秒脉冲与合并单元内部秒脉冲；差值计算模块用于计算合并单元内部秒脉冲与外接秒脉冲同步输出时需要调整的时间差；数据输出使能模块用于生成数据输出使能信号，包含三种使能信号生成状态：不同步状态(没有外接同步信号)、预同步状态(同步前调整)和同步状态。该方法有别于现有技术中采用的时标法同步输出，算法简单；其基于FPGA实现，具有良好的扩展性和实时性、结构简单、功耗低和开发周期短、成本低的优点。其详细步骤如下：An FPGA-based merging unit second pulse synchronous output system of the present invention, as shown in Figure 1, includes a counting module, a difference calculation module and a data output enabling module; the counting module is used to mark the external second pulse and the internal second pulse of the merging unit. Pulse; the difference calculation module is used to calculate the time difference that needs to be adjusted when the internal second pulse of the merging unit and the external second pulse are output synchronously; the data output enable module is used to generate the data output enable signal, including three enable signal generation states: no Sync state (no external sync signal), pre-sync state (adjust before sync) and sync state. The method is different from the time-scale method used in the prior art to synchronize output, and the algorithm is simple; it is implemented based on FPGA, and has the advantages of good scalability and real-time performance, simple structure, low power consumption, short development cycle and low cost. The detailed steps are as follows:
(1)采用外接秒脉冲对合并单元的内部秒脉冲进行计数；根据合并单元输出频率，对其输出数据序号进行循环计数；两计数均在秒脉冲上升沿时刻清零。外接秒脉冲能够采用多种信号源，例如B码和1588时钟，通过转换为秒脉冲的步骤作为外部时钟秒脉冲；本优选实例中外接秒脉冲的信号源采用外部的程序主时钟，主时钟为50MHz，周期为20纳秒，其计数值范围在0～500000000，数据输出的频率为4kHz，其计数值范围在0～3999；(1) The external second pulse is used to count the internal second pulse of the merging unit; according to the output frequency of the merging unit, the output data serial number is counted cyclically; both counts are cleared at the rising edge of the second pulse. The external second pulse can use a variety of signal sources, such as B code and 1588 clock, through the steps of converting to the second pulse as the external clock second pulse; in this preferred example, the external second pulse signal source uses the external program master clock, and the master clock is 50MHz, the period is 20 nanoseconds, the count value range is 0～500000000, the frequency of data output is 4kHz, and the count value range is 0～3999;
(2)如图2所示，标记接收到外部时钟秒脉冲上升沿时刻秒计数值和数据序号计数值，计算出内外时钟在周期输出数据之外的时间差，即为同步输出时要调整的时间差。当检测到外接秒脉冲信号上升沿时，标记秒计数值为C1，数据序号计数值为C2，时间差计数值为(C1-12500*C2)；(2) As shown in Figure 2, the marker receives the second count value and data serial number count value at the time when the external clock second pulse rises . When the rising edge of the external second pulse signal is detected, the marked second count value is C1, the data serial number count value is C2, and the time difference count value is (C1-12500*C2);
(3)将同步输出时要调整的时间差在合并单元同步前调整入合并单元数据输出脉冲，确保输出脉冲的误差不超过±10微秒，以此达到合并单元同步输出的目的。数据输出的频率为4kHz，则周期为250微秒，对应主时钟计数为12500，在合并单元同步输出前，需适当调整输出数据序号计数值(调整范围12000～13000)将时间差值(C1-12500*C2)补偿进去。具体的，如图3所示，当接收到外接秒脉冲时，从内部秒脉冲的下一个周期开始进入预同步阶段；在预同步阶段中，内部秒脉冲第一个周期内为调整阶段的，在调整阶段的时间里，有四千个数据输出脉冲，选择前若干个脉冲，将时间差值(C1-12500*C2)补偿进去，每个补偿的时间都在±10毫秒内，在调整阶段结束之后，合并单元正常输出脉冲信号，当下一个外部秒脉冲上升沿到来时，内部同时输出，数据计数清零，进入同步阶段，实现合并单元同步输出。(3) Adjust the time difference to be adjusted during synchronous output into the data output pulse of the merging unit before the merging unit is synchronized to ensure that the error of the output pulse does not exceed ±10 microseconds, so as to achieve the purpose of synchronous output of the merging unit. The frequency of data output is 4kHz, the period is 250 microseconds, and the corresponding master clock count is 12500. Before the merging unit outputs synchronously, it is necessary to adjust the output data serial number count value (adjustment range 12000～13000) to the time difference value (C1- 12500*C2) to compensate. Specifically, as shown in Figure 3, when an external second pulse is received, the pre-synchronization phase starts from the next cycle of the internal second pulse; in the pre-synchronization phase, the first cycle of the internal second pulse is the adjustment phase, During the adjustment stage, there are 4,000 data output pulses, select the first several pulses, and compensate the time difference (C1-12500*C2), each compensation time is within ±10ms, in the adjustment stage After the end, the merging unit outputs the pulse signal normally. When the rising edge of the next external second pulse arrives, the internal output is simultaneously output, the data count is cleared, and the synchronization stage is entered to realize the synchronous output of the merging unit.
本发明算法简单，其基于FPGA实现，具有良好的扩展性和实时性、结构简单、功耗低和开发周期短、成本低的优点。本发明模块化，易于调试查找问题，具有较强的可移植性。The algorithm of the invention is simple, it is realized based on FPGA, and has the advantages of good expansibility and real-time performance, simple structure, low power consumption, short development period and low cost. The invention is modular, easy to debug and find problems, and has strong portability.
以上显示和描述了本发明的基本原理和主要特征和本发明的优点。本行业的技术人员应该了解，本发明不受上述实施例的限制，上述实施例和说明书中描述的只是说明本发明的原理，在不脱离本发明精神和范围的前提下，本发明还会有各种变化和改进，这些变化和改进都落入要求保护的本发明范围内。本发明要求保护范围由所附的权利要求书及其等效物界定。The basic principles and main features of the present invention and the advantages of the present invention have been shown and described above. Those skilled in the art should understand that the present invention is not limited by the above-mentioned embodiments. The above-mentioned embodiments and descriptions only illustrate the principle of the present invention. Without departing from the spirit and scope of the present invention, the present invention will also have Various changes and modifications fall within the scope of the claimed invention. The claimed scope of the present invention is defined by the appended claims and their equivalents.
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| CN201610505592.1ACN106209090B (en) | 2016-06-30 | 2016-06-30 | An FPGA-based merging unit second pulse synchronous output system and method |
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