Bit width conversion device	100
		Bit width conversion sends sub-device	110
Pseudo-random sequence generator	111
		Selector	112
First stacking control unit	113
		First asynchronous input into/output from cache	114
First pops control unit	115
		First obstructive root canal subelement	1151
First counter	116
		Send control unit	117
First data select subelement	1171
		First remaining bits register	1172
Bit width conversion receives sub-device	120
		Pseudo-random sequence checker	121
Second pops control unit	122
		Second obstructive root canal subelement	1221
Second asynchronous input into/output from cache	123
		Second stacking control unit	124
Second counter	125
		Reception control unit	126
Second data select subelement	1261
		Second remaining bits register	1262

Embodiment

Below in conjunction with accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, completeGround is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Generally existThe component of the embodiment of the present invention described and illustrated in accompanying drawing can be arranged and designed with a variety of configurations herein.CauseThis, the detailed description of the embodiments of the invention to providing in the accompanying drawings is not intended to limit claimed invention below, but it is merely representative of the selected embodiment of the present invention.Based on embodiments of the invention, those skilled in the art are not makingThe every other embodiment obtained on the premise of creative work, belongs to the scope of protection of the invention.

Fig. 1 is refer to, is the electrical block diagram of bit width conversion device 100 provided in an embodiment of the present invention, institute's rhemeWide conversion equipment 100 is connected between the first module and the second module, the data bit width of first module and second mouldThe data bit width of block is differed, and the bit width conversion device 100 can be realized between first module and second moduleThe conversion of bit wide data.

In the present embodiment, the bit width conversion device 100 includes bit width conversion transmission sub-device 110 and bit width conversion connectsReceive sub-device 120.Wherein, it is described second that the bit width conversion, which sends sub-device 110 by the bit width conversion of first module,The bit wide of module.It is first module that the bit width conversion, which receives sub-device 120 by the bit width conversion of second module,Bit wide.

The bit width conversion sends pseudo-random sequence generator 111, the choosing that sub-device 110 includes being electrically connected with each otherSelect device 112, the first stacking control unit 113, the first asynchronous input into/output from cache 114, first pop control unit 115, firstCounter 116 and transmission control unit 117.

The data output end of the output end of the pseudo-random sequence generator 111 and first module respectively with the choosingSelect the input connection of device 112, the control end input select signal of the selector 112.When the selection signal is 1, instituteState selector 112 and export inspection during pseudo-random binary sequence is carried out to bit width conversion reception sub-device 120；In the choosingSelect signal for 0 when, the selector 112 exports the input data of first module.

The output end of the selector 112 is connected with the stacking data terminal of the described first asynchronous input into/output from cache 114, instituteThe stacking signal control end that the first stacking control unit 123 is stated with the described first asynchronous input into/output from cache 114 is connected.DescribedThe data terminal of popping of one asynchronous input into/output from cache 114 is connected with the transmission control unit 117.It is described pop control unit withThe signal control end connection of popping of the first asynchronous input into/output from cache 114.First counter 116 goes out described in being connected toBetween stack control unit and the transmission control unit 117.The first asynchronous input into/output from cache 114 write clock frequency withThe clock frequency of first module is identical, the reading clock frequency and described second of the first asynchronous input into/output from cache 114The clock frequency of module is identical.

The bit width conversion receives the pseudo-random sequence checker 121 that sub-device 120 includes being electrically connected with each other, theTwo pop control unit 122, the second counter 125, reception control unit 126, the second stacking control units 124 and second are asynchronousInput into/output from cache 123.

The input of the reception control unit 126 is connected with the data output end of second module, described to receive controlThe output end of unit 126 processed is connected with the stacking data terminal of the described second asynchronous input into/output from cache 123.The second stacking controlUnit 124 processed is connected with the stacking signal control end of the described second asynchronous input into/output from cache 123.The second counter connectionBetween the second stacking control unit 124 and the reception control unit 126.Described second pop control unit 122 withThe signal control end connection of popping of the second asynchronous input into/output from cache 123.

Pop data output end and the data input pin of first module of the second asynchronous input into/output from cache 123Connection, the data output end of popping of the second asynchronous input into/output from cache 123 also connects with the pseudo-random sequence checker 121Connect, the output of the data output end of popping of the asynchronous input into/output from cache 123 of 121 pairs of the pseudo-random sequence checker described secondData verified.The reading clock frequency of the second asynchronous input into/output from cache 123 and the clock of first module are frequentlyRate is identical, the first asynchronous input into/output from cache 114 to write clock frequency identical with the clock frequency of second module.

Further, in the present embodiment, the transmission control unit 117 includes：First remaining bits register 1172,The first remaining bits register 1172 is used to deposit remaining bit data during bit width conversion.

Further, in the present embodiment, described first control unit 115 is popped including the first obstructive root canal subelement1151, the first obstructive root canal subelement 1151 is used for the behaviour that pops for preventing data in the first asynchronous input into/output from cache 114Make.Described second pops control unit 122 including the second obstructive root canal subelement, and the second obstructive root canal subelement is used to hinderOnly in the second asynchronous input into/output from cache 123 data Pop operations.

Specifically, below using the data bit width of the first module as 66 bits, the bit wide of second module is that 32 bits areThe operation principle of the example wide conversion equipment 100 of place of matchmakers's rheme.In the case, first described in the bit width conversion device 100Asynchronous input into/output from cache 114 writes clock frequency 156.25MHz, the reading clock of the first asynchronous input into/output from cache 114Frequency 322.265625MHz；The second asynchronous input into/output from cache 123 writes clock frequency 322.265625MHz, describedThe reading clock frequency 156.25MHz of one asynchronous input into/output from cache 114.

Concrete operating principle is as follows

Bit width conversion sends the end of sub-device 110：The data bit width that bit width conversion sends the input of sub-device 110 is 66 bits,Clock frequency is 156.25MHz (clock66b)；The data bit width that bit width conversion sends the output of sub-device 110 is 32 bits,Clock frequency is 322.265625MHz (clock32b).Wherein, the bandwidth of the data of input and the data of output is10.3125Gbps。

The puppet that 66 bit datas (dataIn) and pseudo-random sequence generator 111 of described 112 pairs of inputs of selector are producedRandom binary sequence (Pseudo-Random Binary Sequence, abbreviation PRBS) is selected.Selection signal istestEn.If testEn is 1, PRBS data flows are sent, 66 bit datas are otherwise sent.Wherein pseudo-random sequence generator111 use PRBS31 algorithms, and as shown in Equation 1, the fundamental diagram of pseudo-random sequence generator 111 is as shown in Figure 2 for its multinomial.When testEn is 1, PRBS Sequence is sent, receiving the end of sub-device 120 to bit width conversion tests.

1+x²⁸+x³¹

X is the data of input, x in formula²⁸Represent the 28th of data, x³¹The 31st of data is represented ,+represent XOROperation.

66 bit datas are write cross clock domain operation is carried out in the first asynchronous input into/output from cache 114, eachClock66b clocks push on once in the described first asynchronous input into/output from cache 114.When system brings into operation, to firstThe input of asynchronous input into/output from cache 114 carries out holding operation, after 16 clock32b clock cycle are waited, and now firstThe data of 8 depth are just had in asynchronous input into/output from cache 114, start the first counter 116, the first counter 116 starts 0To 32 cycle count.Pop operations are carried out simultaneously, and the logic for control unit of popping is the first counter 116 when being odd number, justCarry out a Pop operations.The data of 66 bits are inputted, it is necessary to 2 in the described first asynchronous input into/output from cache 114 every timeThe clock32b clock cycle could send the data of 64 bits, while can also the first remaining bits of remaining 2 bit data depositIn register 1172.The transmission control unit 117 can also include：First data select subelement 1171, by 32The clock32b clock cycle, now the data in the first remaining bits register 1172 reach 32 bits, the first data choosingSubelement 1171 is selected to send out 32 bit datas of the first remaining bits register 1172 in the 33rd clock32b clock cycleGo out, just complete 1 data conversion for taking turns 66 bits to 32 bits.

Popped end in the data of the first asynchronous input into/output from cache 114, the first obstructive root canal (Hold Control) is singleThe function of member 1151 is the Pop operations that the first asynchronous input into/output from cache 114 is prevented when system brings into operation, and allows theOne asynchronous input into/output from cache 114 accumulates a certain amount of data, to prevent that the first asynchronous input into/output from cache 114 from occurring to underflowGo out (Underrun).

In the present embodiment, first counter 116, control signal of popping (pop), data of popping (pop data), theThe relation of 32 bit datas of one remaining bits register 1172 and output is as shown in table 1 below.

Table 1

Bit width conversion receives the end of sub-device 120：

The data bit width of input is 32 bits, and clock frequency is 322.265625MHz (clock32b)；The data bit of outputA width of 66 bit, clock frequency is 156.25MHz (clock66b).

At the stacking data segment end of the second asynchronous input into/output from cache 123, start the second counter 125, second meterThe cycle count that number device 125 is 0 to 32.For 32 bit datas of input, after 66 bit datas are combined into, it could carry out onceThe Pop operations of second asynchronous input into/output from cache 123.After first three 32 bit datas input, 66 bit datas are combined into, are enteredPop operations of row, three 32 bit datas now inputted there remains the data of 30 bits.The deposit is received into control singleThe second remaining bits register 1262 under member 126.It is single that the reception control unit 126 can also include the second data selectionMember 1261, hereafter each two clock32b clock cycle is just by the data progress in the described second asynchronous input into/output from cache 123Once pop.Until the second data select subelement 1261 by the second remaining bits register under reception control unit 126Remaining data are distributed in 1262.The logic of the signal for control unit of popping is that the second counter 125 is even number and is not 0When, carry out a Pop operations.By 33 clock32b clock cycle, the bit of a wheel 32 can be completed to the data of 66 bitsConversion.When system brings into operation, maintenance operation is carried out to the data terminal of popping of the second asynchronous input into/output from cache 123,After 8 clock66b clock cycle are waited, now there are the data of 8 depth in the second asynchronous input into/output from cache 123, carry outPop operations.The logic of the signal for control unit of popping once is popped for each clock66b clock cycle, and will be poppedObtained data output.When it is 1 to examine signal testEn, 121 pairs of the pseudo-random sequence checker is popped obtained dataPRBS inspections are carried out, if it is checked that wrong, then reporting interruption signal, shows that data conversion malfunctions.

Second counter 125, the control signal that pushes on (push signals), input data, the second remaining bits register 1262And the relation of the data that push on (push data) is as shown in table 2：

Table 2

From Table 2, it can be seen that by 33 clock32b clock cycle, the bit of a wheel 32 can be completed to 66 bitsData conversion.

Popped end in the data of the second asynchronous input into/output from cache 123, the second obstructive root canal (Hold Control) is singleThe function of member 1221 is the Pop operations that the second asynchronous input into/output from cache 123 is prevented when system brings into operation, and allows theTwo asynchronous input into/output from cache 123 accumulate a certain amount of data, to prevent that the second asynchronous input into/output from cache 123 from occurring to underflowGo out (Underrun).After the second asynchronous input into/output from cache 123 is accumulated to a certain amount of data, in each clock66b clocksRising edge, carry out a Pop operations, and obtained 66 bit datas of popping are exported.Carried out simultaneously according to the data that push onPRBS checks that the principle of PRBS31 detectors is as shown in Figure 3.If PRBS checks error, module can export an interruptSignal, shows occur mistake in data conversion.

In summary, bit width conversion device 100 provided in an embodiment of the present invention can not only realize different bit wide modules itBetween bit width conversion, the data that can also be changed by 121 pairs of the pseudo-random sequence checker bit width conversion devices 100 carry outVerification, above-mentioned bit width conversion device 100 can find the mistake in bit width conversion design in time, and be sent when there is mistakeBreak signal, emulation, test to chip bring great convenience, and improve the reliability of system.

The foregoing is only a specific embodiment of the invention, but the protection of the present invention is not limited thereto, any to be familiar withThose skilled in the art the invention discloses technology in, change or replacement can be readily occurred in, should all be covered in this hairWithin bright protection.Therefore, protection of the invention described should be defined by the protection of claim.