技术领域technical field
本发明属于信息安全领域，涉及的是一种集成电路芯片自毁的方法和结构。The invention belongs to the field of information security, and relates to a method and structure for self-destruction of an integrated circuit chip.
背景技术Background technique
微电子技术的不断发展使丰富、海量的信息可以固化到一块微小的芯片当中，而信息的价值往往远大于一块芯片的价值。电子产品的小型化、便携性也往往使它们更容易丢失。个人的手机、U盘等设备往往存储有隐私信息，一旦丢失可能会对自己的生活造成影响；企业里一块拥有核心技术的芯片一旦落入竞争者手中，竞争者通过反向很容易就可以窃取到相关芯片的核心技术，可能会让企业落入困境；政府、企业等部门的涉密信息一般都存储于硬盘、FLASH存储器中，一旦遗失将会造成不可估量的损失；战场上，我方的电子设备落入敌方手中很可能会造成作战方案的相关信息泄露，造成无法弥补的危害。为了避免芯片中的相关机密信息落入他人手中，需要在芯片中引入自毁技术。With the continuous development of microelectronics technology, rich and massive information can be consolidated into a tiny chip, and the value of information is often far greater than the value of a chip. The miniaturization and portability of electronic products also tend to make them easier to lose. Personal mobile phones, USB flash drives and other devices often store private information, and once lost, it may affect your life; once a chip with core technology in an enterprise falls into the hands of a competitor, the competitor can easily steal it by reverse The core technology of related chips may put the enterprise in trouble; the confidential information of the government, enterprises and other departments is generally stored in the hard disk and FLASH memory, once lost, it will cause immeasurable losses; on the battlefield, our Electronic equipment falling into the hands of the enemy is likely to cause the leakage of information related to the combat plan, causing irreparable harm. In order to prevent the relevant confidential information in the chip from falling into the hands of others, it is necessary to introduce self-destruct technology into the chip.
为了让芯片彻底销毁以杜绝后患，目前的自毁方法有化学腐蚀、含能剂引发爆炸使芯片碎片化等。化学腐蚀法需要特定的容器存储化学试剂，这会增大自毁装置的体积，也增加了制造该装置的难度，另一方面这些化学试剂并不能保证长时间内化学性的稳定，而且化学试剂一旦泄露可能会对人体造成危害。含能剂一般采用的是铝热剂、多孔硅(和氧化剂混合)等。制备铝热剂需要将纳米氧化剂和纳米铝粉长时间搅拌，使他们充分混合。同时，为了降低触发温度，一般还需要在铝热剂中加入固态汽油、硫粉等易燃易爆物。之后将铝热剂滴定旋涂到芯片的指定区域上。用多孔硅作含能剂同样存在诸多问题，为了得到适当的触发温度，需要制备孔径大小、孔隙率满足要求的多孔硅。另外将氧化剂渗入到多孔硅中，需要历经多次滴定氧化剂、风干，再滴定、风干这样的步骤。在制造工艺上比较耗费人力，效率也很低。另外，上述铝热剂、氧化剂均属于易燃易爆物，在高温时会引发爆炸，而氧化剂如NaClO4、CdClO4受到猛烈撞击时也有可能爆炸。In order to completely destroy the chip to prevent future troubles, the current self-destruction methods include chemical corrosion, an explosion caused by an energetic agent to fragment the chip, and so on. The chemical corrosion method requires specific containers to store chemical reagents, which will increase the volume of the self-destruct device and increase the difficulty of manufacturing the device. On the other hand, these chemical reagents cannot guarantee chemical stability for a long time, and the chemical reagents Once leaked, it may cause harm to human body. The energetic agent generally adopts thermite, porous silicon (mixed with oxidant) and the like. The preparation of thermite needs to stir the nano-oxidizer and nano-aluminum powder for a long time to make them fully mixed. At the same time, in order to reduce the trigger temperature, it is generally necessary to add solid gasoline, sulfur powder and other flammable and explosive materials to the thermite. Thermite was then titrated and spin-coated onto designated areas of the chip. There are also many problems in using porous silicon as an energetic agent. In order to obtain an appropriate trigger temperature, it is necessary to prepare porous silicon with pore size and porosity that meet the requirements. In addition, to infiltrate the oxidizing agent into the porous silicon, it needs to go through the steps of titrating the oxidizing agent, air-drying, re-titrating, and air-drying. It is manpower-intensive and inefficient in the manufacturing process. In addition, the above-mentioned thermites and oxidants are all flammable and explosive substances, which will cause explosion at high temperature, and oxidants such as NaClO4 and CdClO4 may also explode when they are violently impacted.
芯片自毁的前提是自毁装置不影响芯片的正常工作，不影响芯片的制造工艺，在没有接收到自毁信号时绝对不会自毁更不会对人身存在安全隐患。而上述提到的自毁方法难以避免地存在安全隐患，在制造上和传统硅工艺也存在较大偏差。另外非常容易受外界环境变化的影响，例如温度、湿度的变化容易造成化学试剂和含能剂化学性质的改变，在芯片跌落或有很高的加速度等情况下也可能会引发含能剂自爆。因此需要一种与硅工艺兼容，不影响芯片正常工作，受外界环境影响较小的芯片自毁方法。The premise of self-destruction of the chip is that the self-destruction device does not affect the normal operation of the chip, does not affect the manufacturing process of the chip, and will never self-destruct when no self-destruction signal is received, nor will it pose a safety hazard to the person. However, the self-destruct method mentioned above inevitably has potential safety hazards, and there is also a large deviation from the traditional silicon process in manufacturing. In addition, it is very susceptible to changes in the external environment. For example, changes in temperature and humidity can easily cause changes in the chemical properties of chemical reagents and energetic agents. When the chip falls or there is a high acceleration, it may also cause the self-explosion of the energetic agent. Therefore, there is a need for a chip self-destruction method that is compatible with the silicon process, does not affect the normal operation of the chip, and is less affected by the external environment.
体硅的理论临界断裂应力约为4-7GPa，但Si在低于700℃是一种脆性材料，其泊松比为v＝0.27，在4％应变下即有断裂危险。而且，材料中通常存在各种缺陷或者微裂纹，这会使体硅的断裂条件大大降低，微小的弯曲(200-700MPa)即能导致硅片断裂。因为单晶硅的{111}面面间距最大，原子键密度最小，为其解理面，体硅顺着解理面其裂纹的扩展要比顺着其它面容易得多。针对单晶硅的上述特点，可以在芯片上人为引入应力集中区域，合理利用解理面，在减小硅片断裂难度的同时使芯片的碎裂区域可控。The theoretical critical fracture stress of bulk silicon is about 4-7GPa, but Si is a brittle material below 700°C, its Poisson's ratio is v=0.27, and there is a risk of fracture at 4% strain. Moreover, there are usually various defects or microcracks in the material, which will greatly reduce the fracture conditions of the bulk silicon, and a small bending (200-700MPa) can cause the silicon wafer to break. Because the {111} plane of single crystal silicon has the largest spacing and the smallest atomic bond density, it is the cleavage plane, and the crack propagation of bulk silicon along the cleavage plane is much easier than along other planes. In view of the above-mentioned characteristics of monocrystalline silicon, stress concentration areas can be artificially introduced on the chip, and the cleavage plane can be reasonably used to reduce the difficulty of breaking the silicon chip while making the chip fragmentation area controllable.
发明内容Contents of the invention
本发明针对背景技术中芯片销毁技术中存在的制造困难，可靠性、安全性低等问题，利用硅片呈脆性、易断裂的特点，提出了在硅片上刻蚀深槽，在槽内填充特定金属或者先填充金属后填充热膨胀剂，利用硅的热膨胀系数显著小于该特定金属和热膨胀剂的这一特点，使金属通电迅速产生焦耳热的同时金属和膨胀剂立即热膨胀，而硅片的热膨胀可以忽略不计，因而向硅片中引入了较大的应力和位移，使硅片断裂。另外针对单晶硅顺着解理面更容易断裂的特点，在解理面方向引入应力集中区域，可以降低硅片断裂的难度。Aiming at the problems of manufacturing difficulties, low reliability and low security in chip destruction technology in the background technology, the present invention utilizes the characteristics of brittleness and easy fracture of silicon chips, and proposes to etch deep grooves on silicon chips and fill the grooves with A specific metal or a thermal expansion agent is filled after the metal is filled first, and the thermal expansion coefficient of silicon is significantly smaller than that of the specific metal and thermal expansion agent. When the metal is electrified, Joule heat is generated rapidly, and the metal and the expansion agent thermally expand immediately, while the thermal expansion of the silicon chip It can be ignored, thus introducing a large stress and displacement into the silicon wafer, causing the silicon wafer to break. In addition, considering the fact that single crystal silicon is more likely to break along the cleavage plane, the stress concentration area is introduced in the direction of the cleavage plane, which can reduce the difficulty of breaking the silicon wafer.
本发明的技术方案为一种用于集成电路芯片自毁结构，该结构包括：芯片、设置于芯片背面或正面迂回的通槽、设置在通槽中的金属、通槽首尾两端的金属上设置有电极，所述通槽遍布芯片正面或背面整个非工作区域，所述通槽总的金属杨氏模量大于70GPa，热膨胀系数是硅的5倍以上，其特征在于通槽两侧周期性设置有向外凸起的V型尖角；通槽迂回过程中相邻两段槽向外凸起的V型尖角，角尖相对且不重合。The technical solution of the present invention is a self-destruct structure for an integrated circuit chip, which comprises: a chip, a circuitous through groove arranged on the back or front of the chip, metal arranged in the through groove, and metals arranged on the first and last ends of the through groove. There are electrodes, the through-slots spread over the entire non-working area on the front or back of the chip, the total metal Young’s modulus of the through-slots is greater than 70GPa, and the thermal expansion coefficient is more than 5 times that of silicon, which is characterized in that the two sides of the through-slots are periodically arranged There are V-shaped sharp corners that protrude outward; during the circuitous process of the through groove, the V-shaped sharp corners of two adjacent grooves protrude outward, and the corners are opposite and do not overlap.
进一步的，所述通槽迂回过程中相邻两段槽向外凸起的V型尖角之间设置有窄深槽，该窄深槽的侧壁与芯片的解理面平行。Further, a narrow deep groove is provided between the outwardly protruding V-shaped sharp corners of two adjacent grooves during the circuitous process of the through groove, and the side walls of the narrow deep groove are parallel to the cleavage plane of the chip.
进一步的，所述迂回的通槽底部首先设置热膨胀剂，再填入金属。Further, the bottom of the meandering groove is first provided with a thermal expansion agent, and then filled with metal.
进一步的，所述V型尖角夹角为90°～120°，通槽迂回过程中相邻两段槽向外凸起的V型尖角距离小于等于25μm。Further, the included angle of the V-shaped sharp angle is 90°-120°, and the distance between the outwardly protruding V-shaped sharp angles of two adjacent grooves during the roundabout process of the through groove is less than or equal to 25 μm.
进一步的，所述用于集成电路芯片自毁结构在自毁过程中两端金属电极加载脉冲式电压。Further, the metal electrodes at both ends of the self-destructing structure for the integrated circuit chip are loaded with a pulsed voltage during the self-destructing process.
本发明的有益效果为：The beneficial effects of the present invention are:
1、本发明可以在短时间内使填充金属升温至200至300摄氏度，在该温度区间内，金属仍然具有较高的杨氏模量，而且体积膨胀量也较大，使硅片产生了较大的弯曲量，向硅片中引入了可观的应力。1. The present invention can raise the temperature of the filling metal to 200 to 300 degrees centigrade in a short period of time. In this temperature range, the metal still has a relatively high Young's modulus, and the volume expansion is also relatively large, so that the silicon wafer produces relatively high temperature. A large amount of bending introduces considerable stress into the silicon wafer.
2、同样是使芯片物理性断裂，本发明与含能芯片相比，结构和工艺要简单，安全性、稳定性更高。2. The chip is also physically broken. Compared with the energetic chip, the present invention has a simpler structure and process, and higher safety and stability.
3、芯片中尖角处会产生应力集中，而且尖角的形状对应力集中效应会产生明显的影响。3. Stress concentration will occur at the sharp corner of the chip, and the shape of the sharp corner will have a significant impact on the stress concentration effect.
4、尖角对尖角的结构可以使应力在应力集中的基础上进一步叠加，使该处率先产生裂纹，有利于芯片断裂。4. The structure of sharp corners to sharp corners can further superimpose stress on the basis of stress concentration, so that cracks are first generated at this place, which is conducive to chip fracture.
5、使应力集中处位于单晶硅的解理面上，有利于硅片的断裂及裂纹扩展。5. The stress concentration is located on the cleavage surface of the single crystal silicon, which is beneficial to the fracture and crack expansion of the silicon wafer.
6、V形尖角的引入以及尖角与尖角的角对角处理实际上可以控制局部位置应力的大小以及最大应力出现的位置，进一步地可以控制芯片破坏区域以至破坏碎片数量。6. The introduction of V-shaped sharp corners and the corner-to-corner treatment of sharp corners and sharp corners can actually control the magnitude of local stress and the location of maximum stress, and further control the chip damage area and the number of broken fragments.
附图说明Description of drawings
图1为衬底为<110>晶向时，解理面与硅片表面的夹角情况。Figure 1 shows the angle between the cleavage plane and the surface of the silicon wafer when the substrate is in the <110> crystal orientation.
图2为衬底为<100>晶向时，解理面与硅片表面的夹角情况。Figure 2 shows the angle between the cleavage plane and the surface of the silicon wafer when the substrate is in the <100> crystal orientation.
图3为实施例四的正视图，其特征是在实施例一的基础上，在深槽两侧增加V形尖角。Fig. 3 is the front view of the fourth embodiment, which is characterized in that on the basis of the first embodiment, V-shaped sharp corners are added on both sides of the deep groove.
图4为实施例一、实施例四、实施例五的剖面图，其填充材料为金属锌。Fig. 4 is a cross-sectional view of Embodiment 1, Embodiment 4, and Embodiment 5, and the filling material thereof is metallic zinc.
图5为实施例一、实施例二的正视图。Fig. 5 is the front view of Embodiment 1 and Embodiment 2.
图6为实施例二的剖面图，其填充材料为金属锌和热膨胀微球。Fig. 6 is a sectional view of the second embodiment, the filling material is metal zinc and thermal expansion microspheres.
图7为实施例三的剖面图，其中槽5的侧面为{111}晶向。该结构在实施例一的基础上刻蚀了窄深槽，其目的是使裂纹沿解理面扩展。使用该种结构要求硅片为<110>晶向。Fig. 7 is a cross-sectional view of the third embodiment, in which the side surface of the groove 5 is in the {111} crystal direction. In this structure, narrow and deep grooves are etched on the basis of the first embodiment, the purpose of which is to make cracks propagate along the cleavage plane. The use of this structure requires the silicon wafer to be <110> oriented.
图8为实施例三的背面正视图，其特征是在实施例一的基础上，在硅片上刻蚀窄深槽，使窄深槽的侧面为硅片的解理面。Fig. 8 is the rear front view of the third embodiment, which is characterized in that on the basis of the first embodiment, a narrow and deep groove is etched on the silicon wafer, so that the side of the narrow and deep groove is the cleavage surface of the silicon wafer.
图9为图3中a点到b点的应力分布图。Fig. 9 is a stress distribution diagram from point a to point b in Fig. 3 .
图10为实施例五的背面正视图，其特征是在改变填充金属的图形，使硅片在深槽的拐角处产生应力集中点。Fig. 10 is the front view of the back of the fifth embodiment, which is characterized in that the pattern of the filling metal is changed, so that the silicon wafer produces a stress concentration point at the corner of the deep groove.
图11为实施例六的剖面图，其填充材料为金属锌，自毁结构与芯片工作区域在同一面。Fig. 11 is a cross-sectional view of the sixth embodiment, the filling material is metal zinc, and the self-destruct structure is on the same side as the working area of the chip.
其中，填充金属1、芯片2、电极3、热膨胀剂4、窄深槽5、芯片工作区6，V形尖角7、拐角8。Among them, the filling metal 1, the chip 2, the electrode 3, the thermal expansion agent 4, the narrow and deep groove 5, the chip working area 6, the V-shaped sharp corner 7, and the corner 8.
具体实施方式detailed description
作为可选的技术方案，可以在填充金属之前先填入热膨胀剂后再填入金属。某些材料在达到一定温度后相变(固态、液态、气态相互转化或者固态一级相变)，这些材料相变后会产生体积的变化。热膨胀微球(Thermally Expandable Microspheres)是一钟极其微小的球形颗粒，其外部为气密性良好的的热塑性球体，内部封装低沸点烃类，以氢氧化镁(Mg(OH)2)为分散剂，丙烯腈(AN)和甲基丙烯酸甲酯(MMA)为主要聚合单体，偶氮二异丁氰(AIBN)为引发剂，三羟甲基丙烷三丙烯酸酯(TMPTA)为交联剂，利用悬浮聚合法制备。热膨胀微球在达到其临界温度之前体积基本保持不变，高于临界温度后球体内的烃类相变为气态，其体积会瞬间膨胀几十倍，球体外部的塑性材料可以保持住体积变化后的形态。另外热膨胀微球的临界温度可以通过制备工艺很好地控制。填充的金属用于通电升温使热膨胀微球达到其临界温度。As an optional technical solution, the thermal expansion agent can be filled before the metal is filled, and then the metal can be filled. Certain materials undergo a phase change (solid, liquid, gaseous interconversion or solid-state first-order phase transition) after reaching a certain temperature, and these materials will produce a volume change after the phase transition. Thermally Expandable Microspheres (Thermally Expandable Microspheres) are extremely small spherical particles, the outside of which is a thermoplastic sphere with good airtightness, and the inside is encapsulated with low-boiling point hydrocarbons. Magnesium hydroxide (Mg(OH)2) is used as a dispersant , acrylonitrile (AN) and methyl methacrylate (MMA) are the main polymerization monomers, azobisisobutylcyanide (AIBN) is the initiator, trimethylolpropane triacrylate (TMPTA) is the crosslinking agent, Prepared by suspension polymerization. The volume of the heat-expandable microsphere remains basically unchanged before reaching its critical temperature. After the critical temperature is higher than the critical temperature, the hydrocarbons in the sphere change into a gaseous state, and its volume will expand dozens of times instantaneously. The plastic material outside the sphere can maintain the volume after the volume change. status. In addition, the critical temperature of the thermally expandable microspheres can be well controlled through the preparation process. The filled metal is used to heat up the heat-expandable microspheres to reach their critical temperature.
作为可选的技术方案，金属上所加的电压可以为脉冲式电压，这一方面可以避免金属因为的局部位置温度过高熔化导致断路，另一方面脉冲式电压可以引入循环应力，因而可以产生疲劳裂纹扩展。As an optional technical solution, the voltage applied to the metal can be a pulse voltage. On the one hand, it can prevent the metal from being broken due to the high temperature of the local part of the metal. On the other hand, the pulse voltage can introduce cyclic stress, so it can produce fatigue crack growth.
实施例一Embodiment one
本实施例的剖面如图4所示，背面正视图如图5所示。包括金属锌1，硅片2、电极3，芯片工作区6。本实施例中，硅片正面是芯片的工作区域，背面是芯片的销毁装置。在背面刻蚀出深槽，槽内填充金属锌，最后将电极引出到芯片的控制电路上。本实施例中硅片尺寸为1cm×1cm×350μm(350μm为常规芯片减薄后的厚度，下同)，槽的宽度为100μm，厚度为75μm，槽与槽之间的距离为100μm。当达到触发条件时，控制电路给电极加上电压。为了避免填充的金属在局部位置因为高温熔断，所加的电压可以为脉冲式电压。当电极电压为3V时，金属锌产生焦耳热并热膨胀，该自毁装置在15秒时间内升温至300摄氏度，此时硅片的最大弯曲量为240μm，金属下方硅的应力为400MPa，硅的局部位置如金属的边缘和尖角处硅的应力约为1GPa。The section of this embodiment is shown in FIG. 4 , and the front view of the back is shown in FIG. 5 . Including metal zinc 1, silicon chip 2, electrode 3, chip working area 6. In this embodiment, the front side of the silicon wafer is the chip working area, and the back side is the chip destroying device. Etch a deep groove on the back, fill the groove with metal zinc, and finally lead the electrodes to the control circuit of the chip. In this embodiment, the size of the silicon wafer is 1 cm×1 cm×350 μm (350 μm is the thickness of conventional chips after thinning, the same below), the width of the grooves is 100 μm, the thickness is 75 μm, and the distance between grooves is 100 μm. When the trigger condition is met, the control circuit applies voltage to the electrodes. In order to prevent the filled metal from melting due to high temperature in a local position, the applied voltage can be a pulsed voltage. When the electrode voltage is 3V, the metal zinc generates Joule heat and expands thermally, and the self-destruct device heats up to 300 degrees Celsius in 15 seconds. At this time, the maximum bending amount of the silicon wafer is 240 μm, and the stress of the silicon under the metal is 400 MPa. The stress of silicon at local locations such as the edges and sharp corners of the metal is about 1 GPa.
实施例二Embodiment two
本实施例的剖面图如图6所示，背面正视图如图5所示。包括金属铜1，硅片2，电极3、热膨胀微球4，芯片工作区6。同样在芯片背面刻蚀深槽，然后先填充热膨胀微球，再填充金属铜，最后将电极引出到控制电路上。本实施例中硅片尺寸为1cm×1cm×350μm，槽深100μm、宽100μm、槽间距100μm，热膨胀微球厚度50μm，金属铜厚度50μm。满足触发条件后，金属铜通电产生焦耳热，当电极所加电压为3V时，温度在10秒内可以达到热膨胀微球的临界温度，此时热膨胀微球体积会迅速膨胀几十倍，可以使芯片物理销毁。The sectional view of this embodiment is shown in FIG. 6 , and the front view of the back is shown in FIG. 5 . Including metal copper 1, silicon chip 2, electrode 3, thermal expansion microsphere 4, and chip working area 6. Also etch deep grooves on the back of the chip, then first fill the thermal expansion microspheres, then fill the metal copper, and finally lead the electrodes to the control circuit. In this embodiment, the size of the silicon wafer is 1 cm×1 cm×350 μm, the groove depth is 100 μm, the width is 100 μm, the groove spacing is 100 μm, the thickness of thermal expansion microspheres is 50 μm, and the thickness of metal copper is 50 μm. When the trigger condition is met, the metal copper is energized to generate Joule heat. When the voltage applied to the electrode is 3V, the temperature can reach the critical temperature of thermal expansion microspheres within 10 seconds. At this time, the volume of thermal expansion microspheres will expand dozens of times rapidly, which can make Chips are physically destroyed.
实施例三Embodiment three
本实施例的剖面图如图7所示，背面正视图如图8所示。包括金属铝1，硅片2，电极3、窄深槽5，芯片工作区6。本实施例同样先刻蚀深槽，在槽内填充金属铝，然后刻蚀窄深槽5，引出电极。本实施例中硅片尺寸为1cm×1cm×350μm，金属条的宽度为100μm，厚度为75μm，金属条之间的距离为100μm。当硅片晶向为<110>时，调整刻蚀方向可以使窄深槽5的剖面为{111}面。当电极电压为3V时，温度在10秒内可上升至300℃，硅片因金属铝热膨胀受力弯曲，弯曲量可达240um，硅片中应力达到400MPa。深槽处应力集中，且槽深方向与解理面的方向相同，这样会使裂纹顺着解理面扩展，大大降低了硅片断裂的难度。The sectional view of this embodiment is shown in FIG. 7 , and the front view of the back is shown in FIG. 8 . It includes metal aluminum 1, silicon wafer 2, electrode 3, narrow and deep groove 5, and chip working area 6. In this embodiment, the deep grooves are etched first, the metal aluminum is filled in the grooves, and then the narrow deep grooves 5 are etched to lead out the electrodes. In this embodiment, the size of the silicon wafer is 1 cm×1 cm×350 μm, the width of the metal strips is 100 μm, the thickness is 75 μm, and the distance between the metal strips is 100 μm. When the crystal orientation of the silicon wafer is <110>, adjusting the etching direction can make the cross section of the narrow and deep groove 5 a {111} plane. When the electrode voltage is 3V, the temperature can rise to 300°C within 10 seconds, the silicon wafer is bent due to the thermal expansion of metal aluminum, and the bending amount can reach 240um, and the stress in the silicon wafer can reach 400MPa. Stress is concentrated at the deep groove, and the direction of the groove depth is the same as the direction of the cleavage plane, which will cause the crack to propagate along the cleavage plane, greatly reducing the difficulty of breaking the silicon wafer.
实施例四Embodiment Four
本实施例的剖面图如图4所示，背面正视图如图3所示。包括金属锌1，硅片2，电极3、芯片工作区6。本实施例在实施例一的基础上在刻蚀的槽的两边增加了V形尖角。本实施例中硅片的尺寸为1cm×1cm×350μm，槽的宽度为100μm，厚度为75μm，槽与槽之间的距离为100μm，槽边缘处的V形尖角的夹角为90°，尖角与尖角的距离为20um。接收到自毁信号，电极通电后金属锌迅速热膨胀，向芯片中引入应力，在V形尖角处会产生应力集中，尖角与尖角相对会使应力叠加，因而尖角尖端的应力远大于芯片中其他位置的应力，该处会率先产生裂纹。当电极所加电压为3V时，自毁装置在15秒内升温至300℃，金属锌因热膨胀向芯片中引入应力。图9为图3中a点到b点的应力分布图，硅片中V形尖角处的应力为2.8GPa，而硅中其他区域的应力低于500MPa。因此通过这种方式一方面可以明显增大局部位置的应力从而降低硅片断裂难度，另一方面可以控制硅片的断裂区域。The sectional view of this embodiment is shown in FIG. 4 , and the front view of the back is shown in FIG. 3 . Including metal zinc 1, silicon chip 2, electrode 3, chip working area 6. In this embodiment, on the basis of the first embodiment, V-shaped sharp corners are added on both sides of the etched groove. In this embodiment, the size of the silicon chip is 1 cm × 1 cm × 350 μm, the width of the groove is 100 μm, the thickness is 75 μm, the distance between the grooves is 100 μm, and the included angle of the V-shaped sharp angle at the edge of the groove is 90°. The distance between sharp corners and sharp corners is 20um. After receiving the self-destruct signal, the metal zinc expands rapidly after the electrode is energized, and introduces stress into the chip. Stress concentration will occur at the sharp corner of the V shape. Stress elsewhere in the chip where cracks would be the first to develop. When the voltage applied to the electrodes is 3V, the self-destruct device will heat up to 300°C within 15 seconds, and the metal zinc will introduce stress into the chip due to thermal expansion. Figure 9 is a stress distribution diagram from point a to point b in Figure 3, the stress at the V-shaped sharp corner in the silicon wafer is 2.8GPa, while the stress in other areas of the silicon is lower than 500MPa. Therefore, in this way, on the one hand, the stress at the local position can be significantly increased to reduce the difficulty of breaking the silicon wafer, and on the other hand, the fracture area of the silicon wafer can be controlled.
实施例五Embodiment five
本实施例的剖面图如图4所示，填充金属的图形如图10所示。包括金属锌1，硅片2，电极3、芯片工作区6。本实施例在实施例一的基础上改变了刻蚀的槽的形状。本实施例中，硅片的尺寸为1cm×1cm×350μm，金属条的宽度为100μm，厚度为75μm，金属条之间的距离为100μm。采用这种图形可以使金属锌在x方向和y方向的膨胀量相同，因而使金属锌在拐角处(图10中8所示)的x方向的应力等于y方向的应力，在这种情况下该点的合应力最大。电极接通电源后金属锌中会产生较大的电流，导致金属迅速升温热膨胀。电极电压为3V时，在15秒内升温至300℃，而拐角处硅片的应力明显高于硅片中其他位置，裂纹会从该处萌生。The sectional view of this embodiment is shown in FIG. 4 , and the pattern of the filling metal is shown in FIG. 10 . Including metal zinc 1, silicon chip 2, electrode 3, chip working area 6. In this embodiment, the shape of the etched groove is changed on the basis of the first embodiment. In this embodiment, the size of the silicon wafer is 1 cm×1 cm×350 μm, the width of the metal strips is 100 μm, the thickness is 75 μm, and the distance between the metal strips is 100 μm. Using this figure can make the expansion of the metal zinc in the x direction and the y direction the same, so that the stress in the x direction of the metal zinc at the corner (shown as 8 in Figure 10) is equal to the stress in the y direction, in this case The resultant stress at this point is maximum. After the electrode is powered on, a large current will be generated in the metal zinc, which will cause the metal to heat up rapidly and expand thermally. When the electrode voltage is 3V, the temperature rises to 300°C within 15 seconds, and the stress of the silicon wafer at the corner is obviously higher than other positions in the silicon wafer, and cracks will initiate from this place.
实施例六Embodiment six
本实施例的剖面图如图11所示，自毁装置区域正视图如图3所示。包括金属锌，硅片2，电极3，芯片工作区6，V形尖角7。以上所论述的实施例中自毁结构均在芯片工作区的背面，本实施例中，自毁结构和芯片工作区域在同一面，自毁结构与芯片需要自毁的区域相邻。在该区域旁边刻蚀深槽，淀积金属锌，引出电极与控制电路完成互连。本实施例中槽的宽度和深度可以根据硅片的尺寸做调整。对于1cm×1cm×350μm的硅片，其深度为100μm，厚度为75μm，槽与槽之间的距离为100μm。触发后，金属通电产生焦耳热并热膨胀。电极电压为3V时，自毁结构在15秒内升温至300摄氏度。因为自毁区域上面有很多凹槽，引入了很多应力集中点，在该温度下硅片呈脆性，很小的弯曲量即会使芯片断裂。裂纹扩展至芯片工作区域，芯片就会无法工作，完成自毁。The sectional view of this embodiment is shown in FIG. 11 , and the front view of the self-destruct device area is shown in FIG. 3 . It includes metal zinc, silicon chip 2, electrode 3, chip working area 6, and V-shaped sharp corner 7. In the embodiments discussed above, the self-destruct structure is on the back of the chip working area. In this embodiment, the self-destruct structure and the chip working area are on the same side, and the self-destruct structure is adjacent to the area where the chip needs to self-destruct. Etch a deep groove next to this area, deposit metal zinc, and complete the interconnection between the extraction electrode and the control circuit. The width and depth of the groove in this embodiment can be adjusted according to the size of the silicon wafer. For a silicon wafer of 1 cm×1 cm×350 μm, the depth is 100 μm, the thickness is 75 μm, and the distance between grooves is 100 μm. When triggered, the metal is electrified to generate Joule heat and thermally expand. With an electrode voltage of 3V, the self-destructing structure heated up to 300°C within 15 seconds. Because there are many grooves on the self-destruct area, many stress concentration points are introduced. At this temperature, the silicon chip is brittle, and a small amount of bending will cause the chip to break. If the crack extends to the working area of the chip, the chip will not work and will self-destruct.
本发明通过某些金属热膨胀引入应力，通过顺着解理面刻蚀窄深槽、利用金属的V形尖角产生应力集中等方法降低硅片的断裂难度，可以使芯片在应力集中处首先产生裂纹进而使芯片断裂。本发明利用填充不同图形的金属，对芯片刻槽、填充膨胀剂等方法达到对芯片的可控销毁，具有销毁烈度低，稳定性高等特点。The invention introduces stress through the thermal expansion of some metals, and reduces the difficulty of breaking the silicon chip by etching narrow and deep grooves along the cleavage plane and using V-shaped sharp corners of the metal to generate stress concentration, so that the chip can be first produced at the place of stress concentration. The crack in turn breaks the chip. The invention utilizes the metals filled with different patterns to achieve the controllable destruction of the chip by cutting grooves on the chip, filling expansion agents and other methods, and has the characteristics of low destruction intensity and high stability.
| Application Number | Priority Date | Filing Date | Title |
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| CN201610427727.7ACN106098673B (en) | 2016-06-14 | 2016-06-14 | One kind is used for IC chip self-distruction structure |
| Application Number | Priority Date | Filing Date | Title |
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| CN201610427727.7ACN106098673B (en) | 2016-06-14 | 2016-06-14 | One kind is used for IC chip self-distruction structure |
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