技术领域technical field
本发明涉及半导体领域，具体地，本发明涉及一种半导体器件及其制备方法、电子装置。The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device, a preparation method thereof, and an electronic device.
背景技术Background technique
随着半导体技术的不断发展，集成电路性能的提高主要是通过不断缩小集成电路器件的尺寸以提高它的速度来实现的。目前，由于在追求高器件密度、高性能和低成本中半导体工业已经进步到纳米技术工艺节点，半导体器件的制备受到各种物理极限的限制。With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limits.
随着CMOS器件尺寸的不断缩小，来自制造和设计方面的挑战促使了三维设计如鳍片场效应晶体管(FinFET)的发展。相对于现有的平面晶体管，FinFET是用于20nm及以下工艺节点的先进半导体器件，其可以有效控制器件按比例缩小所导致的难以克服的短沟道效应，还可以有效提高在衬底上形成的晶体管阵列的密度，同时，FinFET中的栅极环绕鳍片(鳍形沟道)设置，因此能从三个面来控制静电，在静电控制方面的性能也更突出。As the dimensions of CMOS devices continue to shrink, manufacturing and design challenges have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Compared with the existing planar transistors, FinFET is an advanced semiconductor device for 20nm and below process nodes, which can effectively control the insurmountable short channel effect caused by device scaling down, and can also effectively improve the formation on the substrate. At the same time, the gate in the FinFET is arranged around the fin (fin-shaped channel), so the static electricity can be controlled from three sides, and the performance in terms of static electricity control is also more prominent.
在LDD离子注入中，在狭窄的鳍片上的离子注入引起的Si损坏，会引起的巨大的LDD电阻，这成为增强所述FinFET器件性能的关键问题，尤其是对于NMOS中的As离子注入，大剂量的离子注入对于狭窄的鳍片来说成为一个很大的隐患，，主要是因为鳍片会遭受无定型并且由于缺乏晶种很难晶体化。In LDD ion implantation, Si damage caused by ion implantation on narrow fins can cause huge LDD resistance, which becomes a key issue in enhancing the performance of said FinFET devices, especially for As ion implantation in NMOS, large Dosed ion implantation becomes a big hazard for narrow fins, mainly because the fins suffer from amorphousness and are difficult to crystallize due to the lack of seeds.
目前降低狭窄鳍片上LDD电阻的方法大都通过大剂量热离子注入的方法，来控制离子注入损坏问题，但是热离子注入工艺需要硬掩膜层，这会进一步增加工艺挑战，同时会增加工艺成本。At present, most of the methods for reducing LDD resistance on narrow fins use high-dose thermal ion implantation to control ion implantation damage, but the thermal ion implantation process requires a hard mask layer, which will further increase process challenges and increase process costs.
因此，为了提高半导体器件的性能和良率，需要对器件的制备方法作进一步的改进，以便消除上述问题。Therefore, in order to improve the performance and yield of semiconductor devices, it is necessary to further improve the manufacturing method of the devices so as to eliminate the above-mentioned problems.
发明内容Contents of the invention
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.
本发明为了克服目前存在问题，提供了一种半导体器件的制备方法，包括：In order to overcome the current existing problems, the present invention provides a method for preparing a semiconductor device, including:
步骤S1：提供半导体衬底，在所述半导体衬底上形成有若干鳍片，其中，所述半导体衬底包括NMOS区域和PMOS区域，在所述NMOS区域上形成有环绕所述鳍片的NMOS栅极，在所述PMOS区域上形成有环绕所述鳍片的PMOS栅极；Step S1: providing a semiconductor substrate on which several fins are formed, wherein the semiconductor substrate includes an NMOS region and a PMOS region, and an NMOS region surrounding the fins is formed on the NMOS region a gate, a PMOS gate surrounding the fin is formed on the PMOS region;
步骤S2：在所述NMOS栅极和所述PMOS栅极的侧壁上形成偏移侧壁；Step S2: forming offset sidewalls on the sidewalls of the NMOS gate and the PMOS gate;
步骤S3：在所述PMOS栅极两侧的鳍片上外延生长第一半导体材料层，以形成PMOS抬升源漏；Step S3: epitaxially growing a first semiconductor material layer on the fins on both sides of the PMOS gate to form a PMOS raised source and drain;
步骤S4：去除所述NMOS栅极侧壁上的所述偏移侧壁，并在所述NMOS栅极两侧的所述鳍片上生长第二半导体材料层，以形成NMOS抬升源漏。Step S4: removing the offset sidewalls on the sidewalls of the NMOS gate, and growing a second semiconductor material layer on the fins on both sides of the NMOS gate to form NMOS raised source and drain.
可选地，在所述步骤S3中，先在所述NMOS区域形成遮蔽层，再形成所述PMOS抬升源漏。Optionally, in the step S3, a shielding layer is first formed in the NMOS region, and then the raised source and drain of the PMOS are formed.
可选地，所述第一半导体材料层选用SiGe，所述第二半导体材料层选用SiC。Optionally, SiGe is selected for the first semiconductor material layer, and SiC is selected for the second semiconductor material layer.
可选地，所述步骤S1包括：Optionally, the step S1 includes:
步骤S11：提供半导体衬底并执行离子注入，以形成阱；Step S11: providing a semiconductor substrate and performing ion implantation to form a well;
步骤S12：图案化所述半导体衬底，以在所述NMOS区域和所述PMOS区域形成所述鳍片；Step S12: patterning the semiconductor substrate to form the fins in the NMOS region and the PMOS region;
步骤S13：沉积隔离材料层，以覆盖所述鳍片，然后回蚀刻所述隔离材料层，以露出所述鳍片至目标高度。Step S13 : Depositing an isolation material layer to cover the fins, and then etching back the isolation material layer to expose the fins to a target height.
可选地，所述步骤S1还进一步包括：Optionally, the step S1 further includes:
步骤S14：执行沟道停止注入，以形成沟道穿通停止层；Step S14: performing channel stop implantation to form a channel punching stop layer;
步骤S15：沉积栅极氧化物和栅极材料层并图案化，以分别形成所述NMOS栅极和所述PMOS栅极；Step S15: Depositing a gate oxide and a gate material layer and patterning to form the NMOS gate and the PMOS gate respectively;
步骤S16：执行源漏LDD注入。Step S16: performing source-drain LDD implantation.
可选地，所述方法还进一步包括：Optionally, the method further includes:
步骤S5：分别对所述PMOS抬升源漏和所述NMOS抬升源漏执行离子注入步骤；Step S5: performing an ion implantation step on the PMOS raised source and drain and the NMOS raised source and drain respectively;
步骤S6：执行退火步骤。Step S6: Perform an annealing step.
可选地，在所述步骤S4中，在去除所述NMOS栅极上的所述偏移侧壁之后形成所述NMOS抬升源漏之前，所述方法还进一步包括在所述NMOS栅极的侧壁上形成间隙壁的步骤。Optionally, in the step S4, before forming the NMOS raised source and drain after removing the offset sidewall on the NMOS gate, the method further includes The step of forming a spacer on the wall.
可选地，在所述步骤S3中，在形成所述PMOS抬升源漏之前，所述方法还包括在所述PMOS栅极的偏移侧壁上形成间隙壁的步骤。Optionally, in the step S3, before forming the raised source and drain of the PMOS, the method further includes the step of forming a spacer on the offset sidewall of the PMOS gate.
本发明还提供了一种如上述的方法制备得到的半导体器件。The present invention also provides a semiconductor device prepared by the above method.
本发明还提供了一种电子装置，包括上述的半导体器件。The present invention also provides an electronic device, including the above-mentioned semiconductor device.
本发明为了解决现有技术中存在的问题，提供了一种半导体器件的制备方法，在所述方法中在形成PMOS抬升源漏之后，去除所述NMOS栅极侧壁上的偏移侧壁，然后在外延生长SiC形成NMOS抬升源漏，通过所述方法可以减小LDD的长度，可以降低LDD电阻,还同时增强沟道来自SIC的应力同时还可以从沟道以及抬升源漏中提供更多的晶种，以提高形成晶体的可能性，通过减小从抬升源漏到沟道的所述偏移侧壁，可以降低所述LDD注入损坏，提高所述半导体器件的性能。In order to solve the problems existing in the prior art, the present invention provides a method for manufacturing a semiconductor device. In the method, after the PMOS raised source and drain are formed, the offset sidewall on the sidewall of the NMOS gate is removed, Then epitaxially grow SiC to form NMOS raised source and drain. By this method, the length of LDD can be reduced, the resistance of LDD can be reduced, and at the same time, the stress of the channel from the SIC can be enhanced, and more can be provided from the channel and the raised source and drain. The seed crystals are used to increase the possibility of crystal formation, and by reducing the offset sidewall from the raised source drain to the channel, the damage of the LDD implantation can be reduced, and the performance of the semiconductor device can be improved.
附图说明Description of drawings
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的装置及原理。在附图中，The following drawings of the invention are hereby included as part of the invention for understanding the invention. Embodiments of the present invention and their descriptions are shown in the drawings to explain the device and principle of the present invention. In the attached picture,
图1a-1e本发明中所述半导体器件的制备过程示意图；1a-1e schematic diagram of the preparation process of the semiconductor device described in the present invention;
图2为制备本发明所述半导体器件的工艺流程图。Fig. 2 is a flow chart of the process for preparing the semiconductor device of the present invention.
具体实施方式Detailed ways
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
现有技术中所述半导体器件的制备方法包括：首先提供衬底，所述衬底包括NMOS区域和PMOS区域，在衬底上形成硬掩膜层；接着，图案化所述硬掩膜层，形成用于蚀刻衬底以在其上形成鳍片的多个彼此隔离的掩膜；接着，蚀刻衬底以在其上形成多个鳍；接着，沉积形成多个鳍片之间的隔离结构；最后，蚀刻去除所述硬掩膜层。The manufacturing method of the semiconductor device in the prior art includes: firstly providing a substrate, the substrate includes an NMOS region and a PMOS region, and forming a hard mask layer on the substrate; then, patterning the hard mask layer, forming a plurality of masks isolated from each other for etching the substrate to form fins thereon; then etching the substrate to form a plurality of fins thereon; then depositing and forming isolation structures between the plurality of fins; Finally, the hard mask layer is removed by etching.
然后执行沟道穿通停止层离子注入，并在所述鳍片上形成栅极，在所述栅极的侧壁上形成间隙壁，在PMOS栅极两侧的所述鳍片上外延生长SiGe，以形成抬升源漏，接着在所述NMOS栅极两侧的所述鳍片上外延生长SiC，以形成抬升源漏，并执行源漏注入、进行退火。Then perform channel punching stop layer ion implantation, form a gate on the fin, form spacers on the side walls of the gate, and epitaxially grow SiGe on the fins on both sides of the PMOS gate to form Lifting the source and drain, and then epitaxially growing SiC on the fins on both sides of the NMOS gate to form the raised source and drain, performing source and drain implantation, and performing annealing.
其中，由于鳍片的宽度很小，在NMOS中的As离子注入时，对于狭窄的鳍片来说成为一个很大的隐患，会造成很大的离子注入损害，需要大注入剂量的离子注入来减小LDD电阻，但是如此以来鳍片会遭受无定型问题并且由于缺乏晶种很难晶体化。Among them, due to the small width of the fins, it becomes a great hidden danger for the narrow fins during the As ion implantation in NMOS, which will cause great ion implantation damage, and requires ion implantation with a large implant dose. Reduces LDD resistance, but then fins suffer from amorphousness and are difficult to crystallize due to lack of seeds.
实施例1Example 1
下面结合图1a-1e、图2对本发明所述半导体器件以及制备方法做进一步的说明。The semiconductor device and the manufacturing method of the present invention will be further described below with reference to FIGS. 1a-1e and FIG. 2 .
执行步骤201，提供半导体衬底101并执行离子注入，以形成阱。Step 201 is executed to provide a semiconductor substrate 101 and perform ion implantation to form a well.
在该步骤中所述半导体衬底101可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。In this step, the semiconductor substrate 101 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S- SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
其中所述半导体衬底包括NMOS区域和PMOS区域，以在后续的步骤中形成NMOS器件和PMOS器件。Wherein the semiconductor substrate includes an NMOS region and a PMOS region, so as to form NMOS devices and PMOS devices in subsequent steps.
接着在所述半导体衬底101上形成垫氧化物层(Pad oxide)，其中所述垫氧化物层(Pad oxide)的形成方法可以通过沉积的方法形成，例如化学气相沉积、原子层沉积等方法，还可以通过热氧化所述半导体衬底的表面形成，在此不再赘述。Next, a pad oxide layer (Pad oxide) is formed on the semiconductor substrate 101, wherein the formation method of the pad oxide layer (Pad oxide) can be formed by a deposition method, such as chemical vapor deposition, atomic layer deposition, etc. , can also be formed by thermally oxidizing the surface of the semiconductor substrate, which will not be repeated here.
接着执行步骤202，在半导体衬底101上形成多个鳍片102，鳍片的宽度全部相同，或者鳍片分为具有不同宽度的多个鳍片组。Next, step 202 is executed to form a plurality of fins 102 on the semiconductor substrate 101 , all of which have the same width, or the fins are divided into a plurality of fin groups with different widths.
如图1a所示，具体的形成方法包括：在半导体衬底201上形成硬掩膜层(图中未示出)，形成所述硬掩膜层可以采用本领域技术人员所熟习的各种适宜的工艺，例如化学气相沉积工艺，所述硬掩膜层可以为自下而上层叠的氧化物层和氮化硅层；图案化所述硬掩膜层，形成用于蚀刻半导体衬底101以在其上形成鳍片的多个彼此隔离的掩膜，在一个实施例中，采用自对准双图案(SADP)工艺实施所述图案化过程；蚀刻半导体衬底101以在其上形成鳍片结构。As shown in FIG. 1a, the specific forming method includes: forming a hard mask layer (not shown in the figure) on the semiconductor substrate 201, and various suitable methods familiar to those skilled in the art can be used to form the hard mask layer. process, such as a chemical vapor deposition process, the hard mask layer can be a bottom-up stacked oxide layer and a silicon nitride layer; pattern the hard mask layer to form a semiconductor substrate 101 for etching A plurality of masks isolated from each other on which the fins are formed, in one embodiment, the patterning process is performed using a self-aligned double patterning (SADP) process; the semiconductor substrate 101 is etched to form the fins thereon structure.
进一步，在该步骤中还可以进一步包含执行沟道停止注入，以形成穿通停止层，所述沟道停止注入的注入离子为碳离子、氮离子或者二者的组合，注入离子相对于垂直于半导体衬底101的方向的入射角度为10°-20°。Further, this step may further include performing channel stop implantation to form a through-stop layer, the implanted ions of the channel stop implant are carbon ions, nitrogen ions or a combination of the two, and the implanted ions are relatively perpendicular to the semiconductor The incident angle of the direction of the substrate 101 is 10°-20°.
执行步骤203，沉积隔离材料层103，以覆盖所述鳍片结构。Step 203 is executed to deposit an isolation material layer 103 to cover the fin structure.
具体地，如图1b所示，沉积隔离材料层103，以完全填充鳍片结构之间的间隙。在一个实施例中，采用具有可流动性的化学气相沉积工艺实施所述沉积。隔离材料层103的材料可以选择氧化物，例如HARP。Specifically, as shown in FIG. 1 b , an isolation material layer 103 is deposited to completely fill the gaps between the fin structures. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer 103 can be oxide, such as HARP.
然后回蚀刻所述隔离材料层103，至所述鳍片的目标高度。The isolation material layer 103 is then etched back to the target height of the fins.
具体地，如图1a所示，回蚀刻所述隔离材料层103，以露出部分所述鳍片，进而形成具有特定高度的鳍片。作为示例，实施高温退火，以使隔离材料层103致密化，所述高温退火的温度可以为700℃-1000℃；执行化学机械研磨，直至露出所述硬掩膜层的顶部；去除所述硬掩膜层中的氮化硅层，在一个实施例中，采用湿法蚀刻去除氮化硅层，所述湿法蚀刻的腐蚀液为稀释的氢氟酸；去除所述硬掩膜层中的氧化物层和部分隔离材料层103，以露出鳍片结构的部分，进而形成具有特定高度的鳍片结构。Specifically, as shown in FIG. 1a, the isolation material layer 103 is etched back to expose part of the fins, thereby forming fins with a specific height. As an example, perform high temperature annealing to densify the isolation material layer 103, the temperature of the high temperature annealing may be 700°C-1000°C; perform chemical mechanical polishing until the top of the hard mask layer is exposed; remove the hard mask layer. The silicon nitride layer in the mask layer, in one embodiment, adopts wet etching to remove the silicon nitride layer, and the etching solution of the wet etching is diluted hydrofluoric acid; remove the silicon nitride layer in the hard mask layer The oxide layer and part of the isolation material layer 103 are used to expose part of the fin structure, thereby forming a fin structure with a specific height.
执行步骤204，在所述隔离材料层上形成栅极结构，所述栅极结构包括NMOS栅极结构和PMOS栅极结构，以覆盖所述鳍片。Step 204 is executed to form a gate structure on the isolation material layer, where the gate structure includes an NMOS gate structure and a PMOS gate structure to cover the fins.
具体地，如图1b所示，在该步骤中沉积栅极结构材料层104，所述栅极结构材料层可以选用本领域常用的半导体材料，例如可以选用多晶硅等，并不局限于某一种，在此不再一一列举、Specifically, as shown in FIG. 1b, in this step, the gate structure material layer 104 is deposited. The gate structure material layer can be selected from semiconductor materials commonly used in the field, such as polysilicon, etc., and is not limited to a certain type. , will not be listed here,
所述栅极材料层的沉积方法可以选用化学气相沉积或者原子层沉积等方法。The deposition method of the gate material layer can be selected from methods such as chemical vapor deposition or atomic layer deposition.
然后图案化所述栅极材料层，以形成环绕所述鳍片的栅极结构。The layer of gate material is then patterned to form a gate structure surrounding the fin.
在该步骤中图案化所述栅极结构材料层，以形成环绕栅极结构，具体地，在所述栅极结构材料层上形成掩膜层叠层105，其中所述掩膜叠层包括依次沉积的氧化物层、金属硬掩膜层(例如NiT)、氧化物硬掩膜层，然后曝光显影，以形成开口，然后以所述掩膜叠层为掩膜蚀刻所述栅极结构材料层，以形成环绕栅极结构。In this step, the gate structure material layer is patterned to form a surrounding gate structure, specifically, a mask layer stack 105 is formed on the gate structure material layer, wherein the mask stack layer includes sequential deposition The oxide layer, the metal hard mask layer (such as NiT), and the oxide hard mask layer are then exposed and developed to form an opening, and then the gate structure material layer is etched using the mask stack as a mask, to form a surrounding gate structure.
可选地，在所述鳍片和所述栅极结构之间还可以进一步形成栅极结构介电层。Optionally, a gate structure dielectric layer may be further formed between the fin and the gate structure.
执行步骤205，在所述栅极结构的侧壁上形成偏移侧壁106。Step 205 is executed to form offset sidewalls 106 on the sidewalls of the gate structure.
具体地，如图1c所示，在步骤中沉积偏移侧壁材料层，以覆盖所述栅极结构，并执行全面蚀刻步骤，以去除所述栅极结构侧壁以外的所述偏移侧壁材料层，以形成所述偏移侧壁106。Specifically, as shown in FIG. 1c, a layer of offset sidewall material is deposited in the step to cover the gate structure, and an overall etching step is performed to remove the offset side other than the sidewall of the gate structure. layer of wall material to form the offset sidewall 106 .
其中，所述偏移侧壁106可以选用本领域常用的材料，在本申请中所述偏移侧壁106选用SiN。Wherein, the offset sidewall 106 can be selected from commonly used materials in the field, and in this application, the offset sidewall 106 is selected from SiN.
执行步骤206，执行离子注入，并在所述栅极结构的两侧形成源漏扩展区(SDE)。Step 206 is executed to perform ion implantation and form source-drain extension regions (SDE) on both sides of the gate structure.
具体地，在该步骤中可以使用剂量较大的离子注入，在此不再赘述。Specifically, a relatively large dose of ion implantation may be used in this step, which will not be repeated here.
执行步骤207，在所述PMOS栅极两侧的鳍片上外延生长第一半导体材料层，以形成PMOS抬升源漏108。Step 207 is executed to epitaxially grow a first semiconductor material layer on the fins on both sides of the PMOS gate to form a PMOS raised source and drain 108 .
具体地，如图1d所示，在该步骤中在所述NMOS区域形成遮蔽层107，以遮蔽所述NMOS区域，然后在所述PMOS栅极结构两侧的所述鳍片上选择性外延生长(SEG)形成所述SiGe层，具体地，选用含硅气体作为原料气体，选用含Ge气体作为掺杂，在载气的输送下进入反应室，进而外延得到所述SiGe层。可选地，外延生长所述SiGe层的同时可以进行原位掺杂(in-situ doped)。Specifically, as shown in FIG. 1d, in this step, a shielding layer 107 is formed in the NMOS region to shield the NMOS region, and then selectively epitaxially grows on the fins on both sides of the PMOS gate structure ( SEG) to form the SiGe layer. Specifically, silicon-containing gas is selected as the raw material gas, Ge-containing gas is selected as the doping gas, and the carrier gas is transported into the reaction chamber, and then the SiGe layer is obtained by epitaxy. Optionally, in-situ doping can be performed while the SiGe layer is epitaxially grown.
执行步骤208，去除所述NMOS栅极侧壁上的所述偏移侧壁，并在所述NMOS栅极两侧的所述鳍片上生长第二半导体衬底材料层，以形成NMOS抬升源漏109。Execute step 208, remove the offset sidewall on the sidewall of the NMOS gate, and grow a second semiconductor substrate material layer on the fins on both sides of the NMOS gate to form an NMOS raised source and drain 109.
具体地，如图1e所示，去除所述NMOS栅极侧壁上的所述偏移侧壁，减小从抬升源漏到沟道的所述偏移侧壁，以减小LDD的长度。Specifically, as shown in FIG. 1 e , the offset sidewall on the sidewall of the NMOS gate is removed, and the offset sidewall from the raised source drain to the channel is reduced, so as to reduce the length of the LDD.
然后在NMOS区域中在所述栅极结构的两侧外延生长SiC层，以形成抬升SiC源漏极。在本发明中采用选择性外延生长(SEG)形成所述SiC层，具体地，选用含硅气体作为原料气体，选用含C气体作为掺杂，在载气的输送下进入反应室，进而外延得到所述SiC层。可选地，外延生长所述SiC层的同时可以进行原位掺杂(in-situ doped)，可以掺杂磷或者砷等，例如外延的同时通入含磷或砷的气体。Then epitaxially grow SiC layers on both sides of the gate structure in the NMOS region to form raised SiC source and drain electrodes. In the present invention, the SiC layer is formed by using selective epitaxial growth (SEG). Specifically, a silicon-containing gas is selected as a raw material gas, and a C-containing gas is selected as a doping gas, which enters the reaction chamber under the transport of a carrier gas, and then obtained by epitaxy. the SiC layer. Optionally, in-situ doping (in-situ doped) can be performed while the SiC layer is grown epitaxially, and phosphorus or arsenic can be doped, for example, a gas containing phosphorus or arsenic can be introduced during epitaxy.
在去除所述NMOS栅极侧壁上的偏移侧壁之后，可以从沟道以及抬升源漏中提供更多的晶种，以提高形成晶体的可能性，通过可以降低所述LDD注入损坏，提高所述半导体器件的性能。After removing the offset sidewall on the sidewall of the NMOS gate, more seeds can be provided from the channel and the raised source and drain to increase the possibility of forming crystals, which can reduce the damage of the LDD implant, The performance of the semiconductor device is improved.
执行步骤209，再次执行离子注入步骤并进行快速热退火。Step 209 is executed to perform ion implantation and rapid thermal annealing again.
在本发明中为了证激活杂质又能抑制杂质的深度和横向扩散，执行完所述离子注入后进行快速热退火，可选地，所述快速热退火温度为1000-1050℃。In the present invention, in order to verify that the impurity is activated and the depth and lateral diffusion of the impurity can be suppressed, rapid thermal annealing is performed after the ion implantation. Optionally, the rapid thermal annealing temperature is 1000-1050° C.
至此，完成了本发明实施例的半导体器件的制备过程的介绍。在上述步骤之后，还可以包括其他相关步骤，此处不再赘述。并且，除了上述步骤之外，本实施例的制备方法还可以在上述各个步骤之中或不同的步骤之间包括其他步骤，这些步骤均可以通过现有技术中的各种工艺来实现，此处不再赘述。So far, the introduction of the manufacturing process of the semiconductor device according to the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which will not be repeated here. Moreover, in addition to the above steps, the preparation method of this embodiment can also include other steps in the above steps or between different steps, and these steps can be realized by various processes in the prior art, here No longer.
本发明为了解决现有技术中存在的问题，提供了一种半导体器件的制备方法，在所述方法中在形成PMOS抬升源漏之后，去除所述NMOS栅极侧壁上的偏移侧壁，然后在外延生长SiC形成NMOS抬升源漏，通过所述方法可以减小LDD的长度，同时还可以从沟道以及抬升源漏中提供更多的晶种，以提高形成晶体的可能性，通过减小从抬升源漏到沟道的所述偏移侧壁，可以降低所述LDD注入损坏，提高所述半导体器件的性能。In order to solve the problems existing in the prior art, the present invention provides a method for manufacturing a semiconductor device. In the method, after the PMOS raised source and drain are formed, the offset sidewall on the sidewall of the NMOS gate is removed, Then epitaxially grow SiC to form NMOS raised sources and drains, by which the length of LDD can be reduced, and more seeds can be provided from the channel and raised sources and drains to increase the possibility of forming crystals, by reducing The small offset sidewall from the raised source drain to the channel can reduce the damage of the LDD implantation and improve the performance of the semiconductor device.
图2为本发明一具体地实施方式中所述半导体器件制备流程图，具体地包括：Fig. 2 is a flow chart of the preparation of the semiconductor device described in a specific embodiment of the present invention, specifically including:
步骤S1：提供半导体衬底，在所述半导体衬底上形成有若干鳍片，其中，所述半导体衬底包括NMOS区域和PMOS区域，在所述NMOS区域上形成有环绕所述鳍片的NMOS栅极，在所述PMOS区域上形成有环绕所述鳍片的PMOS栅极；Step S1: providing a semiconductor substrate on which several fins are formed, wherein the semiconductor substrate includes an NMOS region and a PMOS region, and an NMOS region surrounding the fins is formed on the NMOS region a gate, a PMOS gate surrounding the fin is formed on the PMOS region;
步骤S2：在所述NMOS栅极和所述PMOS栅极的侧壁上形成偏移侧壁；Step S2: forming offset sidewalls on the sidewalls of the NMOS gate and the PMOS gate;
步骤S3：在所述PMOS栅极两侧的鳍片上外延生长第一半导体材料层，以形成PMOS抬升源漏；Step S3: epitaxially growing a first semiconductor material layer on the fins on both sides of the PMOS gate to form a PMOS raised source and drain;
步骤S4：去除所述NMOS栅极侧壁上的所述偏移侧壁，并在所述NMOS栅极两侧的所述鳍片上生长第二半导体材料层，以形成NMOS抬升源漏。Step S4: removing the offset sidewalls on the sidewalls of the NMOS gate, and growing a second semiconductor material layer on the fins on both sides of the NMOS gate to form NMOS raised source and drain.
实施例2Example 2
本发明还提供了一种半导体器件，所述半导体器件选用实施例1所述的方法制备。所述半导体器件中NMOS栅极的侧壁上没有形成偏移侧壁，减小从抬升源漏到沟道的所述偏移侧壁，可以减小LDD的长度，同时还可以从沟道以及抬升源漏中提供更多的晶种，以提高形成晶体的可能性，提高所述半导体器件的性能。The present invention also provides a semiconductor device, which is prepared by the method described in Embodiment 1. There is no offset sidewall formed on the sidewall of the NMOS gate in the semiconductor device, and reducing the offset sidewall from the raised source drain to the channel can reduce the length of the LDD, and at the same time can also be obtained from the channel and More seed crystals are provided in the raised source and drain to increase the possibility of forming crystals and improve the performance of the semiconductor device.
实施例3Example 3
本发明还提供了一种电子装置，包括实施例2所述的半导体器件。其中，半导体器件为实施例2所述的半导体器件，或根据实施例1所述的制备方法得到的半导体器件。The present invention also provides an electronic device, including the semiconductor device described in Embodiment 2. Wherein, the semiconductor device is the semiconductor device described in Embodiment 2, or the semiconductor device obtained according to the preparation method described in Embodiment 1.
本实施例的电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可为任何包括所述半导体器件的中间产品。本发明实施例的电子装置，由于使用了上述的半导体器件，因而具有更好的性能。The electronic device of this embodiment can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV set, VCD, DVD, navigator, camera, video recorder, voice recorder, MP3, MP4, PSP, etc. , can also be any intermediate product including the semiconductor device. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.
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| TR01 | Transfer of patent right | Effective date of registration:20200319 Address after:201203 floor 6, building 3, No. 18, Zhangjiang Road, free trade zone, Pudong New Area, Shanghai Patentee after:SMIC INTERNATIONAL NEW TECHNOLOGY R&D (SHANGHAI) Co.,Ltd. Address before:201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before:Semiconductor Manufacturing International (Shanghai) Corp. |