技术领域technical field
本发明涉及显示设备技术领域，更具体地说，涉及一种阵列基板和显示面板。The present invention relates to the technical field of display devices, and more specifically, to an array substrate and a display panel.
背景技术Background technique
如图1所示，图1为现有的一种阵列基板的俯视结构示意图，该阵列基板包括位于显示区域的多条栅极线10、多条数据线11、由多条栅极线10和多条数据线11绝缘交叉限定出的多个子像素区12以及位于非显示区域的栅极驱动电路13和数据驱动电路14。该阵列基板还包括位于显示区域的多个色阻15，每个色阻15与至少一个子像素区12对应设置。其中，栅极驱动电路13包括多个子栅极驱动电路130，每条栅极线10都与两个子栅极驱动电路130相连，这两个子栅极驱动电路130分别位于阵列基板相对的两侧，且每个子栅极驱动电路130在数据线11延伸方向(如图1中箭头所示X方向)上的长度L1等于一个子像素区12在数据线11延伸方向上的长度L2。As shown in FIG. 1 , FIG. 1 is a schematic top view of an existing array substrate, which includes a plurality of gate lines 10 located in the display area, a plurality of data lines 11 , and a plurality of gate lines 10 and A plurality of data lines 11 are insulated and intersect to define a plurality of sub-pixel regions 12 and a gate driving circuit 13 and a data driving circuit 14 located in a non-display region. The array substrate also includes a plurality of color resists 15 located in the display area, and each color resist 15 is set corresponding to at least one sub-pixel region 12 . Wherein, the gate driving circuit 13 includes a plurality of sub-gate driving circuits 130, and each gate line 10 is connected to two sub-gate driving circuits 130, and the two sub-gate driving circuits 130 are respectively located on opposite sides of the array substrate, And the length L 1 of each sub-gate driving circuit 130 in the extending direction of the data line 11 (the X direction shown by the arrow in FIG. 1 ) is equal to the length L2 of one sub-pixel region 12 in the extending direction of the data line11 .
在该阵列基板的制作过程中，由于生产线内的防静电水平较差，因此，在栅极驱动电路13制作完成后，需要对栅极驱动电路13进行AOI(AutomaticOptic Inspection，自动光学检测)检测，以检测该栅极驱动电路13中是否存在短路或断路等常见缺陷。但是，与不具有色阻的阵列基板相比，上述具有色阻15的阵列基板的栅极驱动电路13的AOI检测效率较低。During the manufacturing process of the array substrate, due to the poor anti-static level in the production line, after the gate drive circuit 13 is fabricated, it is necessary to perform AOI (Automatic Optic Inspection) detection on the gate drive circuit 13, To detect whether there are common defects such as short circuit or open circuit in the gate driving circuit 13 . However, compared with the array substrate without color resistance, the AOI detection efficiency of the gate driving circuit 13 of the above-mentioned array substrate with color resistance 15 is lower.
发明内容Contents of the invention
有鉴于此，本发明提供了一种阵列基板和显示面板，以解决现有技术中的阵列基板的栅极驱动电路AOI检测效率较低的问题。In view of this, the present invention provides an array substrate and a display panel to solve the problem of low AOI detection efficiency of the gate drive circuit of the array substrate in the prior art.
为实现上述目的，本发明提供如下技术方案：To achieve the above object, the present invention provides the following technical solutions:
一种阵列基板，包括显示区域和非显示区域，所述显示区域包括多条栅极线、多条数据线和多个色阻，所述多条栅极线和所述多条数据线绝缘交叉限定出多个子像素区，所述色阻与所述子像素区对应设置；An array substrate, including a display area and a non-display area, the display area includes a plurality of gate lines, a plurality of data lines and a plurality of color resistors, and the plurality of gate lines and the plurality of data lines are insulated and intersect A plurality of sub-pixel areas are defined, and the color resistance is set correspondingly to the sub-pixel areas;
所述非显示区域包括栅极驱动电路，所述栅极驱动电路包括多个子栅极驱动电路，每个所述子栅极驱动电路都与所述栅极线连接，且至少一条所述栅极线与一个所述子栅极驱动电路相连；The non-display area includes a gate drive circuit, the gate drive circuit includes a plurality of sub-gate drive circuits, each of the sub-gate drive circuits is connected to the gate line, and at least one of the gate lines The line is connected to one of the sub-gate drive circuits;
其中，所述子栅极驱动电路在所述数据线延伸方向上的长度大于或等于所述子像素区在所述数据线延伸方向上的长度的1.5倍。Wherein, the length of the sub-gate driving circuit in the extending direction of the data line is greater than or equal to 1.5 times the length of the sub-pixel region in the extending direction of the data line.
一种显示面板，包括阵列基板和与所述阵列基板相对设置的对向基板，所述阵列基板为如上所述的阵列基板。A display panel, comprising an array substrate and an opposite substrate disposed opposite to the array substrate, the array substrate is the above-mentioned array substrate.
与现有技术相比，本发明所提供的技术方案具有以下优点：Compared with the prior art, the technical solution provided by the present invention has the following advantages:
本发明所提供的阵列基板和显示面板，由于至少一条栅极线与一个子栅极驱动电路相连，因此，与现有技术中每条栅极线都与两个子栅极驱动电路相连的方案相比，本发明中子栅极驱动电路的个数较少，因此，可以相对提高具有色阻的阵列基板上栅极驱动电路的AOI检测效率；并且，在减少子栅极驱动电路的个数的基础上，本发明中的子栅极驱动电路在数据线延伸方向上的长度可以大于或等于子像素区在数据线延伸方向上的长度的1.5倍，从而可以减小子栅极驱动电路内器件的分布密度，进一步提高栅极驱动电路的AOI检测效率。In the array substrate and display panel provided by the present invention, since at least one gate line is connected to one sub-gate drive circuit, it is different from the scheme in the prior art that each gate line is connected to two sub-gate drive circuits. Compared with the number of sub-gate drive circuits in the present invention, the number of sub-gate drive circuits is relatively small, so the AOI detection efficiency of the gate drive circuit on the array substrate with color resistance can be relatively improved; and, in reducing the number of sub-gate drive circuits Basically, the length of the sub-gate drive circuit in the present invention in the direction of data line extension can be greater than or equal to 1.5 times the length of the sub-pixel region in the direction of data line extension, thereby reducing the number of devices in the sub-gate drive circuit. The distribution density further improves the AOI detection efficiency of the gate drive circuit.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.
图1为现有的一种阵列基板的俯视结构示意图；FIG. 1 is a schematic top view of an existing array substrate;
图2为本发明实施例提供的一种阵列基板的俯视结构示意图；FIG. 2 is a schematic top view of an array substrate provided by an embodiment of the present invention;
图3为图2所示的阵列基板的剖面结构示意图；FIG. 3 is a schematic cross-sectional structure diagram of the array substrate shown in FIG. 2;
图4为本发明实施例提供的另一种阵列基板的剖面结构示意图；4 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present invention;
图5为本发明实施例提供的另一种阵列基板的俯视结构示意图；FIG. 5 is a schematic top view of another array substrate provided by an embodiment of the present invention;
图6为本发明实施例提供的又一种阵列基板的俯视结构示意图；FIG. 6 is a schematic top view of another array substrate provided by an embodiment of the present invention;
图7为本发明实施例提供的又一种阵列基板的俯视结构示意图；FIG. 7 is a schematic top view of another array substrate provided by an embodiment of the present invention;
图8为本发明实施例提供的又一种阵列基板的俯视结构示意图；FIG. 8 is a schematic top view of another array substrate provided by an embodiment of the present invention;
图9为本发明实施例提供的显示面板的剖面结构示意图。FIG. 9 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention.
具体实施方式detailed description
正如背景技术所述，与不具有色阻的阵列基板相比，具有色阻的阵列基板的栅极驱动电路的AOI检测效率较低。这是因为，在不具有色阻的阵列基板上，栅极驱动电路未被色阻覆盖，可采用可见光成像进行AOI检测；而在具有色阻的阵列基板上，为了减小显示区域和非显示区域的段差，非显示区域也会设置色阻，即栅极驱动电路会被色阻覆盖，由于可见光中的大部分光会被色阻过滤，因此，无法采用可见光对被色阻覆盖的栅极驱动电路进行AOI检测，基于此，现有技术中，采用红外光对被色阻覆盖的栅极驱动电路进行AOI检测，但是，相对于可见光图像而言，红外光图像的清晰度较低，从而导致AOI检测的效率较低。As mentioned in the background, compared with the array substrate without color resistance, the AOI detection efficiency of the gate driving circuit of the array substrate with color resistance is lower. This is because, on an array substrate without color resistance, the gate drive circuit is not covered by color resistance, and visible light imaging can be used for AOI detection; while on an array substrate with color resistance, in order to reduce the display area and non-display The color resistance is also set in the non-display area, that is, the gate drive circuit will be covered by the color resistance. Since most of the light in the visible light will be filtered by the color resistance, it is impossible to use visible light to control the grid covered by the color resistance. The drive circuit performs AOI detection. Based on this, in the prior art, infrared light is used to perform AOI detection on the gate drive circuit covered by color resistance. However, compared with visible light images, the definition of infrared light images is low, so As a result, the efficiency of AOI detection is low.
发明人研究发现，通过减少子栅极驱动电路的个数和TFT等器件的分布密度，可以提高栅极驱动电路的AOI检测效率。基于此，本发明提供了一种阵列基板，以克服现有技术存在的上述问题，该阵列基板包括显示区域和非显示区域；The inventors have found through research that the AOI detection efficiency of the gate drive circuit can be improved by reducing the number of sub-gate drive circuits and the distribution density of devices such as TFTs. Based on this, the present invention provides an array substrate to overcome the above-mentioned problems in the prior art, the array substrate includes a display area and a non-display area;
所述显示区域包括多条栅极线、多条数据线和多个色阻，所述多条栅极线和所述多条数据线绝缘交叉限定出多个子像素区，所述色阻与所述子像素区对应设置；所述非显示区域包括栅极驱动电路，所述栅极驱动电路包括多个子栅极驱动电路，每个所述子栅极驱动电路都与所述栅极线连接，且至少一条所述栅极线与一个所述子栅极驱动电路相连；其中，所述子栅极驱动电路在所述数据线延伸方向上的长度大于或等于所述子像素区在所述数据线延伸方向上的长度的1.5倍。The display area includes a plurality of gate lines, a plurality of data lines and a plurality of color resistors, the plurality of gate lines and the plurality of data lines are insulated and intersect to define a plurality of sub-pixel regions, and the color resistors are connected to the color resistors. The sub-pixel area is correspondingly arranged; the non-display area includes a gate drive circuit, and the gate drive circuit includes a plurality of sub-gate drive circuits, and each of the sub-gate drive circuits is connected to the gate line, And at least one of the gate lines is connected to one of the sub-gate drive circuits; wherein, the length of the sub-gate drive circuit in the extending direction of the data line is greater than or equal to the length of the sub-pixel region in the data line 1.5 times the length in the direction in which the line extends.
本发明所提供的阵列基板中，子栅极驱动电路的个数较少，可以相对提高具有色阻的阵列基板上栅极驱动电路的AOI检测效率；并且，子栅极驱动电路在数据线延伸方向上的长度大于或等于子像素区在数据线延伸方向上的长度的1.5倍，从而可以减小子栅极驱动电路内器件的分布密度，进一步提高栅极驱动电路的AOI检测效率。In the array substrate provided by the present invention, the number of sub-gate drive circuits is relatively small, which can relatively improve the AOI detection efficiency of the gate drive circuit on the array substrate with color resistance; The length in the direction is greater than or equal to 1.5 times the length of the sub-pixel region in the direction in which the data lines extend, so that the distribution density of devices in the sub-gate drive circuit can be reduced, and the AOI detection efficiency of the gate drive circuit can be further improved.
以上是本发明的核心思想，为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The above is the core idea of the present invention. In order to make the above-mentioned purpose, features and advantages of the present invention more obvious and understandable, the specific implementation modes of the present invention will be described in detail below in conjunction with the accompanying drawings. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明的一个实施例提供了一种阵列基板，参考图2，图2为本发明实施例提供的一种阵列基板的俯视结构示意图，该阵列基板包括显示区域和位于显示区域四周的非显示区域。该显示区域包括多条栅极线20、多条数据线21以及由多条栅极线20和多条数据线21绝缘交叉限定出的多个子像素区22，该非显示区域包括数据驱动电路30和栅极驱动电路31。An embodiment of the present invention provides an array substrate. Referring to FIG. 2, FIG. 2 is a schematic top view of an array substrate provided by an embodiment of the present invention. The array substrate includes a display area and a non-display area located around the display area. . The display area includes a plurality of gate lines 20, a plurality of data lines 21, and a plurality of sub-pixel regions 22 defined by insulating intersections of a plurality of gate lines 20 and a plurality of data lines 21, and the non-display area includes a data drive circuit 30 and gate drive circuit 31.
其中，每个子像素区22都对应设置一个子像素，每个子像素都包括设置在该子像素区22内的薄膜晶体管23和像素电极24。参考图3，图3为图2所示的阵列基板的剖面结构示意图，该薄膜晶体管23包括位于基板1上的栅极230、源极231和漏极232，其栅极230与对应的栅极线20相连、源极231与对应的数据线21相连、漏极232通过过孔240与像素电极24相连。此外，该阵列基板还包括位于基板1上的公共电极25，该公共电极25与多个子像素区22对应设置，以通过公共电极25和像素电极24之间的电压差驱动相应的子像素进行图像的显示。Wherein, each sub-pixel region 22 is provided with a corresponding sub-pixel, and each sub-pixel includes a thin film transistor 23 and a pixel electrode 24 disposed in the sub-pixel region 22 . Referring to FIG. 3, FIG. 3 is a schematic cross-sectional structure diagram of the array substrate shown in FIG. The line 20 is connected, the source electrode 231 is connected to the corresponding data line 21 , and the drain electrode 232 is connected to the pixel electrode 24 through the via hole 240 . In addition, the array substrate also includes a common electrode 25 located on the substrate 1, and the common electrode 25 is arranged correspondingly to the plurality of sub-pixel regions 22, so as to drive the corresponding sub-pixels to form an image through the voltage difference between the common electrode 25 and the pixel electrode 24. display.
本实施例中的阵列基板还包括色阻层26，该色阻层26包括黑矩阵260和多个色阻261，黑矩阵260在阵列基板的显示区域限定出多个色阻区域，每个色阻区域设置一个色阻261，且该色阻261与子像素区22对应设置。可选的，每个色阻261与一个子像素区22对应设置，或者，每个色阻261与多个子像素区22对应设置。The array substrate in this embodiment also includes a color-resist layer 26, the color-resist layer 26 includes a black matrix 260 and a plurality of color-resistors 261, the black matrix 260 defines a plurality of color-resist regions in the display area of the array substrate, and each color-resistor A color resistance 261 is provided in the resistance area, and the color resistance 261 is corresponding to the sub-pixel area 22 . Optionally, each color resistance 261 is set corresponding to one sub-pixel region 22 , or each color resistance 261 is set corresponding to multiple sub-pixel regions 22 .
其中，为了减小显示区域和非显示区域的段差，本实施例中的色阻261至少部分覆盖子栅极驱动电路310。如图2所示，位于阵列基板左右两侧的色阻261至少部分覆盖与其相邻的子栅极驱动电路310，可选的，色阻261至少覆盖子栅极驱动电路310面积的80％。Wherein, in order to reduce the level difference between the display area and the non-display area, the color resistor 261 in this embodiment at least partially covers the sub-gate driving circuit 310 . As shown in FIG. 2 , the color resistors 261 located on the left and right sides of the array substrate at least partially cover the sub-gate driving circuit 310 adjacent thereto. Optionally, the color resistors 261 cover at least 80% of the area of the sub-gate driving circuit 310 .
在图3所示的结构中，色阻层26位于薄膜晶体管层和像素电极层之间，其中，薄膜晶体管层是指薄膜晶体管23所在膜层，像素电极层是指像素电极24所在膜层，当然，本发明并不仅限于此，色阻层26可以位于薄膜晶体管层、像素电极层和公共电极层中任意两层之间，即色阻层26可以位于薄膜晶体管23所在膜层、像素电极24所在膜层和公共电极25所在膜层中任意两层之间。In the structure shown in FIG. 3 , the color resistance layer 26 is located between the thin film transistor layer and the pixel electrode layer, wherein the thin film transistor layer refers to the film layer where the thin film transistor 23 is located, and the pixel electrode layer refers to the film layer where the pixel electrode 24 is located. Of course, the present invention is not limited thereto. The color resistance layer 26 can be located between any two layers of the thin film transistor layer, the pixel electrode layer and the common electrode layer, that is, the color resistance layer 26 can be located on the film layer where the thin film transistor 23 is located, the pixel electrode 24 between the film layer where the common electrode 25 is located and any two layers in the film layer where the common electrode 25 is located.
在图3所示的结构中，公共电极25所在膜层位于像素电极24所在膜层的表面，但是，本发明并不仅限于此，在其他实施例中，如图4所示，图4为本发明实施例提供的另一种阵列基板的剖面结构示意图，公共电极25所在膜层位于像素电极24所在膜层和色阻层26之间，此时，薄膜晶体管23的漏极232通过贯穿对应色阻和对应公共电极25的过孔241与该色阻表面的像素电极24相连。In the structure shown in FIG. 3, the film layer where the common electrode 25 is located is located on the surface of the film layer where the pixel electrode 24 is located, but the present invention is not limited thereto. In other embodiments, as shown in FIG. 4, FIG. The schematic cross-sectional structure diagram of another array substrate provided by the embodiment of the invention, the film layer where the common electrode 25 is located is located between the film layer where the pixel electrode 24 is located and the color resistance layer 26, at this time, the drain 232 of the thin film transistor 23 passes through the corresponding color The resistor and the via hole 241 corresponding to the common electrode 25 are connected to the pixel electrode 24 on the surface of the color resistor.
本实施例中，参考图2，数据驱动电路30与所有的数据线21相连，用于向数据线21提供数据信号。栅极驱动电路31包括多个子栅极驱动电路310，每个子栅极驱动电路310都与栅极线20相连，用于向与栅极线20提供扫描信号，以控制与该栅极线20相连的薄膜晶体管23导通，从而使得数据线21中的数据信号通过导通的薄膜晶体管23传输到像素电极24中，进而使得该像素电极24对应的子像素进行图像的显示。In this embodiment, referring to FIG. 2 , the data driving circuit 30 is connected to all the data lines 21 for providing data signals to the data lines 21 . The gate drive circuit 31 includes a plurality of sub-gate drive circuits 310, each sub-gate drive circuit 310 is connected to the gate line 20, and is used to provide a scan signal to the gate line 20 to control the gate line 20 connected to the gate line 20. The thin film transistor 23 is turned on, so that the data signal in the data line 21 is transmitted to the pixel electrode 24 through the turned on thin film transistor 23 , so that the sub-pixel corresponding to the pixel electrode 24 displays an image.
其中，本实施例中的子栅极驱动电路310为移位寄存器，其结构与现有的阵列基板中的移位寄存器的结构相同，在此不再赘述。并且，本实施例中，子栅极驱动电路310之间的连接关系只是移位寄存器的一种级联方式，本发明并不仅限于此，在其他实施例中，子栅极驱动电路310之间可以采用其他级联方式。Wherein, the sub-gate driving circuit 310 in this embodiment is a shift register, and its structure is the same as that of the shift register in the existing array substrate, and will not be repeated here. Moreover, in this embodiment, the connection relationship between the sub-gate driving circuits 310 is only a cascading mode of shift registers, and the present invention is not limited thereto. In other embodiments, the connection relationship between the sub-gate driving circuits 310 Other cascading methods can be used.
本实施例中，至少一条栅极线20与一个子栅极驱动电路310相连，从而可以减少阵列基板上子栅极驱动电路310的个数，进而提高栅极驱动电路31的AOI检测效率。在此基础上，本实施例中子栅极驱动电路310在数据线21延伸方向(如图2中箭头所示X方向)上的长度L3大于或等于子像素区22在数据线21延伸方向上的长度L4的1.5倍，以减小子栅极驱动电路内TFT等器件的分布密度，进而可以通过提高成像清晰度来提高栅极驱动电路31的AOI检测效率。可选的，本实施例中子栅极驱动电路310在数据线21延伸方向上的长度L3等于子像素区22在数据线21延伸方向上的长度L4的1.7倍，以使本发明实施例中具有色阻261的阵列基板上栅极驱动电路31的AOI检测效率与不具有色阻的阵列基板上栅极驱动电路的AOI检测效率相同或略高。In this embodiment, at least one gate line 20 is connected to one sub-gate driving circuit 310 , so that the number of sub-gate driving circuits 310 on the array substrate can be reduced, thereby improving the AOI detection efficiency of the gate driving circuit 31 . On this basis, in this embodiment, the length L3 of the sub-gate drive circuit 310 in the extending direction of the data line 21 (the X direction shown by the arrow in FIG.2 ) is greater than or equal to the length L3 of the sub-pixel region 22 in the extending direction of the data line 21. 1.5 times of the length L4 above, so as to reduce the distribution density of TFT and other devices in the sub-gate drive circuit, and then improve the AOI detection efficiency of the gate drive circuit 31 by improving the imaging definition. Optionally, the length L3of the sub- gate drive circuit 310 in the extending direction of the data line 21 in this embodiment is equal to 1.7 times the length L4 of the sub-pixel region 22 in the extending direction of the data line 21, so that the present invention can be implemented In this example, the AOI detection efficiency of the gate drive circuit 31 on the array substrate with color resistance 261 is the same or slightly higher than that of the gate drive circuit on the array substrate without color resistance 261 .
下面以子栅极驱动电路310在数据线21延伸方向上的长度L3等于子像素区22在数据线21延伸方向上的长度L4的1.7倍为例，结合具体的实施方式对阵列基板的结构进行说明。Taking the example in which the length L3 of the sub- gate driving circuit 310 in the extending direction of the data line21 is equal to 1.7 times the length L4 of the sub-pixel region 22 in the extending direction of the data line 21 as an example, the array substrate will be analyzed in combination with specific implementation methods. The structure is explained.
在一个具体的实施方式中，如图5所示，图5为本发明实施例提供的另一种阵列基板的俯视结构示意图，每条栅极线20都与一个子栅极驱动电路310连接，并且，这些子栅极驱动电路310分布在阵列基板相对的两侧。图5所示的结构中，多条栅极线20沿数据线21的延伸方向顺序排列，可选的，沿图5中箭头所示X方向排序为奇数的栅极线20的子栅极驱动电路310位于阵列基板的一侧，沿图5中箭头所示X方向排序为偶数的栅极线20的子栅极驱动电路310位于阵列基板相对的另一侧，以提高子栅极驱动电路310分布的均匀性，进而栅极驱动电路31的AOI检测效率。In a specific implementation manner, as shown in FIG. 5 , which is a schematic top view of another array substrate provided by an embodiment of the present invention, each gate line 20 is connected to a sub-gate drive circuit 310 , Moreover, these sub-gate driving circuits 310 are distributed on two opposite sides of the array substrate. In the structure shown in FIG. 5, a plurality of gate lines 20 are arranged sequentially along the extending direction of the data lines 21. Optionally, the sub-gates of the odd-numbered gate lines 20 are arranged along the X direction indicated by the arrow in FIG. The circuit 310 is located on one side of the array substrate, and the sub-gate drive circuits 310 of the even-numbered gate lines 20 are located on the opposite side of the array substrate along the X direction indicated by the arrow in FIG. The uniformity of the distribution, and thus the AOI detection efficiency of the gate drive circuit 31 .
在另一个具体的实施方式中，如图6所示，图6为本发明实施例提供的又一种阵列基板的俯视结构示意图，多条栅极线20包括至少一条第一栅极线201和至少一条第二栅极线202，其中，每条第一栅极线201都与一个子栅极驱动电路310连接，可选的，相邻的两条第一栅极线201相连的子栅极驱动电路310分别位于阵列基板相对的两侧；每条第二栅极线202都与两个子栅极驱动电路310连接，这两个子栅极驱动电路310分别位于阵列基板相对的两侧，且这两个子栅极驱动电路310分别与第二栅极线202的两端连接。In another specific embodiment, as shown in FIG. 6 , which is a schematic top view of another array substrate provided by an embodiment of the present invention, the multiple gate lines 20 include at least one first gate line 201 and At least one second gate line 202, wherein each first gate line 201 is connected to a sub-gate drive circuit 310, and optionally, the sub-gates connected to two adjacent first gate lines 201 The driving circuits 310 are respectively located on opposite sides of the array substrate; each second gate line 202 is connected to two sub-gate driving circuits 310, and the two sub-gate driving circuits 310 are respectively located on opposite sides of the array substrate, and this The two sub-gate driving circuits 310 are respectively connected to both ends of the second gate line 202 .
在图6所示的结构中，至少一条第一栅极线201和至少一条第二栅极线202沿数据线21的延伸方向(如图6中箭头所示X方向)顺序排列，即所有的第一栅极线201顺序排列在阵列基板的上部分，所有的第二栅极线202顺序排列在阵列基板的下部分。In the structure shown in FIG. 6, at least one first gate line 201 and at least one second gate line 202 are arranged sequentially along the extending direction of the data line 21 (the X direction shown by the arrow in FIG. 6), that is, all The first gate lines 201 are sequentially arranged on the upper part of the array substrate, and all the second gate lines 202 are sequentially arranged on the lower part of the array substrate.
但是，在其他实施例中，如图7所示，图7为本发明实施例提供的又一种阵列基板的俯视结构示意图，至少一条第二栅极线202和至少一条第一栅极线201沿数据线21的延伸方向顺序排列，即所有的第二栅极线202顺序排列在阵列基板的上部分，所有的第一栅极线201顺序排列在阵列基板的下部分。However, in other embodiments, as shown in FIG. 7 , which is a schematic top view of another array substrate provided by an embodiment of the present invention, at least one second gate line 202 and at least one first gate line 201 They are arranged sequentially along the extending direction of the data lines 21 , that is, all the second gate lines 202 are sequentially arranged on the upper part of the array substrate, and all the first gate lines 201 are sequentially arranged on the lower part of the array substrate.
或者，在其他实施例中，如图8所示，图8为本发明实施例提供的又一种阵列基板的俯视结构示意图，第一栅极线201和第二栅极线202还可以间隔排序，并且，可选的，相邻的两条第一栅极线201相连的子栅极驱动电路310分别位于阵列基板相对的两侧，本发明并不仅限于此。Or, in other embodiments, as shown in FIG. 8 , which is a schematic top view of another array substrate provided by an embodiment of the present invention, the first gate lines 201 and the second gate lines 202 can also be arranged at intervals. , and, optionally, the sub-gate driving circuits 310 connected to two adjacent first gate lines 201 are respectively located on opposite sides of the array substrate, and the present invention is not limited thereto.
此外，需要说明的是，本实施例中的多个色阻261包括红色色阻、绿色色阻和蓝色色阻，当然，在其他实施例中，多个色阻261也可以包括红色色阻、绿色色阻、蓝色色阻和白色色阻，本发明并不仅限于此。需要说明的是，本实施例中子像素的颜色是由其对应设置的色阻的颜色决定的，也就是说，色阻的颜色是红色，则其对应的子像素的显示颜色也为红色，色阻的颜色是绿色，则其对应的子像素的显示颜色也为绿色，色阻的颜色是蓝色，则其对应的子像素的显示颜色也为蓝色。基于此，可通过不同颜色的子像素混色后进行图像的显示。In addition, it should be noted that the plurality of color resistances 261 in this embodiment include red color resistance, green color resistance and blue color resistance. Of course, in other embodiments, the plurality of color resistances 261 may also include red color resistance, green color resistance, and blue color resistance. Green color resistance, blue color resistance and white color resistance, the present invention is not limited thereto. It should be noted that, in this embodiment, the color of the sub-pixel is determined by the color of its corresponding color resistance, that is, if the color of the color resistance is red, the display color of the corresponding sub-pixel is also red. If the color of the color resistance is green, the display color of the corresponding sub-pixel is also green; if the color of the color resistance is blue, the display color of the corresponding sub-pixel is also blue. Based on this, an image can be displayed after color mixing of sub-pixels of different colors.
本发明实施例提供的阵列基板，由于至少一条栅极线与一个子栅极驱动电路相连，因此，与现有技术中每条栅极线都与两个子栅极驱动电路相连的方案相比，本发明中子栅极驱动电路的个数较少，因此，可以相对提高具有色阻的阵列基板上栅极驱动电路的AOI检测效率；并且，在减少子栅极驱动电路的个数的基础上，本发明中的子栅极驱动电路在数据线延伸方向上的长度可以大于或等于子像素区在数据线延伸方向上的长度的1.5倍，从而可以减小子栅极驱动电路内器件的分布密度，进一步提高栅极驱动电路的AOI检测效率。In the array substrate provided by the embodiment of the present invention, since at least one gate line is connected to one sub-gate driving circuit, compared with the prior art in which each gate line is connected to two sub-gate driving circuits, In the present invention, the number of sub-gate drive circuits is small, so the AOI detection efficiency of the gate drive circuit on the array substrate with color resistance can be relatively improved; and, on the basis of reducing the number of sub-gate drive circuits The length of the sub-gate drive circuit in the present invention in the direction of data line extension can be greater than or equal to 1.5 times the length of the sub-pixel region in the direction of data line extension, thereby reducing the distribution of devices in the sub-gate drive circuit Density, further improving the AOI detection efficiency of the gate drive circuit.
本发明实施例还提供了一种显示面板，如图9所示，该显示面板包括上述任一实施例提供的阵列基板90和与该阵列基板90相对设置的对置基板91，当然，在本发明的一个具体实施方式中，该显示面板还包括设置在阵列基板90和对置基板91之间的液晶层92等，在此不再赘述。基于上述阵列基板结构，本实施例中的显示面板的制作时间较短，成本较低。An embodiment of the present invention also provides a display panel. As shown in FIG. 9 , the display panel includes the array substrate 90 provided in any of the above embodiments and an opposite substrate 91 disposed opposite to the array substrate 90. Of course, in this In a specific embodiment of the invention, the display panel further includes a liquid crystal layer 92 and the like disposed between the array substrate 90 and the opposite substrate 91 , which will not be repeated here. Based on the above structure of the array substrate, the manufacturing time of the display panel in this embodiment is shorter and the cost is lower.
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other. The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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| CN201610617410.XACN106023867B (en) | 2016-07-29 | 2016-07-29 | A kind of array substrate and display panel |
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| CN201610617410.XACN106023867B (en) | 2016-07-29 | 2016-07-29 | A kind of array substrate and display panel |
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| CN106023867B CN106023867B (en) | 2019-12-31 |
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| CN201610617410.XAActiveCN106023867B (en) | 2016-07-29 | 2016-07-29 | A kind of array substrate and display panel |
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