技术领域technical field
本发明是有关于一种半导体元件及其制作方法，且特别是有关于一种存储器元件及其制作方法。The present invention relates to a semiconductor element and its manufacturing method, and in particular to a memory element and its manufacturing method.
背景技术Background technique
非易失性存储器元件，例如闪存，具有在移除电源时亦不丢失储存于存储单元中的信息的特性。已广泛运用于用于便携式音乐播放器、移动电话、数字相机等的固态大容量存储应用。为了达到具有更高密度储存容量的需求，目前已经有各种不同结构的三维存储器元件，例如具有单栅极(single-gate)存储单元、双栅极(double gate)存储单元，和环绕式栅极(surrounding gate)存储单元的三维闪存元件，被提出。Non-volatile memory devices, such as flash memory, have the property of not losing information stored in memory cells when power is removed. It has been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, etc. In order to meet the demand for higher density storage capacity, there are currently various three-dimensional memory devices with different structures, such as single-gate memory cells, double-gate memory cells, and wraparound gate memory cells. A three-dimensional flash memory element of a surrounding gate memory cell is proposed.
三维存储器元件，例如垂直通道式(vertical-channel，VC)三维NAND闪存元件，具有许多层叠层(存储器层)结构，可达到更高的储存容量，更具有优异的电子特性，例如具有良好的数据保存可靠性和操作速度。然而，随着元件尺寸持续缩小化，由导线，例如字线或源极线，的电阻与电容所造成的信号传递延迟(RC delay)，将变成影响三维存储器元件擦除和编程等操作速度的主要因素之一。目前业界多使用较低电阻值的金属作为垂直通道式三维NAND闪存元件的栅极，以减少字线的时间延迟。Three-dimensional memory elements, such as vertical-channel (VC) three-dimensional NAND flash memory elements, have many layers of stacked layers (memory layers) structure, which can achieve higher storage capacity and have excellent electronic characteristics, such as good data Preserve reliability and speed of operation. However, as the size of devices continues to shrink, the signal transfer delay (RC delay) caused by the resistance and capacitance of wires, such as word lines or source lines, will become an influence on the operation speed of three-dimensional memory devices such as erasing and programming. one of the main factors. At present, metals with lower resistance values are mostly used as gates of vertical channel 3D NAND flash memory devices in order to reduce the time delay of word lines.
然而，垂直通道式三维NAND存储器元件的金属栅极制作过程，必须先形成贯穿多层叠层结构中刻蚀沟道，再以另一次刻蚀，经由刻蚀沟道来移除位于层叠层结构中多的牺牲层，方能进行金属栅极(字线)的填充。刻蚀沟道的设置，会占据存储单元的形成空间，影响元件的储存容量。加上，多层叠层结构中容易残留牺牲层，或因为过度刻蚀而损伤存储层，而造成存储单元缺陷，严重影响垂直通道式三维NAND闪存元件的储存容量与工艺良率。However, in the metal gate manufacturing process of the vertical channel type three-dimensional NAND memory element, it is necessary to form an etched channel through the multi-layer stacked structure first, and then use another etching to remove the metal gate located in the stacked layer structure through the etched channel. More sacrificial layers can be used to fill the metal gate (word line). The setting of the etched channel will occupy the formation space of the memory cell and affect the storage capacity of the element. In addition, the sacrificial layer is easy to remain in the multi-layer stack structure, or the storage layer is damaged due to over-etching, resulting in memory cell defects, which seriously affects the storage capacity and process yield of the vertical channel 3D NAND flash memory device.
因此，有需要提供一种更先进的存储器元件及其制作方法，以改善已知技术所面临的问题。Therefore, there is a need to provide a more advanced memory device and its manufacturing method to improve the problems faced by the known technology.
发明内容Contents of the invention
本说明书的一实施例是在提供一种存储器元件。此一存储器元件包括多个含硅导电层、多条串行选择线(selection lines)、多条串行(string)、多条位线(bit lines)、多组多层插塞结构以及多条金属字线(metal strapped wordline)。其中，含硅导电层是相互平行地垂直叠层于基板上。串行选择线位于含硅导电层上方，并沿第一方向延伸。串行垂直于含硅导电层和串行选择线，且电性连接至串行选择线。位线位于串行选择线上方，并沿第二方向延伸，且分别与串行电性连接。多层插塞结构沿第一方向排列设置，将多个串行分别夹设于相邻的二个多层插塞结构之间。其中，每一个多层插塞结构包含多个介层插塞，每一个介层插塞与一个含硅导电层对应导通。金属字线沿第一方向延伸，且每一条金属字线与导通同一个含硅导电层的介层插塞电性连接。An embodiment of the present specification provides a memory device. The memory device includes a plurality of silicon-containing conductive layers, a plurality of selection lines, a plurality of strings, a plurality of bit lines, a plurality of multilayer plug structures, and a plurality of Metal strapped wordline. Wherein, the silicon-containing conductive layers are vertically laminated on the substrate parallel to each other. The serial selection line is located above the silicon-containing conductive layer and extends along the first direction. The strings are perpendicular to the silicon-containing conductive layer and the string selection lines, and are electrically connected to the string selection lines. The bit lines are located above the string selection lines, extend along the second direction, and are electrically connected to the strings respectively. The multi-layer plug structures are arranged along the first direction, and a plurality of series are interposed between two adjacent multi-layer plug structures. Wherein, each multi-layer plug structure includes a plurality of through-layer plugs, and each through-layer plug is correspondingly connected to a silicon-containing conductive layer. The metal word lines extend along the first direction, and each metal word line is electrically connected to the via plug that conducts the same silicon-containing conductive layer.
本说明书的另一实施例是在提供一种存储器元件的制作方法，此一方法包括下述步骤：首先于基板上形成垂直叠层且相互平行的多个含硅导电层。之后，形成多条串行垂直穿设含硅导电层。再于硅导电层上形成多条串行选择线，并使串行选择线沿第一方向延伸，且电性连接这些串行。接着，形成多组多层插塞结构，沿第一方向排列设置，将多个串行分别夹设于相邻两多层插塞结构之间。其中，每一个多层插塞结构包含多个介层插塞，每一个介层插塞与一个含硅导电层对应导通。后续，于串行选择在线方形成多条位线，使位线沿第二方向延伸，且与这些个串行电性连接。再于多层插塞结构上方形成多条金属字线，沿第一方向延伸，并使每一条金属字线与导通同一个含硅导电的介层插塞电性连接。Another embodiment of the present specification provides a manufacturing method of a memory device, which includes the following steps: firstly, forming a plurality of silicon-containing conductive layers stacked vertically and parallel to each other on a substrate. Afterwards, a plurality of vertical silicon-containing conductive layers are formed in series. A plurality of string selection lines are formed on the silicon conductive layer, and the string selection lines are extended along the first direction, and these strings are electrically connected. Next, multiple groups of multi-layer plug structures are formed, arranged in a row along the first direction, and a plurality of series are interposed between two adjacent multi-layer plug structures. Wherein, each multi-layer plug structure includes a plurality of through-layer plugs, and each through-layer plug is correspondingly connected to a silicon-containing conductive layer. Subsequently, a plurality of bit lines are formed on the string selection line, the bit lines extend along the second direction, and are electrically connected with these strings. A plurality of metal word lines are formed on the multi-layer plug structure, extending along the first direction, and each metal word line is electrically connected to the same silicon-containing conductive interlayer plug.
根据上述实施例，本发明是在提供一种存储器元件及其制作方法。其是在三维存储器元件的多层叠层结构中形成多组沿着串行选择线平行排列设置的多层插塞结构，将形成于多层叠层结构中的多条串行分别夹设于两相邻的多层插塞结构之间，并且使多层插塞结构所包含的每一个介层插塞，分别与多层叠层结构中的一个含硅导电层对应导通。并以金属字线将导通同一含硅导电层的多个介层插塞电性连接。通过多层插塞结构和金属字线的连接，来降低三维存储器元件中栅极层的整体电阻率，以减少栅极电阻与电容所造成的信号传递延迟现象。又由于三维存储器元件是采用含硅导电材质作为栅极，不需额外形成金属栅极，可扩大串行选择线的频带宽度，解决已知技术，因为使用金属栅极工艺所导致的储存容量与工艺良率无法提高的问题。According to the above-mentioned embodiments, the present invention provides a memory device and a manufacturing method thereof. It is to form multiple groups of multi-layer plug structures arranged in parallel along the serial selection lines in the multi-layer stacked structure of the three-dimensional memory element, and sandwich the multiple serial lines formed in the multi-layer stacked structure between two phases respectively. Between the adjacent multilayer plug structures, and make each via plug included in the multilayer plug structure respectively conduct with a silicon-containing conductive layer in the multilayer stack structure. The metal word lines are used to electrically connect multiple interlayer plugs that are connected to the same silicon-containing conductive layer. The overall resistivity of the gate layer in the three-dimensional memory element is reduced through the connection of the multi-layer plug structure and the metal word line, so as to reduce the signal transmission delay phenomenon caused by the gate resistance and capacitance. And because the three-dimensional memory element uses silicon-containing conductive material as the gate, it does not need to form an additional metal gate, which can expand the frequency bandwidth of the serial selection line and solve the known technology, because the storage capacity caused by the use of the metal gate process is different from that of The problem that the process yield cannot be improved.
附图说明Description of drawings
为了对本发明的上述实施例及其他目的、特征和优点能更明显易懂，特举数个较佳实施例，并配合所附图式，作详细说明如下：In order to make the above-mentioned embodiments of the present invention and other purposes, features and advantages more obvious and easy to understand, several preferred embodiments are specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows:
图1A是根据本发明的一实施例绘示形成在基板上的多层叠层结构的部分结构透视图；FIG. 1A is a partial structural perspective view illustrating a multi-layer stack structure formed on a substrate according to an embodiment of the present invention;
图1B是绘示在图1A的结构上形成多条串行之后的部分结构透视图；FIG. 1B is a perspective view of part of the structure after forming a plurality of strings on the structure of FIG. 1A;
图1C是根据图1B所绘示的结构上视图；FIG. 1C is a top view of the structure shown in FIG. 1B;
图1D是绘示在第1B的结构上形成多条形成多条串行选择线之后的部分结构透视图；1D is a perspective view of a partial structure after forming a plurality of serial selection lines on the structure of 1B;
图1E是根据图1D所绘示的结构上视图；FIG. 1E is a top view of the structure shown in FIG. 1D;
图1F是绘示在图1D所的结构上形成多组多层插塞结构和接触插塞之后的部分结构透视图；FIG. 1F is a perspective view of a partial structure after forming multiple sets of multilayer plug structures and contact plugs on the structure shown in FIG. 1D;
图1G是根据图1F所绘示的结构上视图；FIG. 1G is a top view of the structure shown in FIG. 1F;
图1H是绘示在图1G的结构上形成多条源极线和位线之后的结构上视图；FIG. 1H is a top view of the structure after forming a plurality of source lines and bit lines on the structure of FIG. 1G;
图1I是绘示在图1H的结构上形成多条金属字线之后的结构上视图；FIG. 1I is a top view of the structure after forming a plurality of metal word lines on the structure of FIG. 1H;
图2A至图2D是根据本发明的一实施例所绘示形成串行的部分结工艺构剖面示意图；2A to 2D are schematic cross-sectional views of a part of the structure of the serial structure according to an embodiment of the present invention;
图3是根据本发明的另一实施例绘示多层插塞结构的另一种阶梯状结构样态；FIG. 3 illustrates another stepped structure of a multilayer plug structure according to another embodiment of the present invention;
图4A是沿着图1H所绘示的切线S1所绘示的部分结构剖面图；FIG. 4A is a partial structural cross-sectional view along the tangent line S1 shown in FIG. 1H;
图4B是沿着图1H所绘示的切线S2所绘示的部分结构剖面图；FIG. 4B is a partial structural cross-sectional view along the tangent line S2 shown in FIG. 1H;
图5是根据本发明的另一实施例所绘示的接地层、源极接触结构与源极线的部分结构剖面示意图；5 is a schematic cross-sectional view of a partial structure of a ground layer, a source contact structure and a source line according to another embodiment of the present invention;
图6A是沿着图1I所绘示的切线S3所绘示的部分结构剖面图；FIG. 6A is a partial structural cross-sectional view along the tangent line S3 shown in FIG. 1I;
图6B是沿着图1I所绘示的切线S4所绘示的部分结构剖面图；以及FIG. 6B is a cross-sectional view of a part of the structure shown along the tangent line S4 shown in FIG. 1I; and
图7是根据本发明的另一实施例所绘示的垂直通道式三维NAND存储器元件的部分结构上视图。FIG. 7 is a partial structural top view of a vertical channel three-dimensional NAND memory device according to another embodiment of the present invention.
【符号说明】【Symbol Description】
10：多层叠层结构10: multi-layer laminated structure
100：垂直通道式三维NAND闪存元件100: vertical channel three-dimensional NAND flash memory element
101：基板101: Substrate
102、112、122、132和142：含硅导电层102, 112, 122, 132 and 142: Silicon-containing conductive layers
103：绝缘层 104：串行103: insulating layer 104: serial
104a：存储层 104b：通道层104a: storage layer 104b: channel layer
105：开口 106：串行选择线105: Opening 106: Serial selection line
107：源极接触结构 107a：介电材质层107: Source contact structure 107a: Dielectric material layer
107b：导电材料 108：开口107b: Conductive material 108: Opening
109：硬掩模层 110：多层插塞结构109: hard mask layer 110: multilayer plug structure
110a、110b、110c和110d：介层插塞110a, 110b, 110c and 110d: via plugs
113：串接金属线 114：接触插塞113: Metal wire in series 114: Contact plug
115：源极 116：位线115: source 116: bit line
117a、117b、117c和117d：金属字线117a, 117b, 117c and 117d: metal word lines
118：源极线 119：导孔118: Source line 119: Guide hole
200：三维存储器元件 301接地层200: three-dimensional memory element 301 ground layer
303：绝缘层 A：区域303: Insulation layer A: Area
D1：两相邻多层插塞结构之间的距离D1: the distance between two adjacent multilayer plug structures
D2：两相邻源极接触结构之间的距离D2: Distance between two adjacent source contact structures
具体实施方式detailed description
本发明提供一种存储器元件以及其制作方法，可降低存储器元件的整体电阻率以减少电阻与电容所造成的信号传递延迟现象。为了对本发明的上述实施例及其他目的、特征和优点能更明显易懂，下文特举垂直通道式三维NAND闪存元件100作为较佳实施例，并配合所附图式作详细说明。The invention provides a memory element and its manufacturing method, which can reduce the overall resistivity of the memory element to reduce the signal transmission delay phenomenon caused by resistance and capacitance. In order to make the above-mentioned embodiment and other objects, features and advantages of the present invention more comprehensible, the vertical channel type three-dimensional NAND flash memory device 100 is specifically taken as a preferred embodiment below, and is described in detail with the accompanying drawings.
但必须注意的是，这些特定的实施案例与方法，并非用以限定本发明。本发明仍可采用其他特征、元件、方法及参数来加以实施。较佳实施例的提出，仅是用以例示本发明的技术特征，并非用以限定本发明的权利要求范围。该技术领域中具有通常知识者，将可根据以下说明书的描述，在不脱离本发明的精神范围内，作均等的修饰与变化。在不同实施例与图式之中，相同的元件，将以相同的元件符号加以表示。However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The invention can still be implemented with other features, elements, methods and parameters. The proposal of the preferred embodiment is only used to illustrate the technical features of the present invention, and is not used to limit the scope of the claims of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes according to the descriptions in the following specification without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be denoted by the same element symbols.
制作垂直通道式三维NAND闪存元件100的方法包括下述步骤：首先于基板101上形成一多层叠层结构10。请参照图1A，图1A是根据本发明的一实施例绘示形成在基板101上的多层叠层结构10部分结构透视图。在本实施例中，多层叠层结构10包含多个含硅导电层102、112、122、132和142和多个绝缘层103。其中，含硅导电层102、112、122、132和142和多个绝缘层103是沿着Z轴方向相互平行地交错叠层堆。The method for manufacturing the vertical channel type three-dimensional NAND flash memory device 100 includes the following steps: firstly, a multi-layer stacked structure 10 is formed on the substrate 101 . Please refer to FIG. 1A . FIG. 1A is a perspective view illustrating a partial structure of a multilayer stack structure 10 formed on a substrate 101 according to an embodiment of the present invention. In this embodiment, the multilayer stack structure 10 includes a plurality of silicon-containing conductive layers 102 , 112 , 122 , 132 and 142 and a plurality of insulating layers 103 . Wherein, the silicon-containing conductive layers 102 , 112 , 122 , 132 and 142 and the plurality of insulating layers 103 are stacked in parallel with each other along the Z-axis.
在本发明的一些实施例之中，含硅导电层102、112、122、132和142较佳可以由多晶硅材质所构成；绝缘层103较佳可以由氧化硅(silicon oxide)材质所构成。虽然图1A所绘示的多层叠层结构10仅包含5层含硅导电层102、112、122、132和142以及4层绝缘层103。但其仅为例示，在其他实施例之中，含硅导电层和绝缘层的数量并不以此为限。In some embodiments of the present invention, the silicon-containing conductive layers 102 , 112 , 122 , 132 and 142 are preferably made of polysilicon; the insulating layer 103 is preferably made of silicon oxide. Although the multi-layer stack structure 10 shown in FIG. 1A only includes five silicon-containing conductive layers 102 , 112 , 122 , 132 and 142 and four insulating layers 103 . But it is only an example, and in other embodiments, the quantity of the silicon-containing conductive layer and the insulating layer is not limited thereto.
之后，形成多条串行104垂直穿设含硅导电层102、112、122、132和142和绝缘层103。请参照图1B和图1C，图1B是绘示在图1A的结构上形成多条串行104之后的部分结构透视图。图1C是根据图1B所绘示的结构上视图。After that, a plurality of series 104 are formed to vertically pass through the silicon-containing conductive layers 102 , 112 , 122 , 132 and 142 and the insulating layer 103 . Please refer to FIG. 1B and FIG. 1C . FIG. 1B is a perspective view of a partial structure after forming a plurality of strings 104 on the structure of FIG. 1A . FIG. 1C is a top view of the structure shown in FIG. 1B .
在本发明的一实施例之中，每一条串行104都包含一存储层104a和一通道层104b。存储层104a可以是由一氮化硅(silicon nitride)层、一氧化硅层和一氮化硅层所构成的NON结构。通道层104b较佳为多晶硅材质。通过这些串行104和含硅导电层102、112、122、132和142的交错，可定义出多个排列为多列(rows)及多行(columns)的存储单元(cells)。In an embodiment of the present invention, each string 104 includes a storage layer 104a and a channel layer 104b. The storage layer 104a may be a NON structure composed of a silicon nitride layer, a silicon oxide layer and a silicon nitride layer. The channel layer 104b is preferably made of polysilicon. Through the interlacing of the strings 104 and the silicon-containing conductive layers 102 , 112 , 122 , 132 and 142 , a plurality of memory cells arranged in rows and columns can be defined.
例如。在本发明的一些实施例之中，存储单元的排列方式可以为一矩阵阵列(matrix array)。在本发明的另一些实施例之中，存储单元的排列方式也可以为一蜂巢状阵列(honeycomb array)。但值得注意的是，本发明的实施例并不以此二种存储单元的排列态样为限，任何适用于三维存储器元件的设计规范(design rule)，皆未脱离本案的精神范围。For example. In some embodiments of the present invention, the arrangement of the memory cells may be a matrix array. In other embodiments of the present invention, the arrangement of the storage units may also be a honeycomb array. However, it is worth noting that the embodiments of the present invention are not limited to the arrangement of the two memory cells, and any design rules applicable to three-dimensional memory elements do not deviate from the spirit of the present case.
请参照图2A至图2D，图2A至图2D是根据本发明的一实施例绘示形成串行104的部分工艺结构剖面示意图。串行104的形成可以包括下述步骤：首先以刻蚀工艺在多层叠层结构10(包括含硅导电层102、112、122、132和142和绝缘层103)中形成多个开口105，以暴露出一部份基板101(如图2A所绘示)。接着，于开口侧壁及底部沉积存储层104a，再于存储层104a上沉积半导体材质，例如多晶硅或锗，以形成通道层104b(如图2B所绘示)。之后，在通道层104b上沉积一层硬掩模层109，藉以在开口105侧壁形成串行104(如图2C所绘示)。Please refer to FIG. 2A to FIG. 2D . FIG. 2A to FIG. 2D are cross-sectional schematic diagrams illustrating a partial process structure for forming the string 104 according to an embodiment of the present invention. The formation of the series 104 may include the following steps: first, a plurality of openings 105 are formed in the multilayer stack structure 10 (including the silicon-containing conductive layers 102, 112, 122, 132, and 142 and the insulating layer 103) by an etching process, so as to A part of the substrate 101 is exposed (as shown in FIG. 2A ). Next, a storage layer 104a is deposited on the sidewall and bottom of the opening, and then a semiconductor material such as polysilicon or germanium is deposited on the storage layer 104a to form a channel layer 104b (as shown in FIG. 2B ). Afterwards, a hard mask layer 109 is deposited on the channel layer 104b, so as to form the series 104 on the sidewall of the opening 105 (as shown in FIG. 2C ).
后续，再以非等向刻蚀移除硬掩模层109及一部分存储层104a和通道层104b，而将一部分的基板101由开口105暴露出来。并以多晶硅选择性地在暴露于外的基板101上形成源极115，使串行104与作为垂直通道式三维NAND闪存元件100的接地层的基板101电性连接(如图2D所绘示)。Subsequently, the hard mask layer 109 and a part of the storage layer 104 a and the channel layer 104 b are removed by anisotropic etching, and a part of the substrate 101 is exposed through the opening 105 . And polysilicon is used to selectively form the source 115 on the exposed substrate 101, so that the string 104 is electrically connected to the substrate 101 as the ground layer of the vertical channel type three-dimensional NAND flash memory device 100 (as shown in FIG. 2D ) .
另外在制作串行104的工艺中，更包括在多层叠层结构10中形成多个源极接触结构107。其中，这些源极接触结构107是沿X轴方向排列设置，使这些串行104分别被夹设于相邻两源极接触结构107之间(请参照图1C)。In addition, in the process of manufacturing the strings 104 , it further includes forming a plurality of source contact structures 107 in the multilayer stack structure 10 . Wherein, the source contact structures 107 are arranged along the X-axis direction, so that the strings 104 are sandwiched between two adjacent source contact structures 107 (please refer to FIG. 1C ).
在本实施例中，源极接触结构107的形成方式，是在形成开口105的同时，以刻蚀工艺在硅导电层102、112、122、132和142和绝缘层103形成多个沿着Y轴方向延伸的条状开口108，以暴露出一部份基板101。之后，再于条状开口的侧壁上形成介电材质层107a，并以导电材料107b，例如多晶硅，填满条状开口108，以形成多个沿着Y轴方向延伸的条状源极接触结构107。In this embodiment, the source contact structure 107 is formed by forming the opening 105 and forming multiple layers along the Y The strip-shaped opening 108 extending in the axial direction exposes a part of the substrate 101 . After that, a dielectric material layer 107a is formed on the sidewall of the strip-shaped opening, and the strip-shaped opening 108 is filled with a conductive material 107b, such as polysilicon, to form a plurality of strip-shaped source contacts extending along the Y-axis direction. structure107.
接着，图案化最上层的含硅导电层102，以在含硅导电层102中形成多条串行选择线106，并使这些串行选择线106沿X轴方向延伸。请参照图1D和图1E，图1D是绘示在第1B的结构上形成多条串行选择线106之后的部分结构透视图。图1E是根据图1D所绘示的结构上视图。在本发明的一些实施例中，图案化最上层的含硅导电层102的步骤，包括在含硅导电层102上形成多条浅沟111，藉以将最上层的含硅导电层102区隔成多个条带，进而定义出多条串行选择线106。Next, pattern the uppermost silicon-containing conductive layer 102 to form a plurality of serial selection lines 106 in the silicon-containing conductive layer 102 , and make these serial selection lines 106 extend along the X-axis direction. Please refer to FIG. 1D and FIG. 1E . FIG. 1D is a perspective view of a partial structure after forming a plurality of serial selection lines 106 on the structure of 1B. FIG. 1E is a top view of the structure shown in FIG. 1D . In some embodiments of the present invention, the step of patterning the uppermost silicon-containing conductive layer 102 includes forming a plurality of shallow trenches 111 on the silicon-containing conductive layer 102, so as to separate the uppermost silicon-containing conductive layer 102 into A plurality of strips further define a plurality of serial selection lines 106 .
其中，每一条串行选择线106对应一部分的这些条串行104，并且于这对应的串行104电性连结。例如，在本发明的一些实施例之中，串行104可以是以矩阵阵列方式排列，而每一条串行选择线106可以对应5到10排串行104，并与这5到10排串行104电性连结。在本发明的一些实施例之中，串行104可以是以蜂巢状阵列方式排列，每一条串行选择线106则对应4到20排串行104，并与这4到20排串行104电性连结。Wherein, each string selection line 106 corresponds to a part of the strings 104 and is electrically connected to the corresponding strings 104 . For example, in some embodiments of the present invention, the strings 104 can be arranged in a matrix array, and each string selection line 106 can correspond to 5 to 10 rows of strings 104, and can be connected with these 5 to 10 rows of strings. 104 is electrically connected. In some embodiments of the present invention, the strings 104 can be arranged in a honeycomb array, and each string selection line 106 corresponds to 4 to 20 rows of strings 104, and is electrically connected to the 4 to 20 rows of strings 104. sexual connection.
而在本实施例之中，串行104是以蜂巢状阵列方式排列，每一条串行选择线106则对应4排串行104，并与这4排串行104电性连结。通过同一条串行选择线106，可以将这4排串行选择线106所对应的串行104的存储单元同时读取，进而可提高操作速度。再加上，串行104并不采用金属栅极，因此不需在串行选择线106之间预留刻蚀沟道所需的空间，可使串行选择线106的频带宽度因此(bandwidth)扩大。不仅可增加垂直通道式三维NAND闪存元件100的储存容量，亦可使垂直通道式三维NAND闪存元件100的整体功率消耗(power consumption)下降，进而减少读取存储单元时相邻存储单元之间的干扰。In this embodiment, the strings 104 are arranged in a honeycomb array, and each string selection line 106 corresponds to 4 rows of strings 104 and is electrically connected to these 4 rows of strings 104 . Through the same serial selection line 106, the memory cells of the serial lines 104 corresponding to the four rows of serial selection lines 106 can be read simultaneously, thereby increasing the operation speed. In addition, the series 104 does not use metal gates, so there is no need to reserve the space required for etching channels between the series selection lines 106, so that the bandwidth of the series selection lines 106 can be thus (bandwidth) expand. Not only can the storage capacity of the vertical channel type three-dimensional NAND flash memory element 100 be increased, but also the overall power consumption (power consumption) of the vertical channel type three-dimensional NAND flash memory element 100 can be reduced, thereby reducing the distance between adjacent memory cells when reading the memory cells. interference.
后续。在多层叠层结构10中形成多组多层插塞结构110，沿X轴方向排列设置，将多个串行104分别夹设于相邻两多层插塞结构110之间。另外，在形成多层插塞结构110的同时，一般也会在每一条串行选择线106上形成一个接触插塞114。请参照图1F和图1G，图1F是绘示在图1D所的结构上形成多组多层插塞结构110和接触插塞114之后的部分结构透视图。图1G是根据图1F所绘示的结构上视图。Follow up. Multiple groups of multi-layer plug structures 110 are formed in the multi-layer stack structure 10 , arranged along the X-axis direction, and a plurality of series 104 are sandwiched between two adjacent multi-layer plug structures 110 . In addition, when the multilayer plug structure 110 is formed, a contact plug 114 is generally formed on each serial selection line 106 . Please refer to FIG. 1F and FIG. 1G . FIG. 1F is a perspective view of a partial structure after forming multiple sets of multilayer plug structures 110 and contact plugs 114 on the structure shown in FIG. 1D . FIG. 1G is a top view of the structure shown in FIG. 1F .
在本实施例之中，每一个多层插塞结构110包含多个介层插塞，例如110a、110b、110c和110d；且每一个介层插塞110a、110b、110c和110d与含硅导电层112、122、132和142的其中一者对应导通。其中，介层插塞110a和含硅导电层112对应导通；介层插塞110b和含硅导电层122对应导通；介层插塞110c和含硅导电层132对应导通；以及介层插塞110d和含硅导电层142对应导通。同一组多层插塞结构110的插塞110a、110b、110c和110d，是沿Y轴方向排列，而形成一个平行Y轴方向的直线阶梯状(staircase)结构。但直线阶梯状结构并不以此为限，在本发明的另一个实施例之中，同一组多层插塞结构110的插塞110a、110b、110c和110d，可分成多组，例如2组，沿Y轴方向排列，而形成二个平行Y轴方向的直线阶梯状结构(如图3所绘示)。In this embodiment, each multilayer plug structure 110 includes a plurality of via plugs, such as 110a, 110b, 110c, and 110d; One of the layers 112 , 122 , 132 and 142 is correspondingly turned on. Wherein, the via plug 110a is correspondingly connected to the silicon-containing conductive layer 112; the via layer plug 110b is correspondingly connected to the silicon-containing conductive layer 122; the via layer plug 110c is correspondingly connected to the silicon-containing conductive layer 132; The plug 110d is correspondingly connected to the silicon-containing conductive layer 142 . The plugs 110 a , 110 b , 110 c and 110 d of the same group of multi-layer plug structures 110 are arranged along the Y-axis direction to form a linear staircase structure parallel to the Y-axis direction. But the linear stepped structure is not limited to this. In another embodiment of the present invention, the plugs 110a, 110b, 110c and 110d of the same group of multilayer plug structures 110 can be divided into multiple groups, for example, 2 groups , arranged along the Y-axis direction to form two linear ladder-like structures parallel to the Y-axis direction (as shown in FIG. 3 ).
值得注意的是，两相邻多层插塞结构110之间的距离D1的决定方式，是参考位于两相邻多层插塞结构110之间含硅导电层112、122、132和142的整体电阻值，以及考虑垂直通道式三维NAND闪存元件100的操作效能。在本发明的一些实施例中，两相邻的多层插塞结构110之间的距离D1，可以实质介于500微米至50微米之间。较佳则可以实质为100微米。It should be noted that the distance D1 between two adjacent multilayer plug structures 110 is determined by referring to the overall silicon-containing conductive layers 112 , 122 , 132 and 142 between two adjacent multilayer plug structures 110 . The resistance value, and consider the operation performance of the vertical channel type 3D NAND flash memory device 100 . In some embodiments of the present invention, the distance D1 between two adjacent multilayer plug structures 110 may be substantially between 500 μm and 50 μm. Preferably, it may be substantially 100 microns.
另外，两相邻源极接触结构107之间的距离D2的决定方式，也是参考位于两相邻源极接触结构107之间基板101(接地层)的整体电阻值，以及垂直通道式三维NAND闪存元件100的操作效能。在本发明的一些实施例之中，相邻两源极接触结构107之间的距离可以实质大于等于20微米(μm)。In addition, the determination method of the distance D2 between two adjacent source contact structures 107 also refers to the overall resistance value of the substrate 101 (ground layer) between the two adjacent source contact structures 107, and the vertical channel three-dimensional NAND flash memory The operating performance of the device 100. In some embodiments of the present invention, the distance between two adjacent source contact structures 107 may be substantially greater than or equal to 20 micrometers (μm).
而值得注意的是，虽然在前述实施例中(为了简单说明起见)将两相邻的源极接触结构107之间的距离以及两相邻的多层插塞结构110之间的距离绘示为大致相同。亦即是说，一个源极接触结构107对应搭配一组多层插塞结构110。但源极接触结构107和多层插塞结构110的配置并不以此为限定。在本发明的其他实施例之中，两相邻的源极接触结构107之间的距离以及两相邻的多层插塞结构110之间的距离可以不同。换言之，两相邻多层插塞结构110之间可以包含更多源极接触结构107。后续，于源极接触结构107上方形成多条源极线118，使源极线118沿Y轴方向延伸，并且与源极接触结构107电性连接。并在串行选择线106上方形成多条位线116，使每一条位线116沿Y轴方向延伸，并和同一条串行选择线106中的一串行104对应电性连接。请参照图1H，图1H是绘示在图1G的结构上形成多条源极线118和位线116之后的结构上视图。在本实施例之中，源极线118和位线116平行，且二者与串行选择线106直交。It should be noted that, although in the foregoing embodiments (for the sake of simple description), the distance between two adjacent source contact structures 107 and the distance between two adjacent multilayer plug structures 110 are shown as Much the same. That is to say, one source contact structure 107 corresponds to a set of multilayer plug structures 110 . However, the configuration of the source contact structure 107 and the multilayer plug structure 110 is not limited thereto. In other embodiments of the present invention, the distance between two adjacent source contact structures 107 and the distance between two adjacent multilayer plug structures 110 may be different. In other words, more source contact structures 107 may be included between two adjacent multilayer plug structures 110 . Subsequently, a plurality of source lines 118 are formed on the source contact structure 107 such that the source lines 118 extend along the Y-axis direction and are electrically connected to the source contact structure 107 . A plurality of bit lines 116 are formed above the string selection line 106 , so that each bit line 116 extends along the Y-axis direction and is electrically connected to a string 104 in the same string selection line 106 . Please refer to FIG. 1H , which is a top view of the structure after forming a plurality of source lines 118 and bit lines 116 on the structure of FIG. 1G . In this embodiment, the source line 118 is parallel to the bit line 116 , and they are perpendicular to the string selection line 106 .
在本发明的一些实施例中，源极线118和位线116可以形成于相同或不同的金属内联机层M1中。例如请参照图4A和图4B，图4A是沿着图1H所绘示的切线S1所绘示的部分结构剖面图；图4B是沿着图1H所绘示的切线S2所绘示的部分结构剖面图。在本实施例之中，源极线118和位线116是形成于相同的金属层内联机层M1中。每一条位线116则是通过位于串行104与金属内联机层M1之间的导孔119，与一条对应的串行104电性连接。In some embodiments of the present invention, source line 118 and bit line 116 may be formed in the same or different metal interconnect layer M1. For example, please refer to FIG. 4A and FIG. 4B. FIG. 4A is a partial structural cross-sectional view along the tangent line S1 shown in FIG. 1H; FIG. 4B is a partial structure along the tangent line S2 shown in FIG. 1H Sectional view. In this embodiment, the source line 118 and the bit line 116 are formed in the same metal interconnection layer M1. Each bit line 116 is electrically connected to a corresponding string 104 through a via 119 between the string 104 and the metal interconnect layer M1.
另外值得注意的是，虽然在前述的实施例中，皆是以基板101作为接地层(grounding layer)，使串行104的源极115通过基板101和源极接触结构107而与源极线118电性连接。但垂直通道式三维NAND闪存元件100的接地层结构并不以此为限。请参照图5，图5是根据本发明的另一实施例所绘示的接地层301、源极接触结构107与源极线118的部分结构剖面示意图。It is also worth noting that although in the aforementioned embodiments, the substrate 101 is used as the grounding layer, the source 115 of the string 104 is connected to the source line 118 through the substrate 101 and the source contact structure 107 electrical connection. However, the ground layer structure of the vertical channel type three-dimensional NAND flash memory device 100 is not limited thereto. Please refer to FIG. 5 . FIG. 5 is a schematic cross-sectional view of a partial structure of the ground layer 301 , the source contact structure 107 and the source line 118 according to another embodiment of the present invention.
在本实施例中，图5的结构与图4B的结构类似，差别在于接地层301，可以是位于基板101和含硅导电层142之间的另一个导电材质层。串行104的源极115是通过接地层301、源极接触结构107而与源极线118电性连接。其中，基板101和接地层301之间，以及接地层301和含硅导电层142之间，分别以一绝缘层303加以隔离。In this embodiment, the structure in FIG. 5 is similar to the structure in FIG. 4B , except that the ground layer 301 may be another conductive material layer between the substrate 101 and the silicon-containing conductive layer 142 . The source 115 of the string 104 is electrically connected to the source line 118 through the ground layer 301 and the source contact structure 107 . Wherein, between the substrate 101 and the ground layer 301 , and between the ground layer 301 and the silicon-containing conductive layer 142 are respectively separated by an insulating layer 303 .
接着，再于多层插塞结构110、位线116和源极线118上方形成多条金属字线117a、117b、117c和117d，沿X轴方向延伸，并使每一条金属字线117a、117b、117c或117d与导通同一个含硅导电层112、122、132或142的多个介层插塞110a、110b、110c或110d电性连接。另外，在形成金属字线117a、117b、117c和117d的同时，一般也会形成串接金属线113，用来与连接串行选择线106的接触插塞114电性连接。Next, a plurality of metal word lines 117a, 117b, 117c, and 117d are formed above the multilayer plug structure 110, the bit line 116, and the source line 118, extending along the X-axis direction, and each metal word line 117a, 117b , 117c or 117d are electrically connected to a plurality of via plugs 110a, 110b, 110c or 110d that are connected to the same silicon-containing conductive layer 112 , 122 , 132 or 142 . In addition, while forming the metal word lines 117 a , 117 b , 117 c and 117 d , the series metal lines 113 are generally formed to be electrically connected to the contact plugs 114 connected to the series selection lines 106 .
例如请参照图1I，图1I是绘示在图1H的结构上形成多条金属字线117a、117b、117c和117d以及串接金属线113之后的结构上视图。在本实施例之中，金属字线117a与位于不同组多层插塞结构110中，且同时导通含硅导电层112的多个介层插塞110a电性连接；金属字线117b与位于不同组多层插塞结构110中，且同时导通含硅导电层122的多个介层插塞110b电性连接；金属字线117c与位于不同组多层插塞结构110中，且同时导通含硅导电层132的多个介层插塞110c电性连接；金属字线117c与位于不同组多层插塞结构110中，且同时导通含硅导电层132的多个介层插塞110c电性连接。For example, please refer to FIG. 1I . FIG. 1I is a top view of the structure after forming a plurality of metal word lines 117 a , 117 b , 117 c and 117 d and a serial metal line 113 on the structure of FIG. 1H . In this embodiment, the metal word line 117a is electrically connected to a plurality of via plugs 110a located in different sets of multilayer plug structures 110 and simultaneously conducting the silicon-containing conductive layer 112; In different sets of multi-layer plug structures 110, multiple interposer plugs 110b that simultaneously conduct the silicon-containing conductive layer 122 are electrically connected; metal word lines 117c are located in different sets of multi-layer plug structures 110 and are simultaneously conducted A plurality of via plugs 110c passing through the silicon-containing conductive layer 132 are electrically connected; the metal word line 117c is located in a different group of multi-layer plug structures 110 and is simultaneously connected to a plurality of via plugs containing the silicon-containing conductive layer 132 110c is electrically connected.
而同一组多层插塞结构110的插塞110a、110b、110c和110d，则是按照直线阶梯状结构高低顺序排列，而与按照位置顺序排列的金属字线117a、117b、117c和117d彼此对应并电性连接。例如在本实施例之中，插塞110a对应并电性连接金属字线117a；插塞110b对应并电性连接金属字线117b；插塞110c对应并电性连接金属字线117c；插塞110d对应并电性连接金属字线117d。换言之，同一组多层插塞结构110的插塞110a、110b、110c和110d的配置，必须配合金属字线117a、117b、117c和117d的位置而定。在本发明的一些实施例中，金属字线117a、117b、117c和117d之间的间距彼此相等。因此同一组多层插塞结构110中插塞110a、110b、110c和110d的配置可以是等距配置。The plugs 110a, 110b, 110c, and 110d of the same group of multilayer plug structures 110 are arranged in the order of height of the linear ladder structure, and correspond to the metal word lines 117a, 117b, 117c, and 117d arranged in the order of position. and electrically connected. For example, in this embodiment, the plug 110a corresponds to and is electrically connected to the metal word line 117a; the plug 110b corresponds to and is electrically connected to the metal word line 117b; the plug 110c corresponds to and is electrically connected to the metal word line 117c; the plug 110d It corresponds to and is electrically connected to the metal word line 117d. In other words, the configuration of the plugs 110a, 110b, 110c and 110d of the same group of multilayer plug structures 110 must be determined according to the positions of the metal word lines 117a, 117b, 117c and 117d. In some embodiments of the present invention, the pitches between the metal word lines 117a, 117b, 117c and 117d are equal to each other. Therefore, the configuration of the plugs 110 a , 110 b , 110 c and 110 d in the same set of multilayer plug structures 110 may be an equidistant configuration.
但，在本发明的另一些实施例之中，同一组多层插塞结构110中插塞110a、110b、110c和110d的配置可以是不等距配置。请参照图6A和图6B，图6A是沿着图1I所绘示的切线S3所绘示的部分结构剖面图；图6B是沿着图1I所绘示的切线S4所绘示的部分结构剖面图。在本实施例之中，由于金属字线117a、117b、117c和117d是与连接接触插塞114的串接金属线113形成在相同的金属内联机层M2中，并且具有相同的延伸方向。换句话说，串接金属线113是穿插排列于金属字线117a、117b、117c和117d之间。However, in some other embodiments of the present invention, the arrangement of the plugs 110 a , 110 b , 110 c and 110 d in the same group of multilayer plug structures 110 may be not equidistant. Please refer to FIG. 6A and FIG. 6B. FIG. 6A is a partial structural cross-sectional view along the tangent line S3 shown in FIG. 1I; FIG. 6B is a partial structural cross-sectional view along the tangent line S4 shown in FIG. 1I picture. In this embodiment, since the metal word lines 117 a , 117 b , 117 c and 117 d are formed in the same metal interconnection layer M2 as the serial metal line 113 connected to the contact plug 114 , and have the same extending direction. In other words, the serial metal lines 113 are interspersed between the metal word lines 117a, 117b, 117c and 117d.
因此，为了避免插塞110a、110b、110c和110d与串接金属线113产生非必要的电性连结，在本实施例之中，同一组多层插塞结构110的插塞110b和110c之间的距离P2会较同一组多层插塞结构110的插塞110a和110b之间的距离P2或插塞110c和110d之间的距离P3长。其中，距离P3和P3可以相等。Therefore, in order to avoid unnecessary electrical connections between the plugs 110a, 110b, 110c, and 110d and the serial metal lines 113, in this embodiment, between the plugs 110b and 110c of the same group of multilayer plug structures 110 The distance P2 is longer than the distance P2 between the plugs 110a and 110b or the distance P3 between the plugs 110c and 110d of the same group of multilayer plug structures 110 . Wherein, the distances P3 and P3 may be equal.
在本发明的一些实施例之中，而同一组多层插塞结构110中插塞110a、110b、110c和110d的配置中，至少会有N个不相等的距离。其中N等于与同一组多层插塞结构110的插塞110a、110b、110c和110d交互排列的串接金属线113(或等于串行选择线106)的数量。后续再进行多个后段工艺(未绘示)，即完成垂直通道式三维NAND闪存元件100的制备(以图1I来表示)。由于，在本发明的实施例中，垂直通道式三维NAND闪存元件100是采用含硅导电层112、122、132和142作为栅极；并通过多层插塞结构110和金属字线117a、117b、117c和117的设置，降低含硅导电层112、122、132和142的栅极的整体电阻值，甚至达到与金属栅极相同的阻值，可减少栅极电阻与电容所造成的信号传递延迟现象。因此，采用本发明所提供的垂直通道式三维NAND闪存元件100，可以避免金属栅极工艺，因过镀刻蚀或残留牺牲层而对垂直通道式三维NAND闪存元件100所造成的不良影响。再加上，垂直通道式三维NAND闪存元件100的制作过程中并不需要在多层叠层结构10中形成用来刻蚀牺牲层的沟道。因此，可以减少两相邻串行选择线106之间的距离，进一步扩大串行选择线106的频带宽度，增加可容纳串行104的数量，扩大存储器空间容量。In some embodiments of the present invention, there are at least N unequal distances among the configurations of the plugs 110 a , 110 b , 110 c and 110 d in the same set of multilayer plug structures 110 . Where N is equal to the number of serial metal lines 113 (or equivalent to serial selection lines 106 ) that are alternately arranged with the plugs 110 a , 110 b , 110 c and 110 d of the same group of multilayer plug structures 110 . A number of back-end processes (not shown) are subsequently performed to complete the preparation of the vertical channel type three-dimensional NAND flash memory element 100 (shown in FIG. 1I ). Because, in an embodiment of the present invention, the vertical channel type three-dimensional NAND flash memory element 100 uses silicon-containing conductive layers 112, 122, 132 and 142 as gates; The settings of , 117c and 117 reduce the overall resistance value of the gates of the silicon-containing conductive layers 112, 122, 132 and 142, and even reach the same resistance value as the metal gate, which can reduce the signal transmission caused by gate resistance and capacitance Delay phenomenon. Therefore, the use of the vertical channel three-dimensional NAND flash memory device 100 provided by the present invention can avoid the adverse effects of the metal gate process on the vertical channel three-dimensional NAND flash memory device 100 due to overplating etching or residual sacrificial layer. In addition, during the manufacturing process of the vertical channel type three-dimensional NAND flash memory device 100 , it is not necessary to form a channel for etching the sacrificial layer in the multilayer stack structure 10 . Therefore, the distance between two adjacent string selection lines 106 can be reduced, the frequency bandwidth of the string selection lines 106 can be further expanded, the number of strings 104 that can be accommodated can be increased, and the capacity of the memory space can be expanded.
请参照图7，图7是根据本发明的另一实施例所绘示的三维存储器元件200的部分结构上视图。三维存储器元件200的结构垂直通道式三维NAND闪存元件100相似，差别仅在于三维存储器元件200具有数量更多的多层插塞结构110和源极接触结构107。巨观而言，多层插塞结构110与每一条沿着X方向延伸的串行选择线106相互重叠，而将每一条串行选择线106区隔成多个区域A。在本实施例中，多层插塞结构110将每一条串行选择线106区隔成至少10个区域A。其中，每一个区域A上配置一个接触插塞114，分别经由一条串接金属线113电性连结至译码器(未绘示)中。Please refer to FIG. 7 , which is a partial structural top view of a three-dimensional memory device 200 according to another embodiment of the present invention. The structure of the three-dimensional memory element 200 is similar to that of the vertical channel three-dimensional NAND flash memory element 100 , the only difference is that the three-dimensional memory element 200 has more multilayer plug structures 110 and source contact structures 107 . Macroscopically, the multilayer plug structure 110 overlaps with each serial selection line 106 extending along the X direction, and divides each serial selection line 106 into a plurality of regions A. Referring to FIG. In this embodiment, the multilayer plug structure 110 divides each serial selection line 106 into at least 10 regions A. Referring to FIG. Wherein, a contact plug 114 is disposed on each area A, and is electrically connected to a decoder (not shown) through a serial metal line 113 respectively.
为了清楚描述起见，图5省略部分元件，例如金属字线117a、117b、117c和117d、源极线118，而未加以绘示。该领域中具有通常知识者，当能由前述说明内容并参照相关图式，了解三维存储器元件200的配置。For the sake of clarity, some components are omitted in FIG. 5 , such as the metal word lines 117 a , 117 b , 117 c and 117 d and the source line 118 , and are not shown. Those skilled in the art should be able to understand the configuration of the three-dimensional memory element 200 from the foregoing description and with reference to related drawings.
根据上述实施例，本发明是在提供一种存储器元件及其制作方法。其是在三维存储器元件的多层叠层结构中形成多组沿着串行选择线平行排列设置的多层插塞结构，将形成于多层叠层结构中的多条串行分别夹设于两相邻的多层插塞结构之间，并且使多层插塞结构所包含的每一个介层插塞，分别与多层叠层结构中的一个含硅导电层对应导通。并以金属字线将导通同一含硅导电层的多个介层插塞电性连接。通过多层插塞结构和金属字线的连接，来降低三维存储器元件中栅极层的整体电阻率，以减少栅极电阻与电容所造成的信号传递延迟现象。又由于三维存储器元件是采用含硅导电材质作为栅极，不需额外形成金属栅极，可扩大串行选择线的频带宽度，解决已知技术，因为使用金属栅极工艺所导致的储存容量与工艺良率无法提高的问题。According to the above-mentioned embodiments, the present invention provides a memory device and a manufacturing method thereof. It is to form multiple groups of multi-layer plug structures arranged in parallel along the serial selection lines in the multi-layer stacked structure of the three-dimensional memory element, and sandwich the multiple serial lines formed in the multi-layer stacked structure between two phases respectively. Between the adjacent multilayer plug structures, and make each via plug included in the multilayer plug structure respectively conduct with a silicon-containing conductive layer in the multilayer stack structure. The metal word lines are used to electrically connect multiple interlayer plugs that are connected to the same silicon-containing conductive layer. The overall resistivity of the gate layer in the three-dimensional memory element is reduced through the connection of the multi-layer plug structure and the metal word line, so as to reduce the signal transmission delay phenomenon caused by the gate resistance and capacitance. And because the three-dimensional memory element uses silicon-containing conductive material as the gate, it does not need to form an additional metal gate, which can expand the frequency bandwidth of the serial selection line and solve the known technology, because the storage capacity caused by the use of the metal gate process is different from that of The problem that the process yield cannot be improved.
在本发明的一些实施例中，还包括在三维存储器元件的多层叠层结构中形成多个源极接触结构，平行串行选择线的延伸方向排列设置，将形成于多层叠层结构中的多条串行分别夹设于两相邻的源极接触插塞之间，并且垂直沿伸穿过多层叠层结构而与基板电性连接。通过源极接触结构的设置，亦可达到降低三维存储器元件中源极的整体电阻率，以减少源极电阻与电容所造成的信号传递延迟现象。In some embodiments of the present invention, it also includes forming a plurality of source contact structures in the multilayer stacked structure of the three-dimensional memory element. The bar series are respectively sandwiched between two adjacent source contact plugs, and extend vertically through the multilayer stack structure to be electrically connected to the substrate. Through the configuration of the source contact structure, the overall resistivity of the source in the three-dimensional memory element can also be reduced, so as to reduce the signal transmission delay phenomenon caused by the source resistance and capacitance.
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视随附的权利要求范围所界定的为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.
| Application Number | Priority Date | Filing Date | Title |
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| CN201510042457.3ACN105990354B (en) | 2015-01-28 | 2015-01-28 | Memory element and method of making the same |
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| CN201510042457.3ACN105990354B (en) | 2015-01-28 | 2015-01-28 | Memory element and method of making the same |
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| CN105990354Atrue CN105990354A (en) | 2016-10-05 |
| CN105990354B CN105990354B (en) | 2019-05-31 |
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| CN201510042457.3AActiveCN105990354B (en) | 2015-01-28 | 2015-01-28 | Memory element and method of making the same |
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