技术领域technical field
本发明涉及显示技术领域，尤指一种阵列基板、其制作方法、触控显示面板及显示装置。The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, a touch display panel and a display device.
背景技术Background technique
目前，为了使观看者有更好的视觉享受，窄边框显示产品是目前的流行趋势，随着移动产品的快速发展，显示产品的边框越来越窄，“无边框”已经成为智能手机行业的下一个发展趋势。At present, in order to provide viewers with better visual enjoyment, display products with narrow bezels are the current popular trend. With the rapid development of mobile products, the bezels of display products are getting narrower and narrower. "Borderless" has become a trend in the smartphone industry. The next development trend.
现有技术中栅极驱动电路一般通过阵列工艺形成在显示面板的阵列基板上，即阵列基板行驱动(Gate Driver on Array,GOA)工艺，这种集成工艺不仅节省了成本，而且可以做到显示面板两边对称的美观设计，同时，也省去了栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)的布线空间，从而可以实现窄边框的设计。例如，在阵列基板上设置有交叉而置且相互绝缘的多条栅线和多条数据线，为各栅线依次加载栅极扫描信号的栅极驱动电路位于阵列基板的左右两个边框区域内，将各数据线与源极驱动电路电性连接的数据线引脚位于阵列基板的下边框区域内。然而集成在阵列基板上的栅极驱动电路仍然会占据一定的宽度，制约显示面板超窄边框甚至无边框的发展。In the prior art, the gate driver circuit is generally formed on the array substrate of the display panel through an array process, that is, the Gate Driver on Array (GOA) process of the array substrate. This integrated process not only saves costs, but also can achieve display The symmetrical and beautiful design on both sides of the panel also saves the bonding area of the IC (Integrated Circuit) and the wiring space of the fan-out, so that the narrow border design can be realized. For example, a plurality of gate lines and a plurality of data lines intersecting and insulated from each other are arranged on the array substrate, and the gate driving circuit for sequentially loading gate scanning signals for each gate line is located in the left and right frame areas of the array substrate. , the data line pins electrically connecting each data line to the source driving circuit are located in the lower frame area of the array substrate. However, the gate drive circuit integrated on the array substrate still occupies a certain width, which restricts the development of ultra-narrow bezels or even bezel-less display panels.
因此，如何进一步减小显示面板的边框宽度，是本领域技术人员亟待解决的技术问题。Therefore, how to further reduce the frame width of the display panel is a technical problem to be solved urgently by those skilled in the art.
发明内容Contents of the invention
有鉴于此，本发明实施例提供一种阵列基板、其制作方法、触控显示面板及显示装置，可以大幅提高屏占比，实现三边的极窄边框甚至无边框。In view of this, embodiments of the present invention provide an array substrate, a manufacturing method thereof, a touch display panel, and a display device, which can greatly increase the screen-to-body ratio and realize extremely narrow borders or even no borders on three sides.
因此，本发明实施例提供了一种阵列基板，包括：衬底基板，设置在所述衬底基板上的交叉而置且相互绝缘的多条栅线和多条数据线，以及位于所述阵列基板的一边框区域的源极驱动电路；所述源极驱动电路的各引脚与各所述数据线直接电性连接；还包括：Therefore, an embodiment of the present invention provides an array substrate, including: a base substrate, a plurality of gate lines and a plurality of data lines arranged on the base substrate and intersecting and insulated from each other, and a plurality of data lines located on the array substrate. A source drive circuit in a frame area of the substrate; each pin of the source drive circuit is directly electrically connected to each of the data lines; it also includes:
与所述源极驱动电路位于同一边框区域的栅极驱动电路，以及与各所述栅线一一对应且电性连接的金属走线；a gate drive circuit located in the same frame area as the source drive circuit, and a metal wiring that corresponds to and is electrically connected to each of the gate lines;
所述栅极驱动电路的各引脚与各所述金属走线直接电性连接。Each pin of the gate driving circuit is directly electrically connected to each metal wire.
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，所述金属走线位于所述栅线和所述数据线的下方；In a possible implementation manner, in the above-mentioned array substrate provided by the embodiment of the present invention, the metal wiring is located under the gate line and the data line;
各所述栅线通过过孔与对应的所述金属走线电性连接。Each of the gate lines is electrically connected to the corresponding metal wire through a via hole.
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，所述金属走线与所述数据线相互平行。In a possible implementation manner, in the above-mentioned array substrate provided by the embodiment of the present invention, the metal wiring and the data line are parallel to each other.
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，沿所述数据线的延伸方向，各所述过孔依次交错排布。In a possible implementation manner, in the above-mentioned array substrate provided by the embodiment of the present invention, along the extending direction of the data lines, the via holes are sequentially arranged in a staggered manner.
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，还包括：呈矩阵排列的多个像素单元；相邻两条所述栅线和相邻两条数据线限定一个像素单元；In a possible implementation manner, the above-mentioned array substrate provided by the embodiment of the present invention further includes: a plurality of pixel units arranged in a matrix; two adjacent gate lines and two adjacent data lines define a pixel unit;
所述金属走线设置在相邻的两列所述像素单元之间的间隙处。The metal wires are arranged in the gap between two adjacent columns of the pixel units.
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，还包括：呈矩阵排列的多个触控自电容电极，以及与每个所述触控自电容电极一一对应且电性连接的触控引线，各所述触控自电容电极通过对应的触控引线与触控芯片相连；所述触控芯片与所述源极驱动电路位于同一边框区域；In a possible implementation manner, the above-mentioned array substrate provided in the embodiment of the present invention further includes: a plurality of touch self-capacitance electrodes arranged in a matrix, and a one-to-one correspondence with each of the touch self-capacitance electrodes And electrically connected touch leads, each of the touch self-capacitance electrodes is connected to the touch chip through the corresponding touch lead; the touch chip and the source driver circuit are located in the same frame area;
所述触控自电容电极在显示阶段用作公共电极，在触控阶段用作触控自电容电极；The touch self-capacitance electrode is used as a common electrode in the display stage, and is used as a touch self-capacitance electrode in the touch stage;
所述触控引线用于在显示阶段向所述公共电极传递公共电极信号，在触控阶段向所述触控自电容电极传递触控扫描信号，且还用于将发生触控位置处的触控自电容电极产生的触控信号传输到触控芯片。The touch lead wire is used to transmit the common electrode signal to the common electrode in the display phase, transmit the touch scan signal to the touch self-capacitance electrode in the touch phase, and is also used to transmit the touch signal at the touch position. The touch signal generated by the control self-capacitance electrode is transmitted to the touch chip.
在一种可能的实现方式中，在本发明实施例提供的上述阵列基板中，所述触控引线设置在相邻的两列所述像素单元之间的间隙处。In a possible implementation manner, in the above-mentioned array substrate provided by the embodiment of the present invention, the touch wires are arranged in a gap between two adjacent columns of the pixel units.
本发明实施例还提供了一种本发明实施例提供的上述阵列基板的制作方法，包括：The embodiment of the present invention also provides a method for manufacturing the above-mentioned array substrate provided by the embodiment of the present invention, including:
在衬底基板上形成交叉而置且相互绝缘的多条栅线和多条数据线的图形，以及形成与各所述栅线一一对应且电性连接的金属走线的图形；Forming a pattern of a plurality of gate lines and a plurality of data lines intersecting and insulated from each other on the base substrate, and forming a pattern of metal wirings corresponding to each of the gate lines and electrically connected;
在所述阵列基板的一边框区域形成源极驱动电路和栅极驱动电路；所述源极驱动电路的各引脚与各所述数据线直接电性连接；所述栅极驱动电路的各引脚与各所述金属走线直接电性连接。A source drive circuit and a gate drive circuit are formed in a frame area of the array substrate; each pin of the source drive circuit is directly electrically connected to each of the data lines; each lead of the gate drive circuit The pins are directly electrically connected to each of the metal traces.
本发明实施例还提供了一种触控显示面板，包括本发明实施例提供的上述阵列基板。The embodiment of the present invention also provides a touch display panel, including the above-mentioned array substrate provided by the embodiment of the present invention.
本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述阵列基板或上述触控显示面板。An embodiment of the present invention also provides a display device, including the above-mentioned array substrate or the above-mentioned touch display panel provided by the embodiment of the present invention.
本发明实施例的有益效果包括：The beneficial effects of the embodiments of the present invention include:
本发明实施例提供的一种阵列基板、其制作方法、触控显示面板及显示装置，包括：衬底基板，设置在衬底基板上的交叉而置且相互绝缘的多条栅线和多条数据线，以及位于阵列基板的一边框区域的源极驱动电路；源极驱动电路的各引脚与各数据线直接电性连接；还包括：与源极驱动电路位于同一边框区域的栅极驱动电路，以及与各栅线一一对应且电性连接的金属走线；栅极驱动电路的各引脚与各金属走线直接电性连接。由于栅极驱动电路和源极驱动电路均位于阵列基板的同一边框区域内，栅极驱动电路通过金属走线依次向各栅线加载栅极扫描信号，源极驱动电路直接向各数据线加载灰阶信号，这样可以大幅提高屏占比，实现另外三边的极窄边框甚至无边框，让用户享受到前所未有的视觉体验和更加惊艳的视觉效果。An array substrate, a manufacturing method thereof, a touch display panel, and a display device provided by an embodiment of the present invention include: a base substrate, a plurality of intersecting and mutually insulated gate lines and a plurality of Data lines, and a source drive circuit located in a frame area of the array substrate; each pin of the source drive circuit is directly electrically connected to each data line; also includes: a gate drive located in the same frame area as the source drive circuit Circuits, and metal wires corresponding to and electrically connected to each gate line; each pin of the gate driving circuit is directly electrically connected to each metal wire. Since both the gate drive circuit and the source drive circuit are located in the same frame area of the array substrate, the gate drive circuit sequentially loads the gate scanning signal to each gate line through the metal wiring, and the source drive circuit directly loads the gray signal to each data line. This can greatly increase the screen-to-body ratio and achieve extremely narrow or even no borders on the other three sides, allowing users to enjoy an unprecedented visual experience and more stunning visual effects.
附图说明Description of drawings
图1为本发明实施例提供的阵列基板的示意图；FIG. 1 is a schematic diagram of an array substrate provided by an embodiment of the present invention;
图2为本发明实施例提供的具有金属走线的阵列基板的结构示意图；FIG. 2 is a schematic structural diagram of an array substrate with metal wiring provided by an embodiment of the present invention;
图3为本发明实施例提供的具有金属走线和触控走线的阵列基板的结构示意图；3 is a schematic structural diagram of an array substrate provided with metal traces and touch traces according to an embodiment of the present invention;
图4为本发明实施例提供的具有金属走线和触控走线的阵列基板的截面图；4 is a cross-sectional view of an array substrate provided with metal traces and touch traces according to an embodiment of the present invention;
图5为本发明实施例提供的阵列基板的制作方法流程图；FIG. 5 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present invention;
图6a至图6k分别为本发明实施例提供的阵列基板的制作方法在各步骤执行后的截面图。6a to 6k are respectively cross-sectional views of the fabrication method of the array substrate provided by the embodiment of the present invention after each step is performed.
具体实施方式detailed description
下面结合附图，对本发明实施例提供的阵列基板、其制作方法、触控显示面板及显示装置的具体实施方式进行详细地说明。The specific implementation manners of the array substrate, the manufacturing method thereof, the touch display panel and the display device provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
其中，附图中各膜层的厚度和形状不反映阵列基板的真实比例，目的只是示意说明本发明内容。Wherein, the thickness and shape of each film layer in the drawings do not reflect the real proportion of the array substrate, and the purpose is only to illustrate the content of the present invention.
本发明实施例提供了一种阵列基板，如图1所示，包括：衬底基板，设置在衬底基板上的交叉而置且相互绝缘的多条栅线1和多条数据线(图1中未示出)，以及位于阵列基板的一边框区域的源极驱动电路01；源极驱动电路的各引脚与各数据线直接电性连接；还包括：An embodiment of the present invention provides an array substrate, as shown in FIG. 1 , comprising: a base substrate, a plurality of gate lines 1 and a plurality of data lines ( FIG. 1 not shown in ), and a source drive circuit 01 located in a frame area of the array substrate; each pin of the source drive circuit is directly electrically connected to each data line; it also includes:
与源极驱动电路01位于同一边框区域的栅极驱动电路02，以及与各栅线1一一对应且电性连接的金属走线2；The gate drive circuit 02 located in the same frame area as the source drive circuit 01, and the metal traces 2 corresponding to each gate line 1 and electrically connected;
栅极驱动电路02的各引脚与各金属走线2直接电性连接。Each pin of the gate driving circuit 02 is directly electrically connected to each metal wire 2 .
需要说明的是，图1中示出了源极驱动电路01和栅极驱动电路02均位于阵列基板的下边框区域，对于源极驱动电路01和栅极驱动电路02均位于阵列基板的哪一边框区域，可以根据实际情况而定，在此不做限定。源极驱动电路01和栅极驱动电路02之间可以设置有多路复用选择器MUX_Unit，可以实现多路信号的同时传输，对于MUX_Unit的设置，可以根据实际情况而定，在此不做限定。It should be noted that, as shown in FIG. 1 , both the source driver circuit 01 and the gate driver circuit 02 are located in the lower frame area of the array substrate. The frame area may be determined according to actual conditions, and is not limited here. A multiplexing selector MUX_Unit can be set between the source drive circuit 01 and the gate drive circuit 02, which can realize simultaneous transmission of multiple signals. The setting of MUX_Unit can be determined according to the actual situation, and is not limited here. .
在本发明实施例提供的上述阵列基板中，由于栅极驱动电路和源极驱动电路均位于阵列基板的同一边框区域内，栅极驱动电路通过金属走线向各栅线依次加载栅极扫描信号，实现对栅线的逐行驱动，源极驱动电路直接向数据线加载灰阶信号，这样可以大幅提高屏占比，实现另外三边的极窄边框甚至无边框，让用户享受到前所未有的视觉体验和更加惊艳的视觉效果。In the above-mentioned array substrate provided by the embodiment of the present invention, since the gate drive circuit and the source drive circuit are located in the same frame area of the array substrate, the gate drive circuit sequentially loads the gate scan signal to each gate line through the metal wiring. , realize the row-by-row drive of the gate lines, and the source drive circuit directly loads gray-scale signals to the data lines, which can greatly increase the screen-to-body ratio and realize extremely narrow or even no borders on the other three sides, allowing users to enjoy unprecedented visual Experience and more stunning visual effects.
在具体实施时，在本发明实施例提供的上述阵列基板中，为了防止金属走线占用开口率，金属走线可以位于栅线和数据线的下方，这样可以不会对开口率造成影响；同时，为了最大限度的降低走线的电阻，如图1和图2所示，各栅线1通过过孔3仅与对应的金属走线2电性连接。In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, in order to prevent the metal wires from occupying the aperture ratio, the metal wires may be located under the gate lines and data lines, so that the aperture ratio may not be affected; at the same time , in order to minimize the resistance of the wiring, as shown in FIG. 1 and FIG. 2 , each gate line 1 is only electrically connected to the corresponding metal wiring 2 through the via hole 3 .
在具体实施时，在本发明实施例提供的上述阵列基板中，由于栅极驱动电路通过金属走线向各栅线依次加载栅极扫描信号，为了防止栅极扫描信号和数据线上加载的灰阶信号之间相互干扰，如图2所示，具体地，可以将金属走线2与数据线4设置为相互平行，当然，金属走线2和数据线4也可以交叉设置，但为了避免漏光，金属走线的材料须满足材料为透明导电材料，例如氧化铟锡、氧化铟锌等。对于金属走线的延伸方向，可以根据实际情况而定，在此不做限定。During specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, since the gate drive circuit sequentially loads the gate scan signal to each gate line through the metal wiring, in order to prevent the gate scan signal and the gray Interference between the second-order signals, as shown in Figure 2, specifically, the metal wiring 2 and the data line 4 can be set to be parallel to each other, of course, the metal wiring 2 and the data line 4 can also be arranged to cross, but in order to avoid light leakage , the material of the metal wiring must meet the requirement that the material is a transparent conductive material, such as indium tin oxide, indium zinc oxide, and the like. The extending direction of the metal traces may be determined according to actual conditions, and is not limited here.
在具体实施时，在本发明实施例提供的上述阵列基板中，为了简化制作工艺，如图2所示，沿数据线4的延伸方向，各金属走线2可以依次分别与对应的栅线1通过过孔3电性连接，即第一条金属走线2与第一条栅线1通过过孔3电性连接，第二条金属走线2与第二条栅线1通过过孔3电性连接，以此类推，此时，各过孔3依次交错排布。对于过孔的排布方式也可以为其它方式，可以根据实际情况而定，在此不做限定。In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, in order to simplify the manufacturing process, as shown in FIG. Electrically connected through the via hole 3, that is, the first metal trace 2 and the first grid line 1 are electrically connected through the via hole 3, and the second metal trace 2 and the second gate line 1 are electrically connected through the via hole 3. Sexual connection, and so on, at this time, the via holes 3 are arranged in a staggered order. The way of arranging the via holes can also be other ways, which can be determined according to the actual situation, and are not limited here.
在具体实施时，在本发明实施例提供的上述阵列基板中，如图2所示，阵列基板还包括：呈矩阵排列的多个像素单元(图2中示出了6*5个像素单元)；相邻两条栅线1和相邻两条数据线4限定一个像素单元；金属走线2设置在相邻的两列像素单元之间的间隙处，这样可以保证金属走线不会占用像素的开口率。此时金属走线的材料可以为透明导电材料，也可以为不透明导电材料，在此不做限定。In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, as shown in FIG. 2, the array substrate further includes: a plurality of pixel units arranged in a matrix (6*5 pixel units are shown in FIG. 2) ; Two adjacent gate lines 1 and two adjacent data lines 4 define a pixel unit; metal lines 2 are arranged in the gap between two adjacent columns of pixel units, which can ensure that the metal lines will not occupy pixels opening rate. At this time, the material of the metal wiring may be a transparent conductive material, or an opaque conductive material, which is not limited here.
需要说明的是，以图2为例，在栅线的数量等于数据线的数量时，由于金属走线的数量和栅线的数量相同，则金属走线的数量等于数据线的数量，此时只要在每相邻的两列像素单元之间的间隙处均设置一条金属走线即可；另外，在栅线的数量大于数据线的数量时，由于金属走线的数量和栅线的数量相同，则金属走线的数量大于数据线的数量，此时会出现相邻的两列像素单元之间的间隙处设置有多条金属走线的情况；在栅线的数量小于数据线的数量时，由于金属走线的数量和栅线的数量相同，则金属走线的数量小于数据线的数量，此时会出现相邻的两列像素单元之间的间隙处未设置有金属走线的情况。It should be noted that, taking FIG. 2 as an example, when the number of gate lines is equal to the number of data lines, since the number of metal lines is the same as the number of gate lines, the number of metal lines is equal to the number of data lines. As long as a metal wire is provided at the gap between every two adjacent columns of pixel units; in addition, when the number of gate lines is greater than the number of data lines, since the number of metal wires is the same as the number of gate lines , then the number of metal wires is greater than the number of data lines, and there will be multiple metal wires arranged in the gap between two adjacent columns of pixel units; when the number of gate lines is less than the number of data lines , since the number of metal wires is the same as the number of gate lines, the number of metal wires is smaller than the number of data lines. At this time, there will be no metal wires in the gap between two adjacent columns of pixel units. .
进一步地，在具体实施时，在本发明实施例提供的上述阵列基板中，为了使阵列基板在可以实现三边的极窄边框甚至无边框的基础上，还可以实现自电容触控，如图3和图4所示，阵列基板还包括：呈矩阵排列的多个触控自电容电极6，以及与每个触控自电容电极6一一对应且电性连接的触控引线5，各触控自电容电极6通过对应的触控引线5与触控芯片相连；该触控芯片与源极驱动电路可以位于同一边框区域；触控自电容电极6在显示阶段用作公共电极，在触控阶段用作触控自电容电极；触控引线5用于在显示阶段向公共电极传递公共电极信号，在触控阶段向触控自电容电极传递触控扫描信号，且还用于将发生触控位置处的触控自电容电极产生的触控信号传输到触控芯片。Furthermore, in specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, in order to enable the array substrate to realize a very narrow border or even no border on three sides, it can also realize self-capacitance touch, as shown in the figure 3 and 4, the array substrate further includes: a plurality of touch self-capacitance electrodes 6 arranged in a matrix, and touch leads 5 corresponding to and electrically connected to each touch self-capacitance electrode 6, each touch The control self-capacitance electrode 6 is connected to the touch chip through the corresponding touch lead 5; the touch chip and the source driver circuit can be located in the same frame area; the touch self-capacitance electrode 6 is used as a common electrode in the display stage, The stage is used as a touch self-capacitance electrode; the touch lead 5 is used to transmit the common electrode signal to the common electrode in the display stage, and to transmit the touch scan signal to the touch self-capacitance electrode in the touch stage, and is also used to generate a touch The touch signal at the position is transmitted from the touch signal generated by the capacitive electrode to the touch chip.
在具体实施时，在本发明实施例提供的上述阵列基板中，为了保证触控引线不会占用像素的开口率，如图3所示，触控引线5可以设置在相邻的两列像素单元之间的间隙处(图3中示出了6*2个像素单元)。触控引线也可以与数据线相互平行，同样，触控引线也可以设置在数据线的下方且与数据线相互绝缘。对于触控引线与数据线的位置关系，可以根据实际情况而定，在此不做限定。In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, in order to ensure that the touch wires do not occupy the aperture ratio of the pixels, as shown in FIG. at the gap between them (6*2 pixel units are shown in FIG. 3 ). The touch lead wires can also be parallel to the data lines, and similarly, the touch lead wires can also be arranged below the data lines and insulated from the data lines. The positional relationship between the touch lead wires and the data wires can be determined according to actual conditions, and is not limited here.
需要说明的是，以图3为例，在栅线的数量小于数据线的数量时，由于金属走线的数量和栅线的数量相同，则金属走线的数量小于数据线的数量，此时会出现相邻的两列像素单元之间的间隙处未设置有金属走线，而是设置有触控引线的情况，这样可以简化布线工艺，防止占用开口率；另外，在栅线的数量等于数据线的数量时，由于金属走线的数量和栅线的数量相同，则金属走线的数量等于数据线的数量，此时会出现相邻的两列像素单元之间的间隙处既设置有金属走线，有设置有触控引线的情况；在栅线的数量大于数据线的数量时，由于金属走线的数量和栅线的数量相同，则金属走线的数量大于数据线的数量，此时会出现相邻的两列像素单元之间的间隙处设置有多条金属走线和触控引线的情况。It should be noted that, taking FIG. 3 as an example, when the number of gate lines is less than the number of data lines, since the number of metal lines is the same as the number of gate lines, the number of metal lines is less than the number of data lines. There will be cases where there are no metal wires in the gap between two adjacent columns of pixel units, but touch wires, which can simplify the wiring process and prevent the occupation of the aperture ratio; in addition, when the number of gate lines is equal to For the number of data lines, since the number of metal lines is the same as the number of gate lines, the number of metal lines is equal to the number of data lines. Metal traces are provided with touch leads; when the number of gate lines is greater than the number of data lines, since the number of metal traces is the same as the number of gate lines, the number of metal traces is greater than the number of data lines, In this case, a plurality of metal traces and touch wires are arranged in the gap between two adjacent columns of pixel units.
需要说明的是，对于触控引线和金属走线的位置关系，在本发明实施例提供的上述阵列基板中，可以设置为触控引线与金属走线同层设置(也可以理解为同层同材质)，这样，在制备阵列基板时不需要增加额外的制备工序，只需要通过一次构图工艺即可形成触控引线与金属走线的图形，能够简化制作工艺，节省制备成本，提升产品附加值。It should be noted that, with regard to the positional relationship between the touch wires and the metal wires, in the above-mentioned array substrate provided by the embodiment of the present invention, it can be set that the touch wires and the metal wires are arranged on the same layer (also can be understood as the same layer and the same layer). Material), in this way, no additional preparation process is required when preparing the array substrate, and only one patterning process is required to form the graphics of the touch leads and metal traces, which can simplify the manufacturing process, save the preparation cost, and increase the added value of the product .
基于同一发明构思，本发明实施例还提供了一种本发明实施例提供的上述阵列基板的制作方法，由于该方法解决问题的原理与前述一种阵列基板相似，因此该方法的实施可以参见阵列基板的实施，重复之处不再赘述。Based on the same inventive concept, the embodiment of the present invention also provides a method for manufacturing the above-mentioned array substrate provided by the embodiment of the present invention. Since the problem-solving principle of this method is similar to that of the aforementioned array substrate, the implementation of this method can be found in the array The implementation of the substrate will not be described repeatedly.
在具体实施时，本发明实施例提供的阵列基板的制作方法，如图5所示，具体包括以下步骤：During specific implementation, the method for manufacturing an array substrate provided by the embodiment of the present invention, as shown in FIG. 5 , specifically includes the following steps:
S501、在衬底基板上形成交叉而置且相互绝缘的多条栅线和多条数据线的图形，以及形成与各栅线一一对应且电性连接的金属走线的图形；S501, forming a pattern of a plurality of gate lines and a plurality of data lines intersecting and insulated from each other on the base substrate, and forming a pattern of metal wirings corresponding to each gate line and electrically connected;
S502、在阵列基板的一边框区域形成源极驱动电路和栅极驱动电路；源极驱动电路的各引脚与各数据线直接电性连接；栅极驱动电路的各引脚与各金属走线直接电性连接。S502. Form a source driving circuit and a gate driving circuit in a frame area of the array substrate; each pin of the source driving circuit is directly electrically connected to each data line; each pin of the gate driving circuit is connected to each metal wiring direct electrical connection.
在本发明实施例提供的上述阵列基板的制作方法中，由于栅极驱动电路和源极驱动电路均形成在阵列基板的同一边框区域内，栅极驱动电路通过金属走线向各栅线依次加载栅极扫描信号，实现对栅线的逐行驱动，源极驱动电路直接向数据线加载灰阶信号，这样可以大幅提高屏占比，实现另外三边的极窄边框甚至无边框，让用户享受到前所未有的视觉体验和更加惊艳的视觉效果。In the method for manufacturing the above-mentioned array substrate provided by the embodiment of the present invention, since the gate drive circuit and the source drive circuit are both formed in the same frame area of the array substrate, the gate drive circuit sequentially loads The gate scanning signal realizes the progressive driving of the gate lines, and the source drive circuit directly loads grayscale signals to the data lines, which can greatly increase the screen ratio and realize the extremely narrow or even no border on the other three sides, allowing users to enjoy To an unprecedented visual experience and more stunning visual effects.
下面以一个具体的实例详细的说明本发明实施例提供的阵列基板的制作方法(以制作阵列基板的显示区域内的膜层结构为例)，具体步骤如下：The method for manufacturing the array substrate provided by the embodiment of the present invention will be described in detail below with a specific example (taking the film layer structure in the display area of the array substrate as an example), and the specific steps are as follows:
步骤一、在衬底基板上形成包括有金属走线、遮挡层和触控引线的图形；Step 1, forming a pattern including metal wiring, a shielding layer and a touch lead on the base substrate;
在具体实施时，如图6a所示，通过一次构图工艺，利用衬底基板10上的金属层形成包括有金属走线11、遮挡层12、触控引线13的图形；其中，遮挡层12是用于设置在待形成的栅极下方，防止光线照射到栅极上；In a specific implementation, as shown in FIG. 6a, through a patterning process, the metal layer on the base substrate 10 is used to form a pattern including metal traces 11, shielding layers 12, and touch leads 13; wherein, the shielding layer 12 is It is used to be arranged under the grid to be formed to prevent light from shining on the grid;
步骤二、在形成有金属走线、遮挡层和触控引线图形的衬底基板上形成缓冲层(buffer)；Step 2, forming a buffer layer (buffer) on the base substrate formed with metal wiring, shielding layer and touch lead pattern;
在具体实施时，如图6b所示，在形成有金属走线11、遮挡层12和触控引线13图形的衬底基板上沉积一层缓冲层14，此步骤不需要进行构图工艺；In a specific implementation, as shown in FIG. 6 b , a buffer layer 14 is deposited on the base substrate on which the patterns of the metal traces 11 , the shielding layer 12 and the touch leads 13 are formed. This step does not require a patterning process;
步骤三、在缓冲层上形成有源层的图形；Step 3, forming the pattern of the active layer on the buffer layer;
在具体实施时，如图6c所示，在缓冲层14上沉积一层有源层薄膜，通过一次构图工艺形成有源层15的图形；In a specific implementation, as shown in FIG. 6c, a layer of active layer film is deposited on the buffer layer 14, and the pattern of the active layer 15 is formed through a patterning process;
步骤四、在形成有有源层图形的衬底基板上形成栅极绝缘层、第一过孔和第二过孔的下部刻蚀部分的图形；Step 4, forming patterns of the gate insulating layer, the first via hole and the lower etched part of the second via hole on the base substrate formed with the pattern of the active layer;
在具体实施时，如图6d所示，在形成有有源层15图形的衬底基板11上沉积一层栅极绝缘层薄膜，通过一次构图工艺形成栅极绝缘层16的图形，在金属走线11上方对应的区域形成第一过孔的图形，以待形成的栅线与金属走线11电性连接，以及在触控引线13上方对应的区域形成第二过孔的下部刻蚀部分的图形，以待形成的触控自电容电极与触控引线13电性连接；In specific implementation, as shown in Figure 6d, a gate insulating layer thin film is deposited on the base substrate 11 with the pattern of the active layer 15, and the pattern of the gate insulating layer 16 is formed through a patterning process, and the pattern of the gate insulating layer 16 is formed on the metal trace. The pattern of the first via hole is formed in the corresponding area above the line 11, so that the gate line to be formed is electrically connected with the metal wiring 11, and the lower etched part of the second via hole is formed in the corresponding area above the touch lead 13. Graphics for electrically connecting the touch self-capacitance electrodes to be formed with the touch lead wires 13;
步骤五、在栅极绝缘层上形成包括有栅线和栅极的图形；Step 5, forming a pattern including a gate line and a gate on the gate insulating layer;
在具体实施时，如图6e所示，在栅极绝缘层16上沉积一层栅极金属层，通过一次构图工艺形成栅线17和栅极18的图形；其中，栅线17通过第一过孔与触控引线11电性连接；In specific implementation, as shown in FIG. 6e, a gate metal layer is deposited on the gate insulating layer 16, and the pattern of the gate line 17 and the gate 18 is formed through a patterning process; wherein, the gate line 17 is passed through the first pass The hole is electrically connected with the touch lead 11;
步骤六、在形成有栅线和栅极图形的衬底基板上形成第一钝化层、第二过孔和第三过孔的图形；Step 6, forming patterns of a first passivation layer, a second via hole and a third via hole on the base substrate on which the gate line and the gate pattern are formed;
在具体实施时，如图6f所示，在形成有栅线17和栅极18图形的衬底基板11上沉积一层钝化层薄膜，通过第一次构图工艺形成第一钝化层19的图形，在有源层15上方对应的区域形成第三过孔的图形，以待形成的源极、漏极与有源层15电性连接，以及在触控引线13上方对应的区域形成完整的第二过孔的图形；During specific implementation, as shown in FIG. 6f, a layer of passivation layer film is deposited on the base substrate 11 formed with gate lines 17 and gate 18 patterns, and the first passivation layer 19 is formed by the first patterning process. pattern, forming the pattern of the third via hole in the corresponding area above the active layer 15, so as to electrically connect the source electrode and the drain electrode to be formed with the active layer 15, and form a complete via hole in the corresponding area above the touch lead 13. The graphics of the second via;
步骤七、在第一钝化层上形成包括有源极、漏极和金属层的图形；Step 7, forming a pattern including a source electrode, a drain electrode and a metal layer on the first passivation layer;
在具体实施时，如图6g所示，在第一钝化层19上沉积一层源漏极金属层薄膜，通过一次构图工艺形成源极和漏极20的图形，以及用于连接待形成的触控自电容电极和触控引线的金属层21的图形；In specific implementation, as shown in Figure 6g, a layer of source and drain metal layer film is deposited on the first passivation layer 19, and the pattern of the source and drain electrodes 20 is formed through a patterning process, and is used to connect the to-be-formed The pattern of the metal layer 21 of the touch self-capacitance electrode and the touch lead;
步骤八、在形成有源极、漏极和金属层图形的衬底基板上形成第二钝化层的图形、第四过孔和第五过孔的图形；Step 8, forming the pattern of the second passivation layer, the pattern of the fourth via hole and the pattern of the fifth via hole on the base substrate formed with the pattern of the source electrode, the drain electrode and the metal layer;
在具体实施时，如图6h所示，在形成有源极、漏极20和金属层21图形的衬底基板11上沉积一层钝化层薄膜，通过一次构图工艺形成第二钝化层22的图形，在源极和漏极20上方对应的区域形成第四过孔的图形，以及在金属层21上方对应的区域形成第五过孔的图形；During specific implementation, as shown in FIG. 6h, a passivation layer film is deposited on the base substrate 11 formed with patterns of the source electrode, the drain electrode 20 and the metal layer 21, and the second passivation layer 22 is formed through a patterning process. The pattern of the fourth via hole is formed in the corresponding area above the source electrode and the drain electrode 20, and the pattern of the fifth via hole is formed in the corresponding area above the metal layer 21;
步骤九、在第二钝化层上形成触控自电容电极的图形；Step 9, forming a pattern of touch self-capacitance electrodes on the second passivation layer;
在具体实施时，如图6i所示，在第二钝化层的图形上沉积一层透明导电薄膜，通过一次构图工艺形成触控自电容电极23的图形；触控自电容电极23通过第五过孔和金属层21可以与触控引线13电性相连；触控自电容电极23在显示阶段用作公共电极，在触控阶段用作触控自电容电极；In specific implementation, as shown in Figure 6i, a layer of transparent conductive film is deposited on the pattern of the second passivation layer, and the pattern of the touch self-capacitance electrode 23 is formed through a patterning process; the touch self-capacitance electrode 23 passes through the fifth The via hole and the metal layer 21 can be electrically connected to the touch lead 13; the touch self-capacitance electrode 23 is used as a common electrode in the display phase, and is used as a touch self-capacitance electrode in the touch phase;
步骤十、在形成有触控自电容电极的衬底基板上形成第三钝化层的图形；Step 10, forming a pattern of a third passivation layer on the base substrate on which the touch self-capacitance electrodes are formed;
在具体实施时，如图6j所示，在形成有触控自电容电极23的衬底基板上沉积一层钝化层薄膜，通过一次构图工艺形成第三钝化层24的图形；During specific implementation, as shown in FIG. 6j , a passivation layer film is deposited on the base substrate on which the touch self-capacitance electrode 23 is formed, and the pattern of the third passivation layer 24 is formed through a patterning process;
步骤十一、在第三钝化层上形成像素电极的图形；Step eleven, forming the pattern of the pixel electrode on the third passivation layer;
在具体实施时，如图6k所示，在第三钝化层上沉积一层电极层，通过一次构图工艺形成像素电极25的图形；像素电极25通过第四过孔可以与漏极20电性相连。In specific implementation, as shown in FIG. 6k, an electrode layer is deposited on the third passivation layer, and the pattern of the pixel electrode 25 is formed through a patterning process; the pixel electrode 25 can be electrically connected to the drain electrode 20 through the fourth via hole. connected.
至此，经过具体实例提供的上述步骤一至步骤十一制作出了本发明实施例提供的上述阵列基板，本发明提供的制作工艺共进行了十次构图工艺，相比于现有技术中只增加了一次构图工艺。So far, the above-mentioned array substrate provided by the embodiment of the present invention has been manufactured through the above-mentioned steps 1 to 11 provided by the specific examples. The manufacturing process provided by the present invention has carried out ten patterning processes. Compared with the prior art, only an increase of A composition process.
基于同一发明构思，本发明实施例还提供了一种触控显示面板，包括本发明实施例提供的上述阵列基板。Based on the same inventive concept, an embodiment of the present invention further provides a touch display panel, including the above-mentioned array substrate provided by the embodiment of the present invention.
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述阵列基板或上述触控显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。Based on the same inventive concept, an embodiment of the present invention also provides a display device, including the above-mentioned array substrate or the above-mentioned touch display panel provided by the embodiment of the present invention. The display device can be: a mobile phone, a tablet computer, a TV, a display, Notebook computers, digital photo frames, navigators and any other products or components with display functions. The other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be regarded as limitations on the present invention. For the implementation of the display device, reference may be made to the above-mentioned embodiments of the array substrate, and repeated descriptions will not be repeated.
本发明实施例提供的一种阵列基板、其制作方法、触控显示面板及显示装置，包括：衬底基板，设置在衬底基板上的交叉而置且相互绝缘的多条栅线和多条数据线，以及位于阵列基板的一边框区域的源极驱动电路；源极驱动电路的各引脚与各数据线直接电性连接；还包括：与源极驱动电路位于同一边框区域的栅极驱动电路，以及与各栅线一一对应且电性连接的金属走线；栅极驱动电路的各引脚与各金属走线直接电性连接。由于栅极驱动电路和源极驱动电路均位于阵列基板的同一边框区域内，栅极驱动电路通过金属走线依次向各栅线加载栅极扫描信号，源极驱动电路直接向各数据线加载灰阶信号，这样可以大幅提高屏占比，实现另外三边的极窄边框甚至无边框，让用户享受到前所未有的视觉体验和更加惊艳的视觉效果。An array substrate, a manufacturing method thereof, a touch display panel, and a display device provided by an embodiment of the present invention include: a base substrate, a plurality of intersecting and mutually insulated gate lines and a plurality of Data lines, and a source drive circuit located in a frame area of the array substrate; each pin of the source drive circuit is directly electrically connected to each data line; also includes: a gate drive located in the same frame area as the source drive circuit Circuits, and metal wires corresponding to and electrically connected to each gate line; each pin of the gate driving circuit is directly electrically connected to each metal wire. Since both the gate drive circuit and the source drive circuit are located in the same frame area of the array substrate, the gate drive circuit sequentially loads the gate scanning signal to each gate line through the metal wiring, and the source drive circuit directly loads the gray signal to each data line. This can greatly increase the screen-to-body ratio and achieve extremely narrow or even no borders on the other three sides, allowing users to enjoy an unprecedented visual experience and more stunning visual effects.
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.
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| CN201610405244.7ACN105932029A (en) | 2016-06-08 | 2016-06-08 | Array substrate, production method thereof, touch display panel and display device |
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| CN201610405244.7ACN105932029A (en) | 2016-06-08 | 2016-06-08 | Array substrate, production method thereof, touch display panel and display device |
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| CN105932029Atrue CN105932029A (en) | 2016-09-07 |
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| CN201610405244.7APendingCN105932029A (en) | 2016-06-08 | 2016-06-08 | Array substrate, production method thereof, touch display panel and display device |
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| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
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