Specific embodiment
Carry out detailed description of the present invention illustrative embodiments with reference to the drawings.It should be appreciated that shown in attached drawing andThe embodiment of description is only exemplary, it is intended that is illustrated the principle and spirit of the invention, and is not limited model of the inventionIt encloses.
Phase synchronous device and method in the present invention are completed by directly being handled the amplitude vector of complex signalPhase synchronization.Therefore, the input of each module in following devices and the input of each step in method, are all signalsAmplitude vector rather than the phase of signal.Correspondingly, processed in the treatment process and each step in each moduleJourney, and the amplitude vector for complex signal.
Fig. 3 show the structure chart of one embodiment of phase synchronous device 300 of the invention.As shown in figure 3, phase is sameWalking device 300 may include: differential discriminator 301, error compensator 302, loop filter 303, the first reconstructor 304 and the second weightStructure device 305.
Differential discriminator 301 is to receive signal as input, for removing the modulation intelligence for receiving signal.Since phase modulation isGiven information, it is therefore possible to use any means remove the phase of modulated signal in differential discriminator, such as: it is multiple using twoThe method that signal multiplication adds.It in one embodiment of the invention, can also include phase splicing module in differential discriminator, it can be withEarly gate technique late is used to carry out phase splicing to overcome the problems, such as phase cycle-skipping.
Error compensator 302 may include first input end and the second input terminal.First input end can be with differential discriminator301 output end is connected.Second input terminal can be connected with the output end of the 304 of the first reconstructor.
In one embodiment of the invention, due to the amplitude vector that the input information of error compensator 302 is complex signal,Therefore, error compensator may be constructed such that by calculating the signal from first input end and the signal from the second input terminalConjugate product obtain the phase difference of the two signals.
Loop filter 303 may include the first output end and second output terminal, and input terminal can be with error compensator302 output end is connected.The signal of the first output end output of loop filter can be used for loop-locking and second exportsThe signal of end output can be used for that signal is reconstructed.
Input information due to entering loop filter 303 is the amplitude vector of complex signal, at of the invention oneIn embodiment, loop filter 303 may further include range value adjustment module, be configured to by adjusting loop filteringKeep its value of real part constant while the imaginary values of the input end signal of device 303 to change its phase.It can be by adjusting letter in replyNumber imaginary values simultaneously keep value of real part constant to change its phase.Such as: if phase theta (n) to be synchronized=Δ fn+ Δφ can be such that the real part of signal remains unchanged then when being fitted Δ f, and imaginary part is restrained with certain step-length.And it is fitted ΔReal part can also be made to remain unchanged when φ, and imaginary part is restrained with certain step-length.
Since the range value of the signal after range value adjustment module adjusts the angle can be also changed, in order to protectThe range value for holding signal does not occur big variation, and in one embodiment of the invention, loop filter 303 can be wrapped furtherIt includes range value and keeps module, be configured to adjust the range value size of module output signal according to range value to add itIt weighs to offset the variation of range value.
In one embodiment of the invention, range value keeps module can be according to following Weighted Rule to its input signalIt is weighted:
When | Sc | when > 4, y=Sc*0.0625；
When 2 < | Sc | when < 4, y=Sc*0.5；
When 0 < | Sc | when < 0.25, y=Sc*8；
When 0.25 < | Sc | when < 0.5, y=Sc*2；
When 0.5 < | Sc | when < 2, y=Sc.
Wherein, Sc indicates the output of range value adjustment module, and y indicates the signal obtained after keeping.
It is emphasized that the rule of above-mentioned point of Pyatyi weighting is an example, also it is segmented into other series and carries outWeighting, the also adjustable change of the weighted value of every level-one.
Further, since the processing of removal modulation intelligence has been done in differential discriminator 301, so, for using MPSK tuneFor the signal of system, as phase theta (n) to be synchronized=Δ fn+ Δ φ, entering parameter to be estimated entrained by the vector of ring is D=M Δ fn+M Δ φ.Therefore, it needs to be locked with D=M Δ fn+M Δ φ when loop-locking.And signalIn parameter to be estimated be D=Δ fn+ Δ φ, so need to be compensated with D=Δ fn+ Δ φ when being compensated to signal.
The input terminal of first reconstructor 304 can be connected with the first output end of loop filter 303, the first reconstructor304 output end can be connected with the second input terminal of error compensator 302.In this way, reconstructed through the first reconstructor 304Signal may be used for generating loop-locking signal.
The input terminal of second reconstructor 305 can be connected with the second output terminal of loop filter 303, the second reconstructor305 for generating and receiving the phase locked local load of signal according to the signal of the second output terminal of loop filter 303Wave.That is: the second reconstructor 305 can be with the output signal of output phase synchronizing device 300.
Information due to entering the first reconstructor 304 and the second reconstructor 305 is all the amplitude vector of signal, thisTwo reconstructors can reconstruct corresponding signal by the way of carrying out tired multiply to input signal.Work as phase synchronous deviceWhen the signal received is modulated using MPSK, the input signal of the input signal of the first reconstructor 304 and the second reconstructor 305 itBetween meet the relationship of M:1, wherein M indicates the order of modulation of MPSK.
So far phase synchronous device according to an embodiment of the present invention is described, it is same which can reduce phaseCalculation amount during step reduces the consumption to hardware resource.
The present invention also provides a kind of phase synchronization methods.With reference to Fig. 4, Fig. 4 is phase synchronization method 400 of the inventionThe flow chart of one embodiment.In one embodiment of the invention, phase synchronization method 400 may include steps of 401To 404.
In step 401, removal receives the modulation intelligence of signal.
Since phase modulation is Given information, it is therefore possible to use any means remove modulated signal in differential discriminatorPhase, such as: utilize the mutually multiply-add method of two complex signals.It in one embodiment of the invention, can also be using early slowGate technique carries out phase splicing to overcome the problems, such as phase cycle-skipping.
In step 402, according to the amplitude of the amplitude of the later reception signal of removal modulation intelligence and loop-locking signalGenerate error signal.
In one embodiment of the invention, error letter can be obtained by calculating the conjugate product of the two signalsNumber, the phase difference of the two signals is contained in error signal.
In step 403, loop-locking signal and reconstruction signal are generated by adjusting the amplitude of error signal.
In one embodiment of the invention, value of real part can be kept constant next simultaneously by adjusting the imaginary values of complex signalChange its phase.Such as: if phase theta (n) to be synchronized=Δ fn+ Δ φ can make signal when being fitted Δ fReal part remains unchanged, and imaginary part is restrained with certain step-length.And when being fitted Δ φ real part can also remain unchanged, and it is emptyIt is restrained with certain step-length in portion.
Since the range value of the signal after being adjusted can be also changed, in order to keep the range value of signal not go outNow big variation, in one embodiment of the invention, can according to the range value size of range value signal adjusted come pairIt, which is weighted, offsets the variation of range value to compensate.
In one embodiment of the invention, its input signal can be weighted according to following Weighted Rule:
When | Sc | when > 4, y=Sc*0.0625；
When 2 < | Sc | when < 4, y=Sc*0.5；
When 0 < | Sc | when < 0.25, y=Sc*8；
When 0.25 < | Sc | when < 0.5, y=Sc*2；
When 0.5 < | Sc | when < 2, y=Sc.
Wherein, Sc indicates that real part or imaginary part signal adjusted, y indicate the signal after range value is kept.
It is emphasized that the rule of above-mentioned point of Pyatyi weighting is an example, also it is segmented into other series and carries outWeighting, the also adjustable change of the weighted value of every level-one.
Further, since the processing of removal modulation intelligence has been done in step 401, so, for being modulated using MPSKSignal for, as phase theta (n) to be synchronized=Δ fn+ Δ φ, entering parameter to be estimated entrained by the vector of ring is D=M·Δf·n+M·Δφ.Therefore, it needs to be locked with D=M Δ fn+M Δ φ when loop-locking, and in signalParameter to be estimated be D=Δ fn+ Δ φ, so need to be compensated with D=Δ fn+ Δ φ when being compensated to signal.
In step 404, by reconstruction signal carry out it is tired multiply generate and receive the phase locked of signal and local carryWave.
Can respectively to loop-locking signal and reconstruction signal carry out it is tired multiply, obtain for loop-locking signal and with receptionThe phase locked local carrier of signal.
So far phase synchronization method according to an embodiment of the present invention is described, it is same which can reduce phaseCalculation amount during step reduces the consumption to hardware resource.