CN105870191B - Gate alignment contact and manufacturing method thereof - Google Patents

Abstract

Translated fromChinese

描述了栅极对准接触部和形成栅极对准接触部的方法。例如，制造半导体结构的方法包括在形成于衬底之上的有源区之上形成多个栅极结构。栅极结构每个均包括栅极电介质层、栅极电极和侧壁间隔体。多个接触插塞被形成，每个接触插塞直接在多个栅极结构中的两个相邻栅极结构的侧壁间隔体之间形成。多个接触部被形成，每个接触部直接在多个栅极结构的两个相邻栅极结构的侧壁间隔体之间形成。多个接触部和多个栅极结构在形成所述多个接触插塞之后形成。

Gate alignment contacts and methods of forming gate alignment contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures over an active region formed over a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs are formed, each contact plug being formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts are formed, each contact being formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts and a plurality of gate structures are formed after forming the plurality of contact plugs.

Description

Translated fromChinese

栅极对准接触部及其制造方法Gate-aligned contact and method of making the same

本申请为分案申请，其原申请是2014年6月20日进入中国国家阶段、国际申请日为2011年12月22日的国际专利申请PCT/US2011/066989，该原申请的中国国家申请号是201180075764.1，发明名称为“栅极对准接触部及其制造方法”。This application is a divisional application, the original application is the international patent application PCT/US2011/066989 entered into the Chinese national phase on June 20, 2014, and the international filing date is December 22, 2011, and the Chinese national application number of the original application is It is 201180075764.1, and the title of the invention is "Gate Alignment Contact and Manufacturing Method".

技术领域technical field

本发明的实施例属于半导体器件和处理的领域，且特别涉及栅极对准接触部和形成栅极对准接触部的方法。Embodiments of the invention pertain to the field of semiconductor devices and processing, and in particular to gate-aligned contacts and methods of forming gate-aligned contacts.

背景技术Background technique

在过去的几十年，在集成电路中的特征的缩放是支持不断增长的半导体工业的推动力。缩放到越来越小的特征实现了在半导体芯片的有限占用面积上的功能单元的增加的密度。例如，缩小的晶体管尺寸允许增加数量的存储器或逻辑设备合并在芯片上，从而导致具有增加的容量的产品的制造。然而，对更大的容量的追求并不是没有问题。优化每个设备的性能的必要性变得日益重要。Scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry over the past few decades. Scaling to smaller and smaller features enables increased density of functional units on the limited footprint of a semiconductor chip. For example, shrinking transistor sizes allow an increased number of memory or logic devices to be incorporated on a chip, leading to the manufacture of products with increased capacity. However, the quest for greater capacity is not without its problems. The need to optimize the performance of each device becomes increasingly important.

在集成电路器件的制造中，当器件尺寸继续按比例缩小时，多栅极晶体管(例如三栅极晶体管)变得更普遍。在常规过程中，三栅极晶体管通常被制造在体硅衬底或绝缘体上硅衬底上。在一些实例中，体硅衬底由于其较低的成本且因为它们实现较不复杂的三栅极制造工艺而是优选的。在其它实例中，绝缘体上硅衬底由于三栅极晶体管的提高的短沟道特性而是优选的。In the manufacture of integrated circuit devices, multi-gate transistors (eg, tri-gate transistors) are becoming more common as device dimensions continue to be scaled down. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable less complex tri-gate fabrication processes. In other examples, silicon-on-insulator substrates are preferred due to the improved short channel characteristics of tri-gate transistors.

然而，缩放多栅极晶体管并不是没有后果。当微电子电路的这些基本构成构件的尺寸减小时且当在给定区中制造的基本构成构件的绝对数量增加时，对用于图案化这些构成构件的光刻工艺的约束变成不可抵挡的。特别是，在半导体叠层中被图案化的特征的最小尺寸(临界尺寸)和这样的特征间的间隔之间会有折衷。However, scaling multi-gate transistors is not without consequences. As the size of these basic building blocks of a microelectronic circuit decreases and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on the lithography process used to pattern these building blocks become overwhelming . In particular, there is a trade-off between the minimum dimension (critical dimension) of the features to be patterned in the semiconductor stack and the spacing between such features.

发明内容SUMMARY OF THE INVENTION

本发明的实施例包括栅极对准接触部和形成栅极对准接触部的方法。Embodiments of the invention include gate-aligned contacts and methods of forming gate-aligned contacts.

在实施例中，半导体结构包括在布置在衬底之上的三维有源区的顶表面之上并沿着三维有源区的侧壁布置的多个栅极结构。栅极结构均包括栅极电介质层、栅极电极和侧壁间隔体。多个接触部被包括，每个接触部直接布置在多个栅极结构的两个相邻栅极结构的侧壁间隔体之间。多个接触插塞也被包括，每个接触插塞直接布置在多个栅极结构的两个相邻栅极结构的侧壁间隔体之间。In an embodiment, the semiconductor structure includes a plurality of gate structures arranged over a top surface of a three-dimensional active region disposed over a substrate and along sidewalls of the three-dimensional active region. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contacts are included, each contact being disposed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contact plugs are also included, each contact plug being disposed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures.

在另一实施例中，制造半导体结构的方法包括在形成于衬底之上的有源区之上形成多个栅极结构。每个栅极结构均包括栅极电介质层、栅极电极和侧壁间隔体。多个接触插塞被形成，每个接触插塞直接在多个栅极结构的两个相邻栅极结构的侧壁间隔体之间形成。多个接触部被形成，每个接触部直接在多个栅极结构中的两个相邻栅极结构的侧壁间隔体之间形成。多个接触部和多个栅极结构在形成所述多个接触插塞之后形成。In another embodiment, a method of fabricating a semiconductor structure includes forming a plurality of gate structures over an active region formed over a substrate. Each gate structure includes a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs are formed, each contact plug being formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts are formed, each contact being formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts and a plurality of gate structures are formed after forming the plurality of contact plugs.

在另一实施例中，制造半导体结构的方法包括在衬底之上形成栅极线格栅。栅极线格栅包括多个虚设栅极线。掩蔽叠层在栅极线格栅的虚设栅极线之上和之间形成。图案化硬掩模层仅在栅极线格栅的虚设栅极线的第一部分之上和之间由掩蔽叠层形成，暴露虚设栅极线的第二部分。电介质层在图案化硬掩模层之上和在虚设栅极线的第二部分之上和之间形成。电介质层被平面化以在虚设栅极线的第二部分之上和之间形成图案化电介质层，并重新暴露图案化硬掩模层。图案化硬掩模层从栅极线格栅的虚设栅极线的第一部分去除，重新暴露虚设栅极线的第一部分。层间电介质层在图案化电介质层之上和在虚设栅极线的第一部分之上和之间形成。层间电介质层和图案化电介质层被平面化，以分别形成在虚设栅极线的第一部分之间而不是之上的第一永久层间电介质部分，和形成在虚设栅极线的第二部分之间而不是之上的牺牲电介质部分。虚设栅极线的第一或第二部分或这两者的虚设栅极线中的一个或多个被图案化以提供在多个虚设栅极当中和在第一永久层间电介质部分和牺牲电介质部分的其余区当中的沟槽区。沟槽区填充有第二永久层间电介质部分。多个虚设栅极用永久栅极结构代替。牺牲电介质部分的其余区被去除以提供接触开口。接触部然后在接触开口中形成。In another embodiment, a method of fabricating a semiconductor structure includes forming a grid of gate lines over a substrate. The grid of gate lines includes a plurality of dummy gate lines. A masking stack is formed over and between the dummy gate lines of the gate line grid. A patterned hardmask layer is formed from the masking stack only over and between the first portions of the dummy gate lines of the gate line grid, exposing the second portion of the dummy gate lines. A dielectric layer is formed over the patterned hard mask layer and over and between the second portion of the dummy gate line. The dielectric layer is planarized to form a patterned dielectric layer over and between the second portions of the dummy gate lines, and to re-expose the patterned hardmask layer. The patterned hard mask layer is removed from the first portion of the dummy gate lines of the gate line grid, re-exposing the first portion of the dummy gate lines. An interlayer dielectric layer is formed over the patterned dielectric layer and over and between the first portions of the dummy gate lines. The interlayer dielectric layer and the patterned dielectric layer are planarized to form a first permanent interlayer dielectric portion between and not over the first portion of the dummy gate line, and a second portion of the dummy gate line, respectively between but not over the sacrificial dielectric portion. one or more of the dummy gate lines of the first or second portion or both of the dummy gate lines are patterned to provide a sacrificial dielectric among the plurality of dummy gates and in the first permanent interlayer dielectric portion part of the trench area among the remaining areas. The trench region is filled with a second permanent interlayer dielectric portion. Multiple dummy gates are replaced with permanent gate structures. The remainder of the sacrificial dielectric portion is removed to provide contact openings. Contacts are then formed in the contact openings.

附图说明Description of drawings

图1A-1K示出表示在根据本发明的实施例的制造具有栅极对准接触部的半导体结构的方法中的各种操作的横截面视图，其中：1A-1K illustrate cross-sectional views representing various operations in a method of fabricating a semiconductor structure having gate-aligned contacts in accordance with an embodiment of the present invention, wherein:

图1A示出在衬底之上形成栅极线格栅，栅极线格栅包括多个虚设栅极线；FIG. 1A illustrates forming a grid of gate lines over a substrate, the grid of gate lines including a plurality of dummy gate lines;

图1B示出在图1A的栅极线格栅的虚设栅极线之上和之间形成掩蔽叠层；FIG. 1B illustrates forming a masking stack over and between dummy gate lines of the gate line grid of FIG. 1A;

图1C示出由图1B的掩蔽叠层形成图案化硬掩模层，图案化硬掩模层在栅极线格栅的虚设栅极线的仅仅第一部分之上和之间形成，暴露虚设栅极线的第二部分；1C illustrates the formation of a patterned hardmask layer from the masking stack of FIG. 1B formed over and between only the first portions of the dummy gate lines of the gate line grid, exposing the dummy gates the second part of the polar line;

图1D示出在图1C的图案化硬掩模层之上和在虚设栅极线的第二部分之上和之间形成电介质层；1D illustrates forming a dielectric layer over the patterned hard mask layer of FIG. 1C and over and between the second portion of the dummy gate line;

图1E示出图1D的电介质层被平面化以在虚设栅极线的第二部分之上和之间形成图案化电介质层并重新暴露图案化硬掩模层；1E shows the dielectric layer of FIG. 1D being planarized to form a patterned dielectric layer over and between the second portions of the dummy gate lines and to re-expose the patterned hardmask layer;

图1F示出图1E的图案化硬掩模层被从栅极线格栅的虚设栅极线的第一部分去除，重新暴露虚设栅极线的第一部分；1F shows the patterned hardmask layer of FIG. 1E being removed from a first portion of the dummy gate lines of the gate line grid, re-exposing the first portion of the dummy gate lines;

图1G示出在图案化电介质层之上形成并且在虚设栅极线的第一部分之上和之间形成层间电介质层；1G illustrates forming an interlayer dielectric layer over the patterned dielectric layer and over and between the first portions of the dummy gate lines;

图1H示出层间电介质层和图案化电介质层被平面化，以分别形成在虚设栅极线的第一部分之间而不是之上形成第一永久层间电介质部分，以及在虚设栅极线的第二部分之间而不是之上形成牺牲电介质部分；1H shows that the interlayer dielectric layer and the patterned dielectric layer are planarized to form a first permanent interlayer dielectric portion between and not over the first portion of the dummy gate line, respectively, and that the forming a sacrificial dielectric portion between and not over the second portion;

图1I示出图1H的虚设栅极线的第一或第二部分或这两者的一个或多个虚设栅极线被图案化，以提供在多个虚设栅极当中和在第一永久层间电介质部分和牺牲电介质部分的其余区当中的沟槽区，沟槽区填充有第二永久层间电介质部分；FIG. 1I shows that one or more dummy gate lines of the first or second portion or both of the dummy gate lines of FIG. 1H are patterned to provide among the plurality of dummy gates and in the first permanent layer a trench region among the remaining regions of the inter-dielectric portion and the sacrificial dielectric portion, the trench region being filled with the second permanent inter-layer dielectric portion;

图1J示出用永久栅极结构代替图1I的多个虚设栅极；以及FIG. 1J illustrates replacing the plurality of dummy gates of FIG. 1I with permanent gate structures; and

图1K示出牺牲电介质部分的其余区被去除以提供接触开口。FIG. 1K shows the remaining regions of the sacrificial dielectric portion removed to provide contact openings.

图2示出根据本发明的实施例的具有栅极对准接触部的半导体结构的横截面视图。2 illustrates a cross-sectional view of a semiconductor structure with gate-aligned contacts in accordance with an embodiment of the present invention.

图3示出根据本发明的实施例的具有栅极对准接触部的半导体结构的平面图。3 illustrates a plan view of a semiconductor structure with gate-aligned contacts in accordance with an embodiment of the present invention.

图4示出根据本发明的另一实施例的具有栅极对准接触部的另一半导体结构的平面图。4 shows a plan view of another semiconductor structure having gate aligned contacts in accordance with another embodiment of the present invention.

图5示出根据本发明的一个实现方式的计算设备。5 illustrates a computing device according to one implementation of the present invention.

具体实施方式Detailed ways

描述了栅极对准接触部和形成栅极对准接触部的方法。在下面的描述中，阐述了很多特定的细节，例如特定的集成和材料状况，以便提供对本发明的实施例的透彻理解。对本领域中的技术人员将明显的是，本发明的实施例可在没有这些特定细节的情况下被实施。在其它实例中，公知的特征(例如集成电路设计布局)没有被详细描述，以便不没有必要地使本发明的实施例难以理解。此外，应理解，在附图中示出的各种实施例是例证性表示且不一定按比例绘制。Gate alignment contacts and methods of forming gate alignment contacts are described. In the following description, numerous specific details are set forth, such as specific integrations and material conditions, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, have not been described in detail so as not to unnecessarily obscure embodiments of the invention. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

本发明的一个或多个实施例涉及栅极对准接触过程。这样的过程可被实现来形成用于半导体结构制造(例如用于集成电路制造)的接触图案。在实施例中，接触图案被形成为与现有的栅极图案对准。相反，常规方法一般涉及光刻接触图案结合选择性接触蚀刻而与现有栅极图案紧密配准的额外的光刻工艺。例如，常规过程可包括通过分别图案化接触部和接触插塞来图案化多晶(poly)(栅极)栅格。One or more embodiments of the present invention relate to gate aligned contact processes. Such a process may be implemented to form contact patterns for semiconductor structure fabrication, such as for integrated circuit fabrication. In an embodiment, the contact pattern is formed to be aligned with the existing gate pattern. In contrast, conventional methods generally involve an additional photolithography process in which the photolithographic contact pattern is combined with selective contact etching to closely register with the existing gate pattern. For example, conventional processes may include patterning a poly (gate) grid by patterning contacts and contact plugs, respectively.

根据本文描述的一个或多个实施例，接触部形成的方法包括接触图案的形成，接触图案与现有栅极图案完全对准，同时由于非常严格的配准预算而消除了光刻步骤的使用。在一个这样的实施例中，该方法实现固有地高度选择性的湿蚀刻(例如，与照惯例实现的干或等离子体蚀刻对比)的使用以产生接触开口。在实施例中，通过结合接触插塞光刻操作而利用现有的栅极图案来形成接触图案。在一个这样的实施例中，该方法能够消除对否则如在常规方法中使用的产生接触图案的关键的光刻操作的需要。在实施例中，沟槽接触栅格不被单独地图案化，而是在多晶(栅极)线之间形成。例如，在一个这样的实施例中，沟槽接触栅格在栅极格栅图案化之后但在栅极格栅切割之前形成。In accordance with one or more embodiments described herein, a method of contact formation includes the formation of a contact pattern that is fully aligned with an existing gate pattern while eliminating the use of photolithography steps due to very tight registration budgets . In one such embodiment, the method enables the use of an inherently highly selective wet etch (eg, as opposed to conventionally accomplished dry or plasma etch) to create contact openings. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method can eliminate the need for otherwise critical photolithographic operations to create contact patterns as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately, but is formed between poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

图1A-1K示出表示在根据本发明的实施例的制造具有栅极对准接触部的半导体结构的方法中的各种操作的横截面视图。图2示出根据本发明的实施例的具有栅极对准接触部的半导体结构的横截面视图。1A-1K illustrate cross-sectional views representing various operations in a method of fabricating a semiconductor structure having gate-aligned contacts in accordance with embodiments of the present invention. 2 illustrates a cross-sectional view of a semiconductor structure with gate-aligned contacts in accordance with an embodiment of the present invention.

首先参考图2，半导体结构包括布置在衬底的有源区102之上的多个栅极结构134。例如，有源区可包括如在图2中描绘的扩散区104。栅极结构134每个包括栅极电介质层136、栅极电极138和侧壁间隔体110。电介质盖140也可被包括，如下面更详细描述的。多个接触部142被包括，每个接触部直接布置在多个栅极结构134的两个相邻栅极结构的侧壁间隔体110之间。多个接触插塞128/132也被包括，每个接触插塞直接布置在多个栅极结构的两个相邻栅极结构的侧壁间隔体110之间。下面提供对栅极结构134、有源区102、扩散区104、栅极电介质层136、栅极电极138、侧壁间隔体110、电介质盖140、接触部142和接触插塞128/132的可能的材料选择。因此，在实施例中，没有这样布置在栅极结构134的侧壁间隔体110和接触部142之间的中间材料层或残留物。Referring first to FIG. 2, a semiconductor structure includes a plurality ofgate structures 134 disposed over anactive region 102 of a substrate. For example, the active region may includediffusion region 104 as depicted in FIG. 2 . Thegate structures 134 each include agate dielectric layer 136 , agate electrode 138 andsidewall spacers 110 . Adielectric cover 140 may also be included, as described in more detail below. A plurality ofcontacts 142 are included, each contact being disposed directly between thesidewall spacers 110 of two adjacent gate structures of the plurality ofgate structures 134 . A plurality of contact plugs 128/132 are also included, each contact plug being disposed directly between thesidewall spacers 110 of two adjacent gate structures of the plurality of gate structures. The following provides possibilities forgate structure 134,active region 102,diffusion region 104,gate dielectric layer 136,gate electrode 138,sidewall spacers 110,dielectric cap 140,contacts 142, and contact plugs 128/132 material selection. Thus, in embodiments, there is no intermediate material layer or residue so disposed between thesidewall spacers 110 of thegate structure 134 and thecontacts 142 .

参考图1A，用于制造半导体结构(例如结合图2描述的结构)的方法中的初始点可以以栅极线格栅106的制造开始。栅极线格栅106可包括具有间隔体110的虚设栅极106。栅极线格栅106可形成在有源区102之上且在一些地方形成在有源区102的扩散区104之上。因此，在实施例中，源极和漏极区(例如区104)在这个阶段被制造。然而，最终栅极图案还没有形成，虽然栅极格栅图案已形成。栅极线格栅106可由氮化物柱体或可被称为栅极虚设材料的某种其它牺牲材料构成，如在下面更详细描述的。Referring to FIG. 1A , an initial point in a method for fabricating a semiconductor structure, such as the structure described in connection with FIG. 2 , may begin with fabrication of agate line grid 106 . Thegate line grid 106 may includedummy gates 106 withspacers 110 . Agate line grid 106 may be formed over theactive region 102 and in some places over thediffusion regions 104 of theactive region 102 . Thus, in an embodiment, the source and drain regions (eg, region 104) are fabricated at this stage. However, the final gate pattern has not been formed, although the gate grid pattern has been formed. Thegate line grid 106 may be composed of nitride pillars or some other sacrificial material that may be referred to as gate dummy material, as described in more detail below.

在实施例中，有源区102由单晶材料——包括但不限于硅、锗、硅-锗或III-V化合物半导体材料——构成。扩散区104在一个实施例中是有源区102的重掺杂区。在一个实施例中，有源区102由IV族材料构成，且一个或多个部分104掺杂有硼、砷、磷、铟或其组合。在另一实施例中，有源区102由III-V族材料构成，且一个或多个部分104掺杂有碳、硅、锗、氧、硫、硒或碲。在实施例中，有源区102的至少一部分是应变的。有源区102在一个实施例中可以是三维结构(例如图案化半导体主体)的一部分或全部。可选地，在另一实施例中，有源区102总体上是平面的。In an embodiment, theactive region 102 is composed of a single crystal material including, but not limited to, silicon, germanium, silicon-germanium, or III-V compound semiconductor materials.Diffusion region 104 is a heavily doped region ofactive region 102 in one embodiment. In one embodiment, theactive region 102 is composed of a Group IV material, and one ormore portions 104 are doped with boron, arsenic, phosphorous, indium, or a combination thereof. In another embodiment, theactive region 102 is composed of a III-V material, and one ormore portions 104 are doped with carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium. In an embodiment, at least a portion of theactive region 102 is strained. Theactive region 102 may be part or all of a three-dimensional structure (eg, a patterned semiconductor body) in one embodiment. Optionally, in another embodiment, theactive region 102 is generally planar.

有源区102可作为较宽衬底的一部分被包括。衬底可由适合于半导体器件制造的材料构成。在实施例中，衬底是体衬底。例如，在一个实施例中，衬底是由单晶材料——包括但不限于硅、锗、硅-锗或III-V化合物半导体材料——构成的体衬底。可选地，衬底包括上外延层和下主体部分，其中任一个都可由单晶材料——可以包括但不限于硅、锗、硅-锗或III-V化合物半导体材料——构成。由材料(其包括但不限于二氧化硅、氮化硅或氮氧化硅)构成的中间绝缘体层可布置在上外延层和下主体部分之间。Active region 102 may be included as part of a wider substrate. The substrate may be composed of materials suitable for semiconductor device fabrication. In an embodiment, the substrate is a bulk substrate. For example, in one embodiment, the substrate is a bulk substrate composed of a single crystal material including, but not limited to, silicon, germanium, silicon-germanium, or III-V compound semiconductor materials. Optionally, the substrate includes an upper epitaxial layer and a lower body portion, either of which may be composed of a single crystal material, which may include, but is not limited to, silicon, germanium, silicon-germanium, or III-V compound semiconductor materials. An intermediate insulator layer composed of a material including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride may be disposed between the upper epitaxial layer and the lower body portion.

栅极线格栅106可由虚设栅极108形成。虚设栅极108在实施例中由适合于在替换栅极操作中去除的材料构成，如下面讨论的。在一个实施例中，虚设栅极108由多晶硅、非晶硅、二氧化硅、氮化硅或其组合构成。在另一实施例中，保护盖层(未示出)(例如二氧化硅或氮化硅层)在虚设栅极108之上形成。在实施例中，下层虚设栅极电介质层(也未示出)被包括。在实施例中，虚设栅极108还包括侧壁间隔体110，其可由适合于最终使永久栅极结构与相邻的导电接触部电隔离的材料构成。例如，在一个实施例中，间隔体110由电介质材料——例如但不限于二氧化硅、氮氧化硅、氮化硅或掺杂碳的氮化硅——构成。Thegate line grid 106 may be formed ofdummy gates 108 . Thedummy gate 108 in an embodiment is composed of a material suitable for removal in a replacement gate operation, as discussed below. In one embodiment, thedummy gate 108 is composed of polysilicon, amorphous silicon, silicon dioxide, silicon nitride, or a combination thereof. In another embodiment, a protective capping layer (not shown), such as a silicon dioxide or silicon nitride layer, is formed over thedummy gate 108 . In an embodiment, an underlying dummy gate dielectric layer (also not shown) is included. In an embodiment, thedummy gate 108 also includessidewall spacers 110, which may be composed of a material suitable to ultimately electrically isolate the permanent gate structure from adjacent conductive contacts. For example, in one embodiment, thespacers 110 are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

参考图1B，掩蔽叠层112在栅极线格栅106的虚设栅极108之上和之间形成。掩蔽叠层112包括硬掩模层114和抗反射涂层(ARC)116以及图案化光致抗蚀剂层118。根据本发明的实施例，掩蔽叠层112的光致抗蚀剂层118被图案化以最终便于在随后形成的接触图案中的中断部(interruption)的形成。中断部可被称为“接触插塞”。Referring to FIG. 1B , a maskingstack 112 is formed over and between thedummy gates 108 of thegate line grid 106 . Maskingstack 112 includeshardmask layer 114 and anti-reflective coating (ARC) 116 and patternedphotoresist layer 118 . In accordance with embodiments of the present invention, thephotoresist layer 118 of themask stack 112 is patterned to ultimately facilitate the formation of interruptions in subsequently formed contact patterns. The interruptions may be referred to as "contact plugs".

在实施例中，硬掩模层114由适合于充当随后的牺牲层的材料构成。例如，在一个实施例中，如下面更详细描述的，硬掩模层114最终被图案化以留下随后对其它特征选择性地去除的剩余的部分。在特定的这样的实施例中，硬掩模层114实质上由碳构成，例如作为一层交联有机聚合物。在一个实施例中，硬掩模层114由有机聚合材料(例如底部抗反射涂层(BARC))构成。在实施例中，硬掩模层114通过化学气相沉积(CVD)工艺形成。In an embodiment, thehard mask layer 114 is composed of a material suitable for serving as a subsequent sacrificial layer. For example, in one embodiment, as described in more detail below, thehard mask layer 114 is finally patterned to leave remaining portions that are subsequently selectively removed for other features. In certain such embodiments,hardmask layer 114 consists essentially of carbon, eg, as a layer of a cross-linked organic polymer. In one embodiment, thehard mask layer 114 is composed of an organic polymeric material such as a bottom anti-reflective coating (BARC). In an embodiment, thehard mask layer 114 is formed by a chemical vapor deposition (CVD) process.

在实施例中，ARC层116适合于在光致抗蚀剂层118的光刻图案化期间抑制反射干扰。在一个这样的实施例中，ARC层116由旋涂玻璃材料构成。图案化光致抗蚀剂层118可由适合于在光刻工艺中使用的材料构成。在一个实施例中，图案化光致抗蚀剂层118通过首先掩蔽光致抗蚀剂材料的均厚层并接着将它暴露于光源来形成。图案化光致抗蚀剂层118可接着通过使均厚光致抗蚀剂层显影来形成。在实施例中，暴露于光源的光致抗蚀剂层的部分在使光致抗蚀剂层显影时被去除。因此，图案化光致抗蚀剂层118由正光致抗蚀材料构成。在特定的实施例中，图案化光致抗蚀剂层118由正光致抗蚀材料——例如但不限于248nm抗蚀剂、193nm抗蚀剂、157nm抗蚀剂、远紫外线(EUV)抗蚀剂、电子束压印层或具有邻叠氮萘醌敏化剂的酚醛树脂基体——构成。在另一实施例中，暴露于光源的光致抗蚀剂层的部分在使光致抗蚀剂层显影时被保留。因此，图案化光致抗蚀剂层118由负性光致抗蚀材料构成。在特定的实施例中，图案化光致抗蚀剂层118由负性光致抗蚀材料构成，例如但不限于由顺-聚异戊间二烯或聚乙烯肉桂酸酯构成。In an embodiment, theARC layer 116 is adapted to suppress reflection interference during lithographic patterning of thephotoresist layer 118 . In one such embodiment, theARC layer 116 is composed of a spin-on-glass material. The patternedphotoresist layer 118 may be composed of a material suitable for use in a photolithographic process. In one embodiment, patternedphotoresist layer 118 is formed by first masking a blanket layer of photoresist material and then exposing it to a light source. The patternedphotoresist layer 118 may then be formed by developing the blanket photoresist layer. In an embodiment, the portion of the photoresist layer exposed to the light source is removed when the photoresist layer is developed. Thus, the patternedphotoresist layer 118 is composed of a positive photoresist material. In particular embodiments, the patternedphotoresist layer 118 is made of a positive photoresist material such as, but not limited to, 248nm resist, 193nm resist, 157nm resist, extreme ultraviolet (EUV) resist agent, e-beam imprint layer or phenolic resin matrix with ortho-naphthoquinone sensitizer - constitute. In another embodiment, the portion of the photoresist layer exposed to the light source is retained when the photoresist layer is developed. Thus, the patternedphotoresist layer 118 is composed of a negative photoresist material. In particular embodiments, the patternedphotoresist layer 118 is composed of a negative photoresist material, such as, but not limited to, cis-polyisoprene or polyvinyl cinnamate.

参考图1C，光致抗蚀剂层118的图案通过蚀刻工艺转移到硬掩模层114以提供在栅极线格栅106的一些虚设栅极108之上和之间的图案化硬掩模层120。光致抗蚀剂层118被去除。然而，ARC层116的图案化部分可保留，如图1C所描绘的。根据本发明的实施例，光致抗蚀剂层118的图案转移到硬掩模层114以暴露在扩散区104上面的虚设栅极108，也如图1C所描绘的。在一个这样的实施例中，光致抗蚀剂层118的图案通过使用等离子体蚀刻过程而转移到硬掩模层114。Referring to FIG. 1C , the pattern ofphotoresist layer 118 is transferred tohardmask layer 114 by an etch process to provide a patterned hardmask layer over and between somedummy gates 108 ofgate line grid 106 120. Thephotoresist layer 118 is removed. However, the patterned portion of theARC layer 116 may remain, as depicted in Figure 1C. In accordance with an embodiment of the present invention, the pattern ofphotoresist layer 118 is transferred tohard mask layer 114 to exposedummy gate 108 overdiffusion region 104, also as depicted in FIG. 1C. In one such embodiment, the pattern ofphotoresist layer 118 is transferred tohardmask layer 114 using a plasma etch process.

参考图1D，ARC层116的任何其余部分被去除，且电介质层122在图案化硬掩模层120之上和在栅极线格栅106的被暴露虚设栅极108之上和之间形成。在实施例中，电介质层122由适合于充当随后的牺牲层的材料构成。例如，在一个实施例中，如下面更详细描述的，最终相对于其它被暴露特征选择性地去除电介质层122。在特定的实施例中，电介质层由二氧化硅构成。Referring to FIG. 1D , any remaining portions of theARC layer 116 are removed, and adielectric layer 122 is formed over the patternedhardmask layer 120 and over and between the exposeddummy gates 108 of thegate line grid 106 . In an embodiment, thedielectric layer 122 is composed of a material suitable for serving as a subsequent sacrificial layer. For example, in one embodiment, as described in more detail below,dielectric layer 122 is eventually removed selectively relative to other exposed features. In certain embodiments, the dielectric layer is composed of silicon dioxide.

参考图1E，电介质层122被平面化以形成图案化电介质层124并重新暴露图案化硬掩模层120。在实施例中，通过化学机械平面化(CMP)工艺操作来平面化电介质层122。在一个这样的实施例中，CMP工艺操作涉及使用浆料在抛光垫上抛光电介质层122。在另一实施例中，干蚀刻工艺被使用。Referring to FIG. 1E ,dielectric layer 122 is planarized to form patterneddielectric layer 124 and re-exposed patternedhard mask layer 120 . In an embodiment, thedielectric layer 122 is planarized by a chemical mechanical planarization (CMP) process operation. In one such embodiment, the CMP process operation involves polishing thedielectric layer 122 on the polishing pad using a slurry. In another embodiment, a dry etching process is used.

参考图1F，利用对图案化电介质层124的选择性并且利用对栅极线格栅106的下层虚设栅极108的选择性来去除图案化硬掩模层120。在实施例中，图案化硬掩模层120实质上或全部由碳构成，并利用对由二氧化硅构成的图案化电介质层124的选择性来去除。在实施例中，图案化硬掩模层120实质上或全部由碳构成，并利用灰化工艺(ash process)来去除。在一个实施例中，图案化硬掩模层120由含碳物质构成并在利用氧(O₂)气或氮(N₂)气和氢(H₂)气的组合的干灰化操作中被去除。Referring to FIG. 1F , the patternedhard mask layer 120 is removed with selectivity to the patterneddielectric layer 124 and with selectivity to theunderlying dummy gates 108 of thegate line grid 106 . In an embodiment, the patternedhardmask layer 120 is composed substantially or entirely of carbon and is removed with selectivity to the patterneddielectric layer 124 composed of silicon dioxide. In an embodiment, the patternedhard mask layer 120 consists substantially or entirely of carbon and is removed using an ash process. In one embodiment, the patternedhard mask layer 120 is composed of a carbonaceous material and is etched in a dry ashing operation using oxygen (O₂ ) gas or a combination of nitrogen (N₂ ) gas and hydrogen (H₂ ) gas remove.

参考图1G，层间电介质层126在图案化电介质层124之上以及在栅极线格栅106的被暴露虚设栅极108之上和之间形成。根据本发明的实施例，层间电介质层126提供永久层间电介质层的第一部分，如下面描述的。在一个实施例中，层间电介质层126由碳化硅材料构成。在特定的这样的实施例中，使用化学气相沉积(CVD)工艺来形成碳化硅材料。在另一实施例中，层间电介质层126由例如但不限于二氧化硅、氮化硅或氮氧化硅的材料构成。Referring to FIG. 1G , aninterlayer dielectric layer 126 is formed over the patterneddielectric layer 124 and over and between the exposeddummy gates 108 of thegate line grid 106 . According to embodiments of the present invention, theinterlayer dielectric layer 126 provides the first portion of the permanent interlayer dielectric layer, as described below. In one embodiment, theinterlayer dielectric layer 126 is composed of a silicon carbide material. In certain such embodiments, the silicon carbide material is formed using a chemical vapor deposition (CVD) process. In another embodiment, theinterlayer dielectric layer 126 is composed of a material such as, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride.

参考图1H，层间电介质层126和图案化电介质层124被平面化以暴露栅极线格栅106的所有虚设栅极108的顶部部分。根据本发明的实施例，平面化提供第一永久层间电介质部分128和牺牲电介质部分130。在实施例中，层间电介质层126和图案化电介质层124通过CMP工艺操作来平面化，如上面结合图1E描述的。Referring to FIG. 1H , theinterlayer dielectric layer 126 and the patterneddielectric layer 124 are planarized to expose the top portions of all thedummy gates 108 of thegate line grid 106 . The planarization provides the first permanentinterlayer dielectric portion 128 and thesacrificial dielectric portion 130 in accordance with an embodiment of the present invention. In an embodiment, theinterlayer dielectric layer 126 and the patterneddielectric layer 124 are planarized by a CMP process operation, as described above in connection with FIG. 1E .

在这个阶段，栅极线格栅106的虚设栅极108——包括间隔体110——可垂直于格栅结构而被图案化。作为例子，不在扩散区域之上，例如在隔离区之上的栅极线格栅106的部分可被去除。在另一例子中，图案化产生分立的虚设栅极结构。参考图1I，在一个这样的实施例中，例如通过光刻法和蚀刻工艺来去除不在扩散区104上面的虚设栅极108的部分(和相应的间隔体110部分)。At this stage, thedummy gates 108 of thegate line grid 106, including thespacers 110, may be patterned perpendicular to the grid structure. As an example, portions ofgate line grid 106 that are not over diffusion regions, such as over isolation regions, may be removed. In another example, patterning creates discrete dummy gate structures. Referring to FIG. 1I, in one such embodiment, portions of dummy gate 108 (andcorresponding spacer 110 portions) that are not overdiffusion regions 104 are removed, eg, by photolithography and etching processes.

再次参考图1I，栅极线格栅106被去除的部分可接着由第二永久层间电介质部分132填充。第二永久层间电介质部分132可以用类似于第一永久层间电介质部分128的方式并由与第一永久层间电介质部分128相同或类似的材料而(例如)通过沉积和平面化来形成。应理解，在图1I中的视图可具有在与图1H所示的横截面不同的位置上(例如，进或出纸面)的横截面。因此，此时，永久层间电介质层可由在第一区(在图1I中未示出)中形成的第一永久层间电介质部分128和在第二区中形成的第二永久层间电介质部分132的组合限定。在一个这样的实施例中，第一永久层间电介质部分128和第二永久层间电介质部分132都由碳化硅构成。Referring again to FIG. 1I , the removed portion ofgate line grid 106 may then be filled with second permanentinterlayer dielectric portion 132 . The second permanentinterlayer dielectric portion 132 may be formed, eg, by deposition and planarization, in a similar manner to the first permanentinterlayer dielectric portion 128 and from the same or similar material as the first permanentinterlayer dielectric portion 128 . It should be understood that the view in FIG. 1I may have a cross-section at a different location (eg, into or out of the paper) than the cross-section shown in FIG. 1H . Therefore, at this time, the permanent interlayer dielectric layer may be formed of the first permanentinterlayer dielectric portion 128 formed in the first region (not shown in FIG. 1I ) and the second permanent interlayer dielectric portion formed in the second region A combination of 132 is limited. In one such embodiment, both the first permanentinterlayer dielectric portion 128 and the second permanentinterlayer dielectric portion 132 are composed of silicon carbide.

在这个阶段，被暴露的其余虚设栅极108可以在替换栅极过程方案中被代替。在这样的方案中，虚设栅极材料(例如多晶硅或氮化硅柱体材料)可被去除并用永久栅极电极材料代替。在一个这样的实施例中，永久栅极电介质层也在这个过程中形成，与从早些时候的处理完成的相反。At this stage, the remainingdummy gates 108 that are exposed can be replaced in a replacement gate process scheme. In such a scheme, dummy gate material (eg, polysilicon or silicon nitride pillar material) can be removed and replaced with permanent gate electrode material. In one such embodiment, the permanent gate dielectric layer is also formed during this process, as opposed to what was done from an earlier process.

在实施例中，通过干蚀刻或湿蚀刻工艺来去除虚设栅极108。在一个实施例中，虚设栅极108由多晶硅或非晶硅构成并使用包括SF₆的干蚀刻工艺来去除。在另一实施例中，虚设栅极108由多晶硅或非晶硅构成并使用包括含水NH₄OH或四甲基氢氧化铵的湿蚀刻工艺来去除。在一个实施例中，虚设栅极108由氮化硅构成并使用包括含水磷酸的湿蚀刻来去除。In an embodiment, thedummy gate 108 is removed by a dry etch or wet etch process. In one embodiment, thedummy gate 108 is composed of polysilicon or amorphous silicon and removed using a dry etch process including_SF6 . In another embodiment, thedummy gate 108 is composed of polysilicon or amorphous silicon and removed using a wet etch process including aqueous_NH4OH or tetramethylammonium hydroxide. In one embodiment, thedummy gate 108 is composed of silicon nitride and removed using a wet etch including aqueous phosphoric acid.

参考图1J，永久栅极结构134被形成以包括永久栅极电介质层136和永久栅极电极层或叠层138。此外，在实施例中，永久栅极结构134的顶部部分例如通过蚀刻工艺来去除并用电介质盖层140代替。在实施例中，电介质盖层140由与由碳化硅构成的第一永久层间电介质部分128和第二永久层间电介质部分132都相同的材料构成。在一个这样的实施例中，所有电介质盖层140、第一永久层间电介质部分128和第二永久层间电介质部分132都由碳化硅构成。Referring to FIG. 1J , apermanent gate structure 134 is formed to include a permanentgate dielectric layer 136 and a permanent gate electrode layer orstack 138 . Furthermore, in an embodiment, the top portion of thepermanent gate structure 134 is removed and replaced with adielectric capping layer 140 , such as by an etch process. In an embodiment, thedielectric cap layer 140 is composed of the same material as both the first permanentinterlayer dielectric portion 128 and the second permanentinterlayer dielectric portion 132, which are composed of silicon carbide. In one such embodiment, all of thedielectric cap layer 140, the first permanentinterlayer dielectric portion 128, and the second permanentinterlayer dielectric portion 132 are composed of silicon carbide.

在实施例中，永久栅极电介质层136由高K材料构成。例如，在一个实施例中，永久栅极电介质层136由材料构成，所述材料例如但不限于氧化铪、氮氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸钡锶、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌或其组合。此外，永久栅极电介质层136的一部分可包括由扩散区104的顶部几个层形成的一层天然氧化物。在实施例中，永久栅极电介质层136由顶部高k部分和由半导体材料的氧化物构成的下部分构成。在一个实施例中，永久栅极电介质层136由氧化铪的顶部分和二氧化硅或氮氧化硅的底部分构成。In an embodiment, the permanentgate dielectric layer 136 is composed of a high-K material. For example, in one embodiment, the permanentgate dielectric layer 136 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, titanium barium strontium oxide, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate or combinations thereof. Additionally, a portion of permanentgate dielectric layer 136 may include a layer of native oxide formed from the top layers ofdiffusion region 104 . In an embodiment, the permanentgate dielectric layer 136 is composed of a top high-k portion and a lower portion composed of an oxide of semiconductor material. In one embodiment, the permanentgate dielectric layer 136 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

在实施例中，永久栅极电极层或叠层138由金属栅极构成。在一个实施例中，永久栅极电极层或叠层138由金属层——例如但不限于金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍或导电金属氧化物——构成。在特定的实施例中，永久栅极电极层或叠层138由在金属功函数设定层之上形成的非功函数设定填充材料构成。在实施例中，永久栅极电极层或叠层138还包括可由绝缘电介质材料构成的侧壁间隔体110，如上所述。In an embodiment, the permanent gate electrode layer or stack 138 consists of a metal gate. In one embodiment, the permanent gate electrode layer or stack 138 is composed of metal layers such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, Ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides - make up. In certain embodiments, the permanent gate electrode layer or stack 138 is composed of a non-workfunction setting fill material formed over the metallic workfunction setting layer. In an embodiment, the permanent gate electrode layer or stack 138 also includessidewall spacers 110, which may be composed of an insulating dielectric material, as described above.

参考图1K，相对于电介质盖层140、第一永久层间电介质部分128、第二永久层间电介质部分132、间隔体110和扩散区104的被暴露部分而选择性地去除牺牲电介质部分130。在实施例中，使用干蚀刻或湿蚀刻工艺(例如含水氢氟酸(HF)湿蚀刻工艺)来去除牺牲电介质部分130。根据本发明的实施例，牺牲电介质部分130充当牺牲占位器，用于随后的接触形成。Referring to FIG. 1K ,sacrificial dielectric portion 130 is selectively removed with respect to exposed portions ofdielectric cap layer 140 , first permanentinterlayer dielectric portion 128 , second permanentinterlayer dielectric portion 132 ,spacer 110 , anddiffusion region 104 . In an embodiment, thesacrificial dielectric portion 130 is removed using a dry etch or a wet etch process, such as an aqueous hydrofluoric acid (HF) wet etch process. According to embodiments of the present invention, thesacrificial dielectric portion 130 acts as a sacrificial placeholder for subsequent contact formation.

再次参考图2，一旦设置了牺牲电介质部分130，就形成了接触部142。因此，接触部142在永久栅极结构134之间形成。在实施例中，接触部142通过导电材料的沉积和平面化(例如通过CMP)来形成。接触部142可由导电材料构成。在实施例中，接触部142由金属物质构成。金属物质可以是纯金属(例如镍或钴)，或可以是合金，例如金属-金属合金或金属-半导体合金(例如硅化物材料)。Referring again to FIG. 2, once thesacrificial dielectric portion 130 is provided, thecontacts 142 are formed. Thus,contacts 142 are formed betweenpermanent gate structures 134 . In an embodiment, thecontacts 142 are formed by deposition and planarization of a conductive material (eg, by CMP). Thecontact portion 142 may be composed of a conductive material. In an embodiment, thecontact portion 142 is composed of a metallic substance. The metallic species may be pure metals (eg, nickel or cobalt), or may be alloys, such as metal-metal alloys or metal-semiconductor alloys (eg, silicide materials).

图3示出根据本发明的实施例的显示半导体结构的某些特征的平面图。参考图3，半导体结构包括布置在衬底的有源区102(例如扩散区104)之上的多个栅极结构134。多个接触部142被包括，每个接触部直接布置在多个栅极结构134中的两个相邻栅极结构之间，例如直接在多个栅极结构134中的两个相邻栅极结构的侧壁间隔体之间。3 illustrates a plan view showing certain features of a semiconductor structure in accordance with an embodiment of the present invention. Referring to FIG. 3, the semiconductor structure includes a plurality ofgate structures 134 disposed over the active region 102 (eg, the diffusion region 104) of the substrate. A plurality ofcontacts 142 are included, each contact being disposed directly between two adjacent gate structures of the plurality ofgate structures 134 , eg, directly within two adjacent gates of the plurality ofgate structures 134 between the sidewall spacers of the structure.

因此，在实施例中，制造半导体结构的方法包括在衬底之上形成栅极线格栅。栅极线格栅包括多个虚设栅极线。掩蔽叠层在栅极线格栅的虚设栅极线之上和之间形成。图案化硬掩模层在栅极线格栅的虚设栅极线的仅仅第一部分之上和之间由掩蔽叠层形成，暴露虚设栅极线的第二部分。电介质层在图案化硬掩模层之上以及在虚设栅极线的第二部分之上和之间形成。电介质层被平面化以在虚设栅极线的第二部分之上和之间形成图案化电介质层，并重新暴露图案化硬掩模层。图案化硬掩模层从栅极线格栅的虚设栅极线的第一部分去除，重新暴露虚设栅极线的第一部分。层间电介质层在图案化硬掩模层之上以及在虚设栅极线的第一部分之上和之间形成。层间电介质层和图案化电介质层被平面化，以分别形成在虚设栅极线的第一部分之间而不是之上的第一永久层间电介质部分以及形成在虚设栅极线的第二部分之间而不是之上的牺牲电介质部分。虚设栅极线的第一或第二部分或这两者的虚设栅极线中的一个或多个被图案化以提供在多个虚设栅极当中和在第一永久层间电介质部分和牺牲电介质部分的其余区当中的沟槽区。沟槽区填充有第二永久层间电介质部分。多个虚设栅极用永久栅极结构代替。牺牲电介质部分的其余区被去除以提供接触开口。接触部然后在接触开口中形成。Accordingly, in an embodiment, a method of fabricating a semiconductor structure includes forming a grid of gate lines over a substrate. The grid of gate lines includes a plurality of dummy gate lines. A masking stack is formed over and between the dummy gate lines of the gate line grid. A patterned hardmask layer is formed of a masking stack over and between only a first portion of the dummy gate lines of the gate line grid, exposing a second portion of the dummy gate lines. A dielectric layer is formed over the patterned hard mask layer and over and between the second portion of the dummy gate line. The dielectric layer is planarized to form a patterned dielectric layer over and between the second portions of the dummy gate lines, and to re-expose the patterned hard mask layer. The patterned hard mask layer is removed from the first portion of the dummy gate lines of the gate line grid, re-exposing the first portion of the dummy gate lines. An interlayer dielectric layer is formed over the patterned hard mask layer and over and between the first portions of the dummy gate lines. The interlayer dielectric layer and the patterned dielectric layer are planarized to form between, respectively, a first permanent interlayer dielectric portion between and not over the first portion of the dummy gate line and a second portion of the dummy gate line. between and not over the sacrificial dielectric portion. one or more of the dummy gate lines of the first or second portion or both of the dummy gate lines are patterned to provide a sacrificial dielectric among the plurality of dummy gates and in the first permanent interlayer dielectric portion part of the trench area among the remaining areas. The trench region is filled with a second permanent interlayer dielectric portion. Multiple dummy gates are replaced with permanent gate structures. The remainder of the sacrificial dielectric portion is removed to provide contact openings. Contacts are then formed in the contact openings.

在一个这样的实施例中，形成图案化硬掩模层包括形成交联有机聚合物层，形成电介质层包括形成一层二氧化硅，形成层间电介质层包括形成一层碳化硅，并且用第二永久层间电介质部分填充沟槽区包括形成并平面化第二层碳化硅。在特定的这样的实施例中，用永久栅极结构代替多个虚设栅极包括形成永久栅极电介质层、永久栅极层和碳化硅盖层。在另一这样的实施例中，在衬底之上形成栅极线格栅包括在三维有源区的顶表面之上并沿着三维有源区的侧壁形成虚设栅极线。In one such embodiment, forming the patterned hardmask layer includes forming a crosslinked organic polymer layer, forming a dielectric layer includes forming a layer of silicon dioxide, forming an interlayer dielectric layer includes forming a layer of silicon carbide, and Partially filling the trench region with a permanent interlayer dielectric includes forming and planarizing a second layer of silicon carbide. In certain such embodiments, replacing the plurality of dummy gates with a permanent gate structure includes forming a permanent gate dielectric layer, a permanent gate layer, and a silicon carbide capping layer. In another of these embodiments, forming a grid of gate lines over the substrate includes forming dummy gate lines over a top surface of the three-dimensional active region and along sidewalls of the three-dimensional active region.

在实施例中，本文描述的一种或多种方法有效地设想结合虚设和替换接触部过程的虚设和替换栅极过程。在一个这样的实施例中，替换接触部过程在替换栅极过程之后被执行以允许永久栅极叠层的至少一部分的高温退火。例如，在特定的这样的实施例中，永久栅极结构的至少一部分的退火例如在栅极电介质层形成之后在比大约600摄氏度更高的温度下被执行。退火在永久接触部的形成之前被执行。In an embodiment, one or more of the methods described herein effectively envision dummy and replacement gate processes combined with dummy and replacement contact processes. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature annealing of at least a portion of the permanent gate stack. For example, in certain such embodiments, the annealing of at least a portion of the permanent gate structure is performed, eg, after the gate dielectric layer is formed, at a temperature higher than about 600 degrees Celsius. Annealing is performed prior to the formation of permanent contacts.

在实施例中，虚设接触部在接触部插塞的形成之前形成。也就是说，虚设接触部可在切割栅极格栅中的虚设栅极结构之前形成。这样的方法可提供在最终布局中的灵活性。在一个这样的实施例中，接触结构被形成为与两个或更多个扩散区接触。例如，图4示出根据本发明的另一实施例的具有栅极对准接触部的另一半导体结构的平面图。In an embodiment, the dummy contacts are formed prior to the formation of the contact plugs. That is, the dummy contacts may be formed before cutting the dummy gate structures in the gate grid. Such an approach provides flexibility in the final layout. In one such embodiment, the contact structure is formed in contact with two or more diffusion regions. For example, FIG. 4 shows a plan view of another semiconductor structure having gate-aligned contacts in accordance with another embodiment of the present invention.

参考图4，半导体结构包括布置在衬底的有源区102(例如扩散区104)之上的多个栅极结构134。多个接触部142被包括，每个接触部直接布置在多个栅极结构134的两个相邻栅极结构之间，例如直接在多个栅极结构134的两个相邻栅极结构的侧壁间隔体之间。接触部144之一被形成为与两个扩散区接触。在特定的实施例中通过之前存在的虚设栅极格栅线来促进接触部144的形成，虚设栅极格栅线未被切割，直到接触部144的至少虚设接触占位器形成为止。Referring to FIG. 4, the semiconductor structure includes a plurality ofgate structures 134 disposed over the active region 102 (eg, the diffusion region 104) of the substrate. A plurality ofcontacts 142 are included, each contact being disposed directly between two adjacent gate structures of the plurality ofgate structures 134 , eg, directly between two adjacent gate structures of the plurality ofgate structures 134 . between the sidewall spacers. One of thecontact portions 144 is formed in contact with the two diffusion regions. Formation ofcontacts 144 is facilitated in certain embodiments by pre-existing dummy gate grid lines that are not cut until at least dummy contact placeholders ofcontacts 144 are formed.

应理解，不是上述过程的所有方面都需要被实施以落在本发明的实施例的精神和范围内。例如，在一个实施例中，从来不需要形成虚设栅极。上面描述的栅极叠层可实际上是如最初形成的永久栅极叠层。在一个这样的实施例中，只要插塞形成后面是栅极切割操作，益处和优点就将实现。It should be understood that not all aspects of the above-described processes need to be implemented to fall within the spirit and scope of embodiments of the present invention. For example, in one embodiment, dummy gates need never be formed. The gate stacks described above may actually be permanent gate stacks as originally formed. In one such embodiment, benefits and advantages are realized as long as plug formation is followed by a gate dicing operation.

本文描述的过程可用于制造一个或多个半导体器件。半导体器件可以是晶体管或类似器件。例如，在实施例中，半导体器件是用于逻辑或存储器的金属氧化物半导体(MOS)晶体管、或双极晶体管。此外，在实施例中，半导体器件具有三维架构，例如三栅极器件、独立访问的双栅极器件或FIN-FET。The processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Furthermore, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, or a FIN-FET.

图5示出根据本发明的一个实现方式的计算设备500。计算设备500容纳板502。板502可包括多个部件，包括但不限于处理器504和至少一个通信芯片506。处理器504物理地和电气地耦合到板502。在一些实现方式中，至少一个通信芯片506也物理地和电气地耦合到板502。在另外的实现方式中，通信芯片506是处理器504的部分。Figure 5 illustrates a computing device 500 according to one implementation of the invention. Computing device 500 houses board 502 . Board 502 may include various components including, but not limited to,processor 504 and at least onecommunication chip 506 .Processor 504 is physically and electrically coupled to board 502 . In some implementations, at least onecommunication chip 506 is also physically and electrically coupled to board 502 . In other implementations, thecommunication chip 506 is part of theprocessor 504 .

根据其应用，计算设备500可包括可以或可以不物理地和电气地耦合到板502的其它部件。这些其它部件可包括但不限于易失性存储器(例如DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机和大容量存储设备(例如硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等)。Depending on its application, computing device 500 may include other components that may or may not be physically and electrically coupled to board 502 . These other components may include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreens Displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard drives, Compact Disc (CD), Digital Versatile Disc (DVD), etc.).

通信芯片506实现用于数据往返于计算设备500的传输的无线通信。术语“无线”及其派生词可用于描述可通过使用经由非固体介质的经调制电磁辐射来传递数据的电路、设备、系统、方法、技术、通信信道等。该术语并不暗示相关联的设备不包含任何电线，虽然在一些实施例中它们可以不包含电线。通信芯片506可实现多种无线标准或协议中的任一个，包括但不限于Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物以及被指定为3G、4G、5G和更高代的任何其它无线协议。计算设备500可包括多个通信芯片506。例如，第一通信芯片506可专用于较短距离无线通信(例如Wi-Fi和蓝牙)，而第二通信芯片506可专用于较长距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。Communication chip 506 enables wireless communication for the transfer of data to and from computing device 500 . The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. Thecommunication chip 506 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+ , HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G and higher generations. Computing device 500 may include multiple communication chips 506 . For example, thefirst communication chip 506 may be dedicated to short-range wireless communication (eg, Wi-Fi and Bluetooth), while thesecond communication chip 506 may be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

计算设备500的处理器504包括封装在处理器504内的集成电路管芯。在本发明的一些实现方式中，处理器的集成电路管芯包括一个或多个器件，例如根据本发明的实现方式构建的MOS-FET晶体管。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将所述电子数据转换成可存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的部分。Theprocessor 504 of the computing device 500 includes an integrated circuit die packaged within theprocessor 504 . In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors constructed in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to convert the electronic data into other electronic data that may be stored in the registers and/or memory.

通信芯片506还包括封装在通信芯片506内的集成电路管芯。根据本发明的另一实现方式，通信芯片的集成电路管芯包括一个或多个器件，例如根据本发明的实现方式构建的MOS-FET晶体管。Communication chip 506 also includes an integrated circuit die packaged withincommunication chip 506 . According to another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors constructed in accordance with implementations of the invention.

在另外的实现方式中，容纳在计算设备500内的另一部件可包含集成电路管芯，其包括一个或多个器件，例如根据本发明的实现方式构建的MOS-FET晶体管。In further implementations, another component housed within computing device 500 may comprise an integrated circuit die that includes one or more devices, such as MOS-FET transistors constructed in accordance with implementations of the present invention.

在各种实现方式中，计算设备500可以是膝上型计算机、上网本、笔记本计算机、超级本计算机、智能电话、平板计算机、个人数字助理(PDA)、超移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录器。在另外的实现方式中，计算设备500可以是处理数据的任何其它电子设备。In various implementations, computing device 500 may be a laptop computer, netbook, notebook computer, ultrabook computer, smartphone, tablet computer, personal digital assistant (PDA), ultramobile PC, mobile phone, desktop computer , server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player or digital video recorder. In further implementations, computing device 500 may be any other electronic device that processes data.

因此，公开了栅极对准接触部和形成栅极对准接触部的方法。在实施例中，制造半导体结构的方法包括在形成在衬底之上的有源区之上形成多个栅极结构。栅极结构每个均包括栅极电介质层、栅极电极和侧壁间隔体。形成多个接触插塞，每个接触插塞直接形成在多个栅极结构中的两个相邻栅极结构的侧壁间隔体之间。形成多个接触部，每个接触部直接形成在多个栅极结构中的两个相邻栅极结构的侧壁间隔体之间。多个接触部和多个栅极结构在形成多个接触插塞之后形成。在一个实施例中，多个栅极结构通过在形成多个接触部之前代替多个虚设栅极而形成。在一个实施例中，形成多个接触部包括形成与有源区的两个或更多个扩散区接触的接触结构。Accordingly, gate alignment contacts and methods of forming gate alignment contacts are disclosed. In an embodiment, a method of fabricating a semiconductor structure includes forming a plurality of gate structures over an active region formed over a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs are formed, each contact plug being formed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts are formed, each contact being formed directly between sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed after forming the plurality of contact plugs. In one embodiment, the plurality of gate structures are formed by replacing the plurality of dummy gates before forming the plurality of contacts. In one embodiment, forming the plurality of contacts includes forming a contact structure in contact with two or more diffusion regions of the active region.

Claims (14)

Translated fromChinese

1.一种半导体结构，包括：1. A semiconductor structure comprising:多个栅极结构，所述多个栅极结构中的每一个均布置在衬底的三维有源区之上，而不布置在隔离区之上，所述多个栅极结构中的每一个均包括栅极电介质层、栅极电极、侧壁间隔体和位于所述侧壁间隔体之间且与所述侧壁间隔体横向相邻的电介质盖层，其中所述侧壁间隔体包括第一电介质材料，其中所述电介质盖层包括独立于所述第一电介质材料的第二电介质材料，并且其中所述侧壁间隔体的所述第一电介质材料与所述电介质盖层的所述第二电介质材料在基本竖直的界面处相交；a plurality of gate structures, each of the plurality of gate structures disposed over the three-dimensional active region of the substrate and not over the isolation region, each of the plurality of gate structures Each includes a gate dielectric layer, a gate electrode, sidewall spacers, and a dielectric cap layer between and laterally adjacent to the sidewall spacers, wherein the sidewall spacers include a first a dielectric material, wherein the dielectric cap layer includes a second dielectric material separate from the first dielectric material, and wherein the first dielectric material of the sidewall spacers is separate from the first dielectric material of the dielectric cap layer The two dielectric materials intersect at a substantially vertical interface;多个接触部，所述多个接触部中的每一个均直接布置在所述多个栅极结构中的两个相邻栅极结构的所述侧壁间隔体之间并且均布置在所述三维有源区之上，而不布置在所述隔离区之上，并且所述多个接触部中的每一个的顶表面与所述多个栅极结构的所述电介质盖层的顶表面基本上共面；以及a plurality of contacts, each of the plurality of contacts being disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures and each being disposed within the plurality of gate structures over a three-dimensional active region, but not over the isolation region, and a top surface of each of the plurality of contacts is substantially the same as a top surface of the dielectric capping layer of the plurality of gate structures upper coplanar; and多个接触插塞，所述多个接触插塞中的每一个均直接布置在所述多个栅极结构中的两个相邻栅极结构的所述侧壁间隔体之间，并且所述多个接触插塞中的每一个的顶表面与所述多个栅极结构的所述电介质盖层的所述顶表面基本上共面且与所述多个接触部的所述顶表面基本上共面。a plurality of contact plugs, each of the plurality of contact plugs being disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures, and the a top surface of each of the plurality of contact plugs is substantially coplanar with the top surface of the dielectric capping layer of the plurality of gate structures and substantially coplanar with the top surface of the plurality of contacts coplanar.2.如权利要求1所述的半导体结构，其中所述多个栅极结构中的每一个均包括高K栅极电介质、金属栅极和作为所述电介质盖层的所述第二电介质材料的碳化硅盖。2. The semiconductor structure of claim 1, wherein each of the plurality of gate structures comprises a high-K gate dielectric, a metal gate, and the second dielectric material as the dielectric capping layer. Silicon carbide cover.3.如权利要求1所述的半导体结构，其中所述侧壁间隔体由二氧化硅、氮氧化硅、氮化硅或掺杂碳的氮化硅构成。3. The semiconductor structure of claim 1, wherein the sidewall spacers are comprised of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.4.如权利要求3所述的半导体结构，其中所述电介质盖层由碳化硅构成。4. The semiconductor structure of claim 3, wherein the dielectric cap layer is comprised of silicon carbide.5.如权利要求1所述的半导体结构，其中所述多个接触部包括导电材料，而所述多个接触插塞包括碳化硅。5. The semiconductor structure of claim 1, wherein the plurality of contacts comprise conductive material and the plurality of contact plugs comprise silicon carbide.6.如权利要求5所述的半导体结构，其中所述多个栅极结构中的每一个均包括高K栅极电介质、金属栅极和作为所述电介质盖层的所述第二电介质材料的碳化硅盖。6. The semiconductor structure of claim 5, wherein each of the plurality of gate structures includes a high-K gate dielectric, a metal gate, and the second dielectric material as the dielectric cap layer. Silicon carbide cover.7.如权利要求1所述的半导体结构，其中所述多个接触部之一与所述三维有源区的两个或更多个扩散区接触。7. The semiconductor structure of claim 1, wherein one of the plurality of contacts is in contact with two or more diffusion regions of the three-dimensional active region.8.一种半导体结构，包括：8. A semiconductor structure comprising:多个栅极结构，所述多个栅极结构中的每一个均布置在衬底的有源区之上，而不布置在隔离区之上，所述多个栅极结构中的每一个均包括栅极电介质层、栅极电极、侧壁间隔体和位于所述侧壁间隔体之间且与所述侧壁间隔体横向相邻的电介质盖层，其中所述侧壁间隔体包括第一电介质材料，其中所述电介质盖层包括独立于所述第一电介质材料的第二电介质材料，并且其中所述侧壁间隔体的所述第一电介质材料与所述电介质盖层的所述第二电介质材料在基本竖直的界面处相交；a plurality of gate structures, each of the plurality of gate structures disposed over the active region of the substrate and not over the isolation region, each of the plurality of gate structures including a gate dielectric layer, a gate electrode, sidewall spacers, and a dielectric cap layer between and laterally adjacent to the sidewall spacers, wherein the sidewall spacers include a first a dielectric material, wherein the dielectric cap layer includes a second dielectric material separate from the first dielectric material, and wherein the first dielectric material of the sidewall spacers is separate from the second dielectric material of the dielectric cap layer the dielectric materials intersect at a substantially vertical interface;多个接触部，所述多个接触部中的每一个均直接布置在所述多个栅极结构中的两个相邻栅极结构的所述侧壁间隔体之间并且均布置在所述有源区之上，而不布置在所述隔离区之上，并且所述多个接触部中的每一个的顶表面与所述多个栅极结构的所述电介质盖层的顶表面基本上共面；以及a plurality of contacts, each of the plurality of contacts being disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures and each being disposed within the plurality of gate structures over the active region, but not over the isolation region, and a top surface of each of the plurality of contacts is substantially the same as a top surface of the dielectric capping layer of the plurality of gate structures coplanar; and多个接触插塞，所述多个接触插塞中的每一个均直接布置在所述多个栅极结构中的两个相邻栅极结构的所述侧壁间隔体之间，并且所述多个接触插塞中的每一个的顶表面与所述多个栅极结构的所述电介质盖层的所述顶表面基本上共面且与所述多个接触部的所述顶表面基本上共面。a plurality of contact plugs, each of the plurality of contact plugs being disposed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures, and the a top surface of each of the plurality of contact plugs is substantially coplanar with the top surface of the dielectric capping layer of the plurality of gate structures and substantially coplanar with the top surface of the plurality of contacts coplanar.9.如权利要求8所述的半导体结构，其中所述多个栅极结构中的每一个均包括高K栅极电介质、金属栅极和作为所述电介质盖层的所述第二电介质材料的碳化硅盖。9. The semiconductor structure of claim 8, wherein each of the plurality of gate structures comprises a high-K gate dielectric, a metal gate, and the second dielectric material as the dielectric capping layer. Silicon carbide cover.10.如权利要求8所述的半导体结构，其中所述侧壁间隔体由二氧化硅、氮氧化硅、氮化硅或掺杂碳的氮化硅构成。10. The semiconductor structure of claim 8, wherein the sidewall spacers are comprised of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.11.如权利要求10所述的半导体结构，其中所述电介质盖层由碳化硅构成。11. The semiconductor structure of claim 10, wherein the dielectric capping layer is comprised of silicon carbide.12.如权利要求8所述的半导体结构，其中所述多个接触部包括导电材料，而所述多个接触插塞包括碳化硅。12. The semiconductor structure of claim 8, wherein the plurality of contacts comprise conductive material and the plurality of contact plugs comprise silicon carbide.13.如权利要求12所述的半导体结构，其中所述多个栅极结构中的每一个均包括高K栅极电介质、金属栅极和作为所述电介质盖层的所述第二电介质材料的碳化硅盖。13. The semiconductor structure of claim 12, wherein each of the plurality of gate structures comprises a high-K gate dielectric, a metal gate, and as the dielectric capping layer of the second dielectric material Silicon carbide cover.14.如权利要求8所述的半导体结构，其中所述多个接触部之一与所述衬底的所述有源区的两个或更多个扩散区接触。14. The semiconductor structure of claim 8, wherein one of the plurality of contacts contacts two or more diffusion regions of the active region of the substrate.

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