Disclosure of Invention
The invention solves the technical problem of how to realize the full-symmetric bidirectional work of the input end and the output end of the switching power supply.
To solve the above technical problem, an embodiment of the present invention provides a converter having an input terminal and an output terminal, one of the input terminal and the output terminal of the converter receiving an input voltage, and the other of the input terminal and the output terminal of the converter outputting a dc voltage, the converter including: the switching power supply circuit comprises an energy storage element and at least one switching tube; a first sampling circuit adapted to sample a first current flowing through the energy storage element via the input terminal; a second sampling circuit adapted to sample a second current flowing through the energy storage element via the output terminal; and the PWM signal generating circuit is coupled with the first sampling circuit and the second sampling circuit and generates a PWM signal for controlling the at least one switching tube according to the first current and the second current.
Optionally, the PWM signal generation circuit includes: the first input end of the integration circuit is coupled with the input end, the second input end of the integration circuit is coupled with the output end, reference voltages are input to the third input end and the fourth input end of the integration circuit, the integration circuit is suitable for detecting errors between the direct current voltage and the reference voltages and carrying out integration operation, the first output end of the integration circuit outputs a first integration voltage, and the second output end of the integration circuit outputs a second integration voltage; a comparison circuit, a first input end of which is coupled to the first output end of the integration circuit, a second input end of which is coupled to the second output end of the integration circuit, and a third input end and a fourth input end of which are input with energy storage feedback voltages, and are adapted to compare the first integration voltage with the energy storage feedback voltages, output a first comparison result, compare the second integration voltage with the energy storage feedback voltages, and output a second comparison result; the logic control circuit is suitable for receiving the first comparison result and the second comparison result, outputting the PWM signal and adjusting the duty ratio of the PWM signal according to the first comparison result or the second comparison result; and the current calculation circuit is suitable for calculating the current flowing through the energy storage element according to the first current and/or the second current under the control of the logic control circuit and outputting the energy storage feedback voltage.
Optionally, the current calculation circuit comprises: the energy storage circuit comprises a first resistor, a second resistor and a first switch, wherein the first current is input to the first end of the first resistor, the second current is input to the first end of the second resistor, and the first end of the first resistor is coupled to the first end of the second resistor and outputs the energy storage feedback voltage; the second end of the first resistor is coupled to the first end of the first switch, the second end of the second resistor is coupled to the second end of the first switch and grounded, the control end of the first switch receives a control signal, and the control signal is associated with the PWM signal output by the logic control circuit.
Optionally, the number of the switching tubes in the switching power supply circuit is four, and the switching tubes are respectively a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; the drain electrode of the first MOS tube is coupled with the first end of the switching power supply circuit, and the source electrode of the first MOS tube is coupled with the drain electrode of the second MOS tube and the first end of the energy storage element; the source electrode of the second MOS tube is coupled with the source electrode of the third MOS tube and is grounded; the drain electrode of the third MOS tube is coupled with the source electrode of the fourth MOS tube and the second end of the energy storage element; the drain electrode of the fourth MOS tube is coupled with the second end of the switching power supply circuit; one or more of the grids of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are inputted with the PWM signal.
Optionally, the control signal is obtained by performing logical and operation on PWM signals received by the gates of the first MOS transistor and the fourth MOS transistor.
Optionally, the first switch includes a fifth MOS transistor, a gate of the fifth MOS transistor is coupled to the control terminal of the first switch, a source of the fifth MOS transistor is coupled to the first terminal of the first switch, and a drain of the fifth MOS transistor is coupled to the second terminal of the first switch.
Optionally, the resistance value of the first resistor is equal to the resistance value of the second resistor.
Optionally, the first sampling circuit includes a first resistor, a first end of the first resistor is coupled to the input terminal, and a second end of the first resistor is directly or indirectly coupled to the first end of the energy storage element.
Optionally, the second sampling circuit includes a second resistor, a first end of the second resistor is coupled to the output terminal, and a second end of the second resistor is directly or indirectly coupled to the second end of the energy storage element.
Optionally, the integration circuit comprises: a first error amplifier having a first input terminal coupled to the first input terminal of the integrating circuit, a second input terminal coupled to the third input terminal of the integrating circuit, and an output terminal coupled to the first output terminal of the integrating circuit; a second error amplifier, a first input terminal of which is coupled to the second input terminal of the integrating circuit, a second input terminal of which is coupled to the fourth input terminal of the integrating circuit, and an output terminal of which is coupled to the second output terminal of the integrating circuit.
Optionally, the comparison circuit comprises: a first voltage comparator, a first input terminal of which is coupled to the first output terminal of the comparison circuit, a second input terminal of which is coupled to the third output terminal of the comparison circuit, and an output terminal of which outputs the first comparison result; a first input terminal of the second voltage comparator is coupled to the second output terminal of the comparison circuit, a second input terminal of the second voltage comparator is coupled to the fourth output terminal of the comparison circuit, and an output terminal of the second voltage comparator outputs the second comparison result.
Optionally, the energy storage element is an inductor.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
on the basis of the prior art, the embodiment of the invention can comprise a first sampling circuit, a second sampling circuit and a PWM signal generating circuit; wherein the first sampling circuit is adapted to sample a first current flowing through the energy storage element via the input terminal; the second sampling circuit is suitable for sampling a second current flowing through the energy storage element through the output end; the PWM signal generating circuit is suitable for generating a PWM signal for controlling at least one switching tube in the embodiment according to the first current and the second current; the embodiment adopts the fully-symmetrical current sampling, and the PWM signal for controlling the switching power supply circuit can be generated according to the first current obtained by sampling the input end or the second current obtained by sampling the output end, so that the input end and the output end can be interchanged as required, and the fully-symmetrical input and output work can be realized.
Further, the switching power supply circuit in the embodiment of the invention may include an energy storage element and four switching tubes, so that a large duty cycle output of the converter of the embodiment is achieved.
Further, the current calculation circuit adopted in the embodiment of the present invention calculates the average current by using an algorithm under the action of a control signal, wherein the control signal is associated with the PWM signal; when the four switching tubes included in the switching power supply circuit are switched on or off under the control of the PWM signal, the average current may represent the current flowing through the energy storage element, where the average current includes a dc component and an ac component, so that it is suitable for controlling a current loop in the converter.
Detailed Description
As described in the background section, the switching power supply in the prior art has a problem that the input terminal and the output terminal of the switching power supply cannot realize full-symmetric bidirectional operation.
In order to solve the above technical problem, an embodiment of the present invention provides a converter, which realizes fully symmetrical operation of input and output and optionally exchangeable characteristics by using fully symmetrical current sampling.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 is a schematic block diagram of a converter according to an embodiment of the present invention.
As shown in fig. 2, an embodiment of the present invention discloses a converter having an input terminal and an output terminal, one of the input terminal and the output terminal of the converter receiving an input voltage Vin, and the other outputting a dc voltage Vout, and the converter may include: a switching power supply circuit 11, a first sampling circuit 13, a second sampling circuit 14, and a PWM signal generation circuit 15.
The switching power supply circuit 11 may include an energy storage element 12 and at least one switching tube; the number of the switching tubes included in the switching power supply circuit 11 may be one, two, or four, which is not shown in fig. 2.
The first sampling circuit 13 is adapted to sample a first current I1 flowing through the energy storage element 12 via the input.
The second sampling circuit 14 is adapted to sample a second current I2 flowing through the energy storage element 12 via the output terminal.
The PWM signal generating circuit 15 is coupled to the first sampling circuit 13 and the second sampling circuit 14, and generates a PWM signal for controlling the at least one switching tube according to the first current I1 and the second current I2.
The converter of the embodiment of the present invention has the first sampling circuit 13 and the second sampling circuit 14 disposed in full symmetry, so that equivalent operation can be performed from the input end to the output end and from the output end to the input end.
Fig. 3 is a schematic block diagram of another converter according to an embodiment of the present invention.
As shown in fig. 3, in the embodiment of the present invention, the PWM signal generation circuit 15 may include an integration circuit 16, a comparison circuit 17, a logic control circuit 18, and a current calculation circuit 19.
A first input terminal of the integrating circuit 16 is coupled to the input terminal, a second input terminal of the integrating circuit 16 is coupled to the output terminal, a reference voltage Vref is input to each of a third input terminal and a fourth input terminal of the integrating circuit 16, the third input terminal and the fourth input terminal are adapted to detect an error between the dc voltage Vout and the reference voltage Vref and perform an integrating operation, a first output terminal of the integrating circuit 16 outputs a first integrated voltage E1, and a second output terminal of the integrating circuit 16 outputs a second integrated voltage E2.
A first input terminal of the comparison circuit 17 is coupled to the first output terminal of the integration circuit 16, a second input terminal of the comparison circuit 17 is coupled to the second output terminal of the integration circuit 16, and a tank feedback voltage VIFB is input to a third input terminal and a fourth input terminal of the comparison circuit 17, and is adapted to compare the first integrated voltage E1 with the tank feedback voltage VIFB, output a first comparison result V1, compare the second integrated voltage E2 with the tank feedback voltage VIFB, and output a second comparison result V2.
The logic control circuit 18 is adapted to receive the first comparison result V1 and the second comparison result V2, output the PWM signal, and adjust the duty ratio of the PWM signal according to the first comparison result V1 or the second comparison result V2.
Under the control of the logic control circuit 18, the current calculating circuit 19 is adapted to calculate the current flowing through the energy storage element 12 according to the first current I1 and/or the second current I2, and output the energy storage feedback voltage VIFB.
Fig. 4 is a schematic block diagram of the current calculating circuit 19 in the embodiment of the present invention.
As shown in fig. 4, in a specific implementation, the current calculating circuit 19 may include: a first resistor R1, a second resistor R2, and a first switch (not shown).
A first end of the first resistor R1 may be inputted with the first current I1, a first end of the second resistor R2 may be inputted with the second current I2, and a first end of the first resistor R1 is coupled to a first end of the second resistor R2 and outputs the energy storage feedback voltage VIFB; a second terminal of the first resistor R1 is coupled to a first terminal of the first switch, and a second terminal of the second resistor R2 is coupled to a second terminal of the first switch and to ground; the control terminal of the first switch receives a control signal Contr _ Sig, which is associated with the PWM signal output by the logic control circuit 18.
Fig. 5 is a schematic block diagram of another converter according to an embodiment of the present invention.
As shown in fig. 5, in a specific implementation, the number of the switching transistors in the switching power supply circuit 11 may be four, and the four switching transistors are respectively the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4, so that the converter of the present embodiment has a large duty ratio output, and the converter of the present embodiment has a high efficiency.
The drain of the first MOS transistor Q1 is coupled to the first terminal of the switching power supply circuit 11, and the source of the first MOS transistor Q1 is coupled to the drain of the second MOS transistor Q2 and the first terminal of the energy storage element 12; the source of the second MOS transistor Q2 is coupled to the source of the third MOS transistor Q3 and grounded; the drain of the third MOS transistor Q3 is coupled to the source of the fourth MOS transistor Q4 and the second terminal of the energy storage element 12; the drain of the fourth MOS transistor Q4 is coupled to the second terminal of the switching power supply circuit 11; one or more of the gates of the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3 and the fourth MOS transistor Q4 are inputted with the PWM signal (not shown).
In this embodiment, the gates of the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3 and the fourth MOS transistor Q4 are coupled to the logic control circuit 18, and the operating states of the four switching transistors can be controlled by the PWM signal output by the logic control circuit 18, but not limited in particular. The logic control circuit 18 can control signals output to the gates of the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3 and the fourth MOS transistor Q4 under the following conditions.
For example, when the input voltage Vin is less than the output voltage Vout, that is, the converter operates in a boost state, the first MOS transistor Q1 may be controlled to be turned on, the second MOS transistor Q2 may be controlled to be turned off, and the third MOS transistor Q3 and the fourth MOS transistor Q4 may be controlled by PWM signals to be alternately turned on or turned off, where the PWM signals input to the gates of the third MOS transistor Q3 and the fourth MOS transistor Q4 are opposite.
When the input terminal voltage Vin is greater than the output terminal voltage Vout, that is, the converter operates in a step-down state, the fourth MOS transistor Q4 may be controlled to be turned on, the third MOS transistor Q3 may be turned off, and the first MOS transistor Q1 and the second MOS transistor Q2 may be controlled by PWM signals to be alternately turned on or turned off, where the PWM signals input to the gates of the first MOS transistor Q1 and the second MOS transistor Q2 are opposite.
When the voltage Vin at the input end is equal to the voltage Vout at the output end, the first MOS transistor Q1 may be controlled to be turned on, the second MOS transistor Q2 may be turned off, and the third MOS transistor Q3 and the fourth MOS transistor Q4 may be controlled to be turned on or turned off alternately by a PWM signal in a preset first period; and in a second period after the first period, the fourth MOS transistor Q4 is controlled to be switched on, the third MOS transistor Q3 is controlled to be switched off, and the first MOS transistor Q1 and the second MOS transistor Q2 are controlled to be alternately switched on or switched off by PWM signals.
In the embodiment of the present invention, the energy storage element 12 may be an inductor; in fig. 5, the energy storage element 12 is shown as an inductance L.
As shown in fig. 4 and 5, the control signal may be obtained by logically and-ing the PWM signals received by the gates of the first MOS transistor Q1 and the fourth MOS transistor Q4. That is, when the first MOS transistor Q1 is controlled to be turned on or off, the first input data of the logical and is high or low, and when the fourth MOS transistor Q4 is controlled to be turned on or off, the second input data of the logical and is high or low. It should be noted that, when the coupling relationship between the first sampling circuit 13, the second sampling circuit 14 and the switching power supply circuit 11 is changed, the embodiment of the present invention may use the PWM signals received by the gates of other switching tubes to perform a logic operation to obtain the control signal, which is not limited in this embodiment.
In a specific implementation, the first switch may include a fifth MOS transistor Q5, a gate of the fifth MOS transistor Q5 is coupled to the control terminal of the first switch, a source of the fifth MOS transistor Q5 is coupled to the first terminal of the first switch, and a drain of the fifth MOS transistor Q5 is coupled to the second terminal of the first switch; the fifth MOS transistor Q5 may be an NMOS transistor, a PMOS transistor, or any other functionally equivalent circuit combination, and only needs to correspondingly adjust the logic level of the control signal, which is not limited in this embodiment.
In an embodiment, the resistance of the first resistor R1 and the resistance of the second resistor R2 may be equal or different, and may be adjusted according to specific requirements, which is not limited in this embodiment.
When the resistance of the first resistor R1 is equal to the resistance of the second resistor R2, assuming that the first current I1 is discontinuous and the second current I2 is continuous, the fifth MOS transistor Q5 is turned off when the first MOS transistor Q1 is turned off, and the fifth MOS transistor Q5 is turned on when the first MOS transistor Q1 is turned on.
The energy storage feedback voltage VIFB can be obtained by a volt-second law
VIFB＝(1-D)×(I1+I2)×R/2+D×I2×R
Wherein R may represent a resistance value of the first resistor R1 or the second resistor R2, and D may represent a duty ratio of the PWM signal.
Because of the switching power supply characteristics, when the first current I1 and the second current I2 are both continuous, I1 is equal to I2, and the above formula is simplified to VIFB is equal to I2, where I2 is equal to the current flowing through the inductor L.
Due to the symmetrical structure of the converter, when the first current I1 is discontinuous, the second current I2 is continuous, the first current I1 is continuous, the second current I2 is discontinuous, the first current I1 and the second current I2 are both continuous, and the first current I1 and the second current I2 are both discontinuous, the obtained average current can show the current flowing on the energy storage element 12 (i.e., the inductor L) no matter under the forward or reverse operating condition from the input end to the output end, wherein the average current comprises a direct current component and an alternating current component, so that the average current is suitable for controlling a current loop in the converter, the input with any duty ratio is enabled, and the bidirectional symmetrical operation of the converter is enabled.
Referring to fig. 3 and 5, in the embodiment of the present invention, the first sampling circuit 13 may include a first resistor R1, a first end of the first resistor R1 is coupled to the input terminal, and a second end of the first resistor R1 is directly or indirectly coupled to the first end of the energy storage element 12. The second sampling circuit 14 may include a second resistor R2, a first terminal of the second resistor R2 is coupled to the output terminal, and a second terminal of the second resistor R2 is coupled to the second terminal of the energy storage element 12 directly or indirectly. Since one of the first resistor R1 and the second resistor R2 is arranged at the input end of the converter, and the other one is arranged at the output end of the converter, the monitoring and the control of the currents of the input end and the output end can be realized.
It should be noted that the first current I1 is not limited to the current flowing through the first resistor R1, and may be a current arbitrarily flowing from the input terminal to the first terminal of the inductor L through the first MOS transistor Q1Q 1; similarly, the second current I2 is not limited to the current flowing through the second resistor R2, and may be a current flowing from the output terminal to the second terminal of the inductor L through the fourth MOS transistor Q4Q 4.
With continued reference to fig. 5, in a specific implementation, the integrating circuit 16 may include:
a first error amplifier 20, a first input of the first error amplifier 20 being coupled to a first input of the integrating circuit 16, a second input of the first error amplifier 20 being coupled to a third input of the integrating circuit 16, an output of the first error amplifier 20 being coupled to a first output of the integrating circuit 16;
a second error amplifier 21, a first input of the second error amplifier 21 being coupled to the second input of the integrating circuit 16, a second input of the second error amplifier 21 being coupled to the fourth input of the integrating circuit 16, and an output of the second error amplifier 21 being coupled to the second output of the integrating circuit 16.
In a specific implementation, the comparison circuit 17 may include:
a first voltage comparator 22, a first input terminal of the first voltage comparator 22 is coupled to the first output terminal of the comparison circuit 17, a second input terminal of the first voltage comparator 22 is coupled to the third output terminal of the comparison circuit 17, and an output terminal of the first voltage comparator 22 outputs the first comparison result V1;
a second voltage comparator 23, a first input terminal of the second voltage comparator 23 is coupled to the second output terminal of the comparison circuit 17, a second input terminal of the second voltage comparator 23 is coupled to the fourth output terminal of the comparison circuit 17, and an output terminal of the second voltage comparator 23 outputs the second comparison result V2.
It should be noted that, in the embodiment of the present invention, the logic control circuit 18 is adapted to adjust the duty ratio of the PWM signal according to the first comparison result V1 or the second comparison result V2, which can be implemented by technical means known to those skilled in the art, and the description of the embodiment is not repeated herein.
The converter described above may be a buck-boost converter. However, it should be noted that the converter of the present embodiment may also be configured as another type of converter, such as a boost converter or a buck converter, by appropriate configuration.
It should be further noted that the converter according to the embodiment of the present invention may be implemented as a circuit-level product, or may be manufactured as a chip, or only the PWM signal generating circuit 15 may be implemented as a chip, and when the PWM signal generating circuit 15 disclosed in the embodiment of the present invention is manufactured as a chip, the first sampling circuit 13, the second sampling circuit 14, and a part of the switching power supply circuit 11 may be configured as peripheral circuits.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.