技术领域technical field
本发明涉及微/纳米材料技术领域，涉及一种利用陷阱态调控电阻态的非易失性多比特微/纳米阻变存储器，可在无需构筑栅电压和特殊器件结构的情况下，将根据不同大小的电信号进行信息的读取、写入、存储及擦除。The present invention relates to the technical field of micro/nano materials, and relates to a non-volatile multi-bit micro/nano resistive memory that utilizes trap states to regulate resistance states. Large and small electrical signals are used to read, write, store and erase information.
背景技术Background technique
近年来，在各种新型非易失性存储器件中，阻变存储器由于其具有结构简单、能耗低、响应速度快、重复读写性好、信息存储时间长、非破坏性读取、可拓展组装及CMOS工艺可兼容等优点，受到了国内外科学家广泛的关注。电阻开关效应作为阻变存储器中关键的物理现象，被广泛的发现于电解质材料、钙钛矿材料、透明金属氧化物中。电阻开关器件的电流电压特性曲线随电压变化能够在高阻态和低阻态之间快速的转变。虽然电阻开关效应已经被清楚的观察到，然而其机理仍然在不断的研究中，目前研究得出的可能导致电阻开关的机理有有灯丝效应、氧空位迁移、电子跃迁传导、肖特基隧道调制、Poole-Frenkel激发等等。最近研究者在具有电阻开关效应的一维纳米材料中观察到了负差分电阻效应。此外，背对背的电阻开关效应也在两端为相同金属电极的一维纳米结构器件中发现，这种效应基于表面陷阱态的对注入电子的局域作用可长时间存储电荷及电子。为了实现非易失型阻态存储效果，James M. Tour课题组将单壁碳纳米管的两端焊接在SiO2/Si衬底上，并在底部构建一个栅电极。在栅电压的作用下电荷在碳纳米管和SiO2界面被俘获。这种基于单根一维单壁碳纳米管结构的纳米器件具有电阻开关效应，以及非易失性存储功能。Ting Yu课题组将单根一维ZnO纳米线焊接在铁电Pb(Zr0.3Ti0.7)O3薄膜上，构筑成具有栅电极的场效应管(FET)，其存储效果可通过栅电压有效的被调控。Wooyoung Shim等人在单根一维Ge/Si核壳纳米线上构筑两个叠加的栅电极，所构筑的内层的栅电极可控制电阻的开关，外层栅电极具有调节阻态的作用。所构筑的器件具有多比特阻变存储器的效果，同时其开关比大，稳定时间长，可被整合应用于逻辑电路中。Minghui Cao等在GeSe2掺入Bi形成有序的超结构纳米带。在高电压下，电子从Bi杂质能级跳跃至导带，空间电荷极化作用下，跃迁出来的电子局域在空间电荷区中，而电子跃迁留下空的陷阱一直被保持。这使得由单根GeSe2:Bi纳米带构筑的二端焊接Ag电极纳米器件在具有负差分电阻开关的同时还可作为非易失型阻变存储器。In recent years, among all kinds of new non-volatile memory devices, resistive memory has the advantages of simple structure, low energy consumption, fast response speed, good repeatability of reading and writing, long information storage time, non-destructive reading, and The advantages of extended assembly and CMOS process compatibility have attracted extensive attention from scientists at home and abroad. As a key physical phenomenon in RRAM, resistive switching effect is widely found in electrolyte materials, perovskite materials, and transparent metal oxides. The current-voltage characteristic curve of the resistive switching device can rapidly change between a high-resistance state and a low-resistance state as the voltage changes. Although the resistive switching effect has been clearly observed, its mechanism is still under continuous research. The mechanisms that may lead to resistive switching are the filament effect, oxygen vacancy migration, electronic transition conduction, and Schottky tunnel modulation. , Poole-Frenkel excitation and so on. Recently, negative differential resistance effects have been observed in one-dimensional nanomaterials with resistive switching effects. In addition, the back-to-back resistive switching effect is also found in one-dimensional nanostructured devices with the same metal electrodes at both ends. This effect can store charges and electrons for a long time based on the localization of surface trap states on injected electrons. In order to realize the non-volatile resistive storage effect, James M. Tour's research group welded both ends of the single-walled carbon nanotubes on the SiO2 /Si substrate, and built a gate electrode at the bottom. Charges are trapped at the CNT-SiO2 interface under the action of the gate voltage. This nano-device based on a single one-dimensional single-walled carbon nanotube structure has a resistive switching effect and a non-volatile storage function. Ting Yu's research group welded a single one-dimensional ZnO nanowire on a ferroelectric Pb(Zr0.3 Ti0.7 )O3 film to construct a field effect transistor (FET) with a gate electrode, and its storage effect can be effectively controlled by the gate voltage. is regulated. Wooyoung Shim et al. built two superimposed gate electrodes on a single one-dimensional Ge/Si core-shell nanowire. The inner gate electrode can control the switch of resistance, and the outer gate electrode can adjust the resistance state. The constructed device has the effect of a multi-bit resistive variable memory, and at the same time has a large switching ratio and a long stable time, and can be integrated and applied in a logic circuit. Minghui Cao et al. Incorporated Bi into GeSe2 to form ordered superstructure nanobelts. Under high voltage, electrons jump from the Bi impurity energy level to the conduction band. Under the action of space charge polarization, the electrons that jump out are localized in the space charge region, and the empty traps left by the electron transition are kept all the time. This enables the two-terminal welded Ag electrode nanodevices constructed from a single GeSe2 :Bi nanoribbon to be used as a nonvolatile resistive variable memory while having a negative differential resistance switch.
虽然国内外研究者在非易失性阻变存储器方面已经获得了一些成果，然而为了获得非易失性多比特存储性能，研究者在设计器件时会构建栅电压或设计特殊器件结构，少数不需要构建栅电压或特殊器件结构的阻变存储器也只有两个阻态，很难实现多比特存储性能。Although researchers at home and abroad have obtained some achievements in non-volatile resistive memory, in order to obtain non-volatile multi-bit storage performance, researchers will build gate voltage or design special device structure when designing devices. Resistive variable memory that needs to build a gate voltage or a special device structure also has only two resistance states, and it is difficult to achieve multi-bit storage performance.
发明内容Contents of the invention
本发明提供一种基于陷阱态调控的非易失性多比特微/纳米阻变存储器，是一种无需构筑栅电压和特殊器件结构的，非易失性多比特微/纳米阻变存储器，能够响应不同电场信号并长时间存储，可实现电场信号的多比特存储以及克服现有非易失性多比特记忆存储器对栅电压及特殊器件结构的依赖，The present invention provides a non-volatile multi-bit micro/nano resistive memory based on trap state control, which is a non-volatile multi-bit micro/nano resistive memory that does not need to build a gate voltage and a special device structure, and can Responding to different electric field signals and storing them for a long time, it can realize multi-bit storage of electric field signals and overcome the dependence of existing non-volatile multi-bit memory memory on gate voltage and special device structure.
本发明是通过以下技术方案实现的。The present invention is achieved through the following technical solutions.
本发明所述的一种基于陷阱态调控的非易失性多比特微/纳米阻变存储器，包括绝缘衬底（101）、单根Sn元素掺杂的ZnO一维微/纳米线（102）、电极一（103）、电极二（104）、导线一（105）、导线二（106）、封装材料（107）。单根Sn元素掺杂的ZnO一维微/纳米线（102）放置在绝缘衬底（101）上，单根Sn元素掺杂的ZnO一维微/纳米线（102）两端分别焊接电极一（103）和电极二（104），电极一（103）和电极二（104）分别连接导线一（105）和导线二（106）；封装材料（107）将整个单根Sn元素掺杂的ZnO一维微/纳米线（102）、电极一（103）和电极二（104）封装在绝缘衬底（101）上。A non-volatile multi-bit micro/nano resistive memory based on trap state regulation according to the present invention, comprising an insulating substrate (101), a single ZnO one-dimensional micro/nano wire (102) doped with Sn element , electrode one (103), electrode two (104), wire one (105), wire two (106), packaging material (107). A single Sn element-doped ZnO one-dimensional micro/nano wire (102) is placed on an insulating substrate (101), and the two ends of a single Sn element-doped ZnO one-dimensional micro/nano wire (102) are respectively welded with one electrode (103) and electrode two (104), electrode one (103) and electrode two (104) are respectively connected to wire one (105) and wire two (106); the packaging material (107) is the entire single Sn element doped ZnO The one-dimensional micro/nano wire (102), electrode one (103) and electrode two (104) are packaged on an insulating substrate (101).
优选地，所述的单根Sn元素掺杂的ZnO一维微/纳米线为ZnO晶格中掺入Sn元素杂质缺陷的一维微/纳米线。Preferably, the single Sn element-doped ZnO one-dimensional micro/nanowire is a one-dimensional micro/nanowire doped with Sn element impurity defects in the ZnO lattice.
优选地，所述绝缘基底为氧化铝陶瓷基底、氮化铝陶瓷基底或氮化硅陶瓷基底。Preferably, the insulating substrate is an alumina ceramic substrate, an aluminum nitride ceramic substrate or a silicon nitride ceramic substrate.
优选地，所述的金属电极为铝、银或铂。Preferably, the metal electrode is aluminum, silver or platinum.
优选地，所述的封装材料为环氧树脂、氨基甲酸乙酯、聚二甲基硅氧烷或聚甲基丙烯酸甲酯。Preferably, the packaging material is epoxy resin, urethane, polydimethylsiloxane or polymethylmethacrylate.
本发明所述的微/纳米阻变存储器工作时，可将导线一（105）和导线二（106）与函数功能发生器（108）连接。When the micro/nano resistive variable memory described in the present invention works, the first wire (105) and the second wire (106) can be connected with the function generator (108).
本发明的另一个目的是提供一种使用上述非易失性多比特微/纳米阻变存储器对不同电场信号的响应、存储、擦除的方法。Another object of the present invention is to provide a method for responding, storing and erasing different electric field signals using the above-mentioned non-volatile multi-bit micro/nano resistive variable memory.
（1）一种基于陷阱态调控的非易失性多比特微/纳米阻变存储器的信息写入方法，其特征是在微/纳米阻变存储器两端电极之间施加1V-10V内任一写入电压。(1) A non-volatile multi-bit micro/nano resistive variable memory information writing method based on trap state regulation, which is characterized by applying any one of 1V-10V between the two electrodes of the micro/nano resistive variable memory. write voltage.
（2）一种基于陷阱态调控的非易失性多比特微/纳米阻变存储器的非易失性多比特的存储方法，其特征是在所述的微/纳米阻变存储器两端电极之间施加1V-10V内任一写入电压，然后撤去写入电压并施加0.5V读取电压。(2) A non-volatile multi-bit storage method of non-volatile multi-bit micro/nano resistive memory based on trap state control, characterized in that between the electrodes at both ends of the micro/nano resistive memory Apply any write voltage within 1V-10V, then remove the write voltage and apply 0.5V read voltage.
（3）一种基于陷阱态调控的非易失性多比特微/纳米阻变存储器的信息擦除方法，其特征是在微/纳米阻变存储器两端电极之间施加1V-10V内任一写入电压，然后撤去写入电压并施加0.5V读取电压，再将微/纳米阻变存储器放置于70℃环境中，随后放置于室温环境中。(3) A method for erasing information of a non-volatile multi-bit micro/nano resistive variable memory based on trap state control, which is characterized in that any one of 1V-10V is applied between the electrodes at both ends of the micro/nano resistive variable memory. Write the voltage, then remove the write voltage and apply a 0.5V read voltage, then place the micro/nano resistive memory in a 70°C environment, and then in a room temperature environment.
与现有技术相比，本发明具有以下优点。Compared with the prior art, the present invention has the following advantages.
（1）应用上的新突破。本发明利用陷阱态中电子的调制作用，实现了对电场信息的响应及存储；所述的微/纳米阻变存储器能够有识别1V至12V内任一电压，根据电压的大小有区别的将信号存储于所述的微/纳米阻变存储器中，实现多比特存储性能。(1) New breakthroughs in applications. The present invention utilizes the modulation effect of electrons in the trap state to realize the response and storage of electric field information; the micro/nano resistive memory can identify any voltage from 1V to 12V, and differentiate the signal according to the magnitude of the voltage Stored in the micro/nano resistive memory to realize multi-bit storage performance.
（2）工艺简便、体积小、轻巧便携、兼容性好。本发明的微/纳米阻变存储器无需构建栅电压和特殊器件结构就可获得非易失的和多比特的存储性，简化了生产工序，节约能源消耗；本发明的微/纳米阻变存储器结构简单、体积小、制作工艺简单、成本低廉，且无需特殊的工作环境，具有很好的环境兼容性。(2) Simple process, small size, light and portable, and good compatibility. The micro/nano resistive memory of the present invention can obtain non-volatile and multi-bit storage without building a gate voltage and a special device structure, which simplifies the production process and saves energy consumption; the structure of the micro/nano resistive memory of the present invention It is simple, small in size, simple in manufacturing process, low in cost, does not require a special working environment, and has good environmental compatibility.
（3）高效利用。本发明的微/纳米阻变存储器无需大规模、高强度的能量输入，仅需放置大气环境中即可；本发明的微/纳米阻变存储器能够将电场信号重复写入-存储-擦除，使阻变存储器可循环利用；本发明的微/纳米阻变存储器具有多比特存储性能，增加了存储密度，实现能源的高效利用。(3) Efficient utilization. The micro/nano resistive memory of the present invention does not require large-scale and high-intensity energy input, and only needs to be placed in the atmospheric environment; the micro/nano resistive memory of the present invention can repeatedly write-store-erase electric field signals, The resistive variable memory can be recycled; the micro/nano resistive variable memory of the present invention has multi-bit storage performance, increases storage density, and realizes efficient utilization of energy.
附图说明Description of drawings
图1为本发明的微/纳米阻变存储器的一种典型结构示意图。其中，101为绝缘衬底、102为单根Sn元素掺杂的ZnO一维微/纳米线、103为电极一、104为电极二、105为导线一、106为导线二、107为封装材料、108为函数功能发生器。FIG. 1 is a schematic diagram of a typical structure of the micro/nano resistive memory of the present invention. Among them, 101 is an insulating substrate, 102 is a single Sn-doped ZnO one-dimensional micro/nano wire, 103 is electrode 1, 104 is electrode 2, 105 is wire 1, 106 is wire 2, 107 is packaging material, 108 is a function generator.
图2为本发明的微/纳米阻变存储器在2V、4V、6V、8V、10V电压写入后，存储性能测试，图片上部的实线部分为测试过程中的电流，图片下部的虚线部分为测试过程中的操作电压。Fig. 2 is the storage performance test of the micro/nano resistive memory of the present invention after the voltages of 2V, 4V, 6V, 8V, and 10V are written. The solid line at the top of the picture is the current during the test, and the dotted line at the bottom of the picture is The operating voltage during the test.
图3为本发明的微/纳米阻变存储器在2V、4V、6V、8V、10V电压写入后，电流随时间变化图。Fig. 3 is a diagram showing the change of current with time after the voltages of 2V, 4V, 6V, 8V and 10V are written in the micro/nano resistive memory of the present invention.
图4为本发明的微/纳米阻变存储器在2V下的重复读写性能测试曲线，图片上部的实线部分为测试过程中的电流，图片下部的虚线部分为测试过程中的操作电压。Fig. 4 is the repeated read/write performance test curve of the micro/nano resistive memory of the present invention at 2V, the solid line at the top of the picture is the current during the test, and the dotted line at the bottom of the picture is the operating voltage during the test.
图5为本发明的微/纳米阻变存储器在4V下的重复读写性能测试曲线，图片上部的实线部分为测试过程中的电流，图片下部的虚线部分为测试过程中的操作电压。Fig. 5 is the repeated read/write performance test curve of the micro/nano resistive memory of the present invention at 4V, the solid line at the top of the picture is the current during the test, and the dotted line at the bottom of the picture is the operating voltage during the test.
图6为本发明的微/纳米阻变存储器在6V下的重复读写性能测试曲线，图片上部的实线部分为测试过程中的电流，图片下部的虚线部分为测试过程中的操作电压。Fig. 6 is the repeated read/write performance test curve of the micro/nano resistive memory of the present invention at 6V, the solid line at the top of the picture is the current during the test, and the dotted line at the bottom of the picture is the operating voltage during the test.
图7为本发明的微/纳米阻变存储器在8V下的重复读写性能测试曲线，图片上部的实线部分为测试过程中的电流，图片下部的虚线部分为测试过程中的操作电压。Fig. 7 is the repeated read/write performance test curve of the micro/nano resistive memory of the present invention at 8V, the solid line at the top of the picture is the current during the test, and the dotted line at the bottom of the picture is the operating voltage during the test.
图8为本发明的微/纳米阻变存储器在10V下的重复读写性能测试曲线，图片上部的实线部分为测试过程中的电流，图片下部的虚线部分为测试过程中的操作电压。Fig. 8 is the repeated read/write performance test curve of the micro/nano resistive memory of the present invention at 10V, the solid line at the top of the picture is the current during the test, and the dotted line at the bottom of the picture is the operating voltage during the test.
具体实施方式Detailed ways
下面将结合实施例和附图，对本发明的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例，基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护范围。The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments and the accompanying drawings. Apparently, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work , all belong to the protection scope of the present invention.
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，所述示意图只是示例，其在此不应限制本发明保护的范围。Secondly, the present invention is described in detail with reference to the schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.
本发明提供一种微/纳米阻变存储器，在无需栅压和特殊器件结构的情况下，能够响应1V至10V内任一电压，根据两端电极之间电压的大小有区别的将电信号存储于所述的微/纳米阻变存储器中，实现非易失性多比特存储性能。本发明的一种微/纳米阻变存储器利用单根Sn元素掺杂的ZnO微/纳米线中的陷阱能级，通过外加电场对陷阱能级内电子填充状态来调控器件的电阻，实现对电信号的非易失性多比特存储性能。The invention provides a micro/nano resistive variable memory, which can respond to any voltage within 1V to 10V without the need of gate voltage and special device structure, and store electrical signals differently according to the voltage between the electrodes at both ends. In the micro/nano resistive memory, the non-volatile multi-bit storage performance is realized. A micro/nano resistive variable memory of the present invention utilizes the trap energy level in the ZnO micro/nano wire doped with a single Sn element, and regulates the resistance of the device by applying an electric field to the electron filling state in the trap energy level, so as to realize the electric resistance. Signal non-volatile multi-bit storage capability.
图1示出的是本发明的微/纳米阻变存储器典型结构示意图依次包括绝缘基底101、单根Sn共掺杂的ZnO微/纳米线102、电极一103、电极二 104、导线一105、导线二106、封装材料107、函数功能发生器108。Figure 1 shows a schematic diagram of a typical structure of the micro/nano resistive variable memory of the present invention, including an insulating substrate 101, a single Sn co-doped ZnO micro/nano wire 102, electrode one 103, electrode two 104, wire one 105, Wire two 106 , packaging material 107 , and function generator 108 .
所述的绝缘基底101由氧化铝陶瓷基底、氮化铝陶瓷基底、氮化硅陶瓷基底任一材料构成。所述的单根Sn掺杂的ZnO微/纳米线102为ZnO晶格中含有Sn元素杂质缺陷的一维微/纳米线，其制备步骤为。The insulating substrate 101 is made of any material such as alumina ceramic substrate, aluminum nitride ceramic substrate, or silicon nitride ceramic substrate. The single Sn-doped ZnO micro/nano wire 102 is a one-dimensional micro/nano wire containing Sn element impurity defects in the ZnO lattice, and the preparation steps are as follows.
1、清洗并烘干刚玉陶瓷基片和陶瓷舟。1. Clean and dry the corundum ceramic substrate and ceramic boat.
2、按照4:1:2的质量比称取所需要的ZnO粉、SnO2粉和C粉作为蒸发源，在玛瑙钵中进行研磨，使其充分混合均勾。然后取3 g左右的混合原料作为蒸发源装入原料洁净的陶瓷舟中，将陶瓷舟缓慢推入到陶瓷管上风处，接着将装有陶瓷基片放入下风处，并保证装有混合物的陶瓷舟正好对准热电偶处，以便更好地控制温度，让其有效蒸发。2. Weigh the required ZnO powder, SnO2 powder and C powder according to the mass ratio of 4:1:2 as the evaporation source, and grind them in an agate bowl to make them fully mixed and uniform. Then take about 3 g of the mixed raw material as an evaporation source and put it into a ceramic boat with clean raw materials, slowly push the ceramic boat into the upwind of the ceramic tube, then put the ceramic substrate into the downwind place, and ensure that the mixture is filled The ceramic boat is aligned right at the thermocouple for better temperature control and efficient evaporation.
3、先向陶瓷管中预通入10 min的氮气，完毕后，将管式炉的设定到1100oC,调节电流使得电炉温度以50oC/min的速率开始升温，并持续通入氮气和氢气的混合气体，为了防止粉末被吹走需控制气流速率，保持稳定的气流量，为Sn掺杂ZnO纳米棒提供适宜的生长条件，升到指定温度后，保温3h。到时间后停止加热，在温度降到60 oC即可关闭气阀，冷却致室温后发现桂片上沉积了大量的白色产物。3. Pre-flow nitrogen into the ceramic tube for 10 minutes. After completion, set the tube furnace to 1100o C, adjust the current so that the temperature of the electric furnace starts to rise at a rate of 50o C/min, and continue to feed The mixed gas of nitrogen and hydrogen, in order to prevent the powder from being blown away, it is necessary to control the gas flow rate, maintain a stable gas flow, and provide suitable growth conditions for Sn-doped ZnO nanorods. After rising to the specified temperature, keep it warm for 3 hours. Stop heating after the time is up, the gas valve can be closed when the temperature drops to 60o C , and after cooling to room temperature, it is found that a large amount of white products are deposited on the cassia slices.
所述的金属电极一103、电极二 104，选自铝、银、铂、金。The first metal electrode 103 and the second electrode 104 are selected from aluminum, silver, platinum, and gold.
所述的封装层选自环氧树脂、氨基甲酸乙酯、聚二甲基硅氧烷、聚甲基丙烯酸甲酯中任意一种。The encapsulation layer is selected from any one of epoxy resin, urethane, polydimethylsiloxane and polymethyl methacrylate.
结合图1，本发明的一种微/纳米阻变存储器的制备步骤包括。Referring to FIG. 1 , the preparation steps of a micro/nano resistive variable memory of the present invention include.
1、绝缘基底101采用规格为20mmⅹ10mmⅹ1mm的氧化铝陶瓷基底，用无水乙醇及去离子水超声分别清洗3次。1. The insulating substrate 101 is made of an alumina ceramic substrate with a specification of 20mmⅹ10mmⅹ1mm, and is ultrasonically cleaned three times with absolute ethanol and deionized water respectively.
2、单根Sn掺杂的ZnO一维微/纳米线102采用直径为5µm长度为735µm的微/纳米线，分散Sn元素掺杂的ZnO一维微/纳米线102并横置于绝缘基底101上，在Sn元素掺杂的ZnO一维微/纳米线102两端分别焊接电极一103、电极二104，电极一、电极二为银浆。2. A single Sn-doped ZnO one-dimensional micro/nano wire 102 adopts a micro/nano wire with a diameter of 5 µm and a length of 735 µm, and the Sn-doped ZnO one-dimensional micro/nano wire 102 is dispersed and placed horizontally on the insulating substrate 101 Above, the first electrode 103 and the second electrode 104 are respectively welded on both ends of the ZnO one-dimensional micro/nano wire 102 doped with Sn element, and the first electrode and the second electrode are silver paste.
3、室温下待银浆干燥，在电极一103焊接铜线作为导线一105，电极二104焊接铜线作为导线一106，引出电路。3. Wait for the silver paste to dry at room temperature, weld copper wire on electrode one 103 as lead one 105, and weld copper wire on electrode two 104 as lead one 106, and lead out the circuit.
4、涂覆预先调配好的封装材料107聚二甲基硅氧烷(PDMS)，并放置于恒温加热面板上，升温至150℃固化2 h。4. Coat the pre-prepared packaging material 107 polydimethylsiloxane (PDMS), place it on a constant temperature heating panel, and raise the temperature to 150°C for 2 hours to cure.
5、将铜线引出的外电路与函数发生器108连接，完成热发电机的制备。5. Connect the external circuit led by the copper wire to the function generator 108 to complete the preparation of the thermal generator.
下面结合图2至图8分别介绍本发明的微/纳米阻变存储器在2V、4V、6V、8V、10V电压写入、存储、擦除及循环读写的方法The methods for writing, storing, erasing, and cyclically reading and writing the micro/nano resistive memory of the present invention at 2V, 4V, 6V, 8V, and 10V voltages are respectively introduced below in conjunction with Fig. 2 to Fig. 8
实施例1。Example 1.
图2为本发明的微/纳米阻变存储器在2V、4V、6V、8V、10V电压写入后，存储性能测试。将所述的微/纳米阻变存储器两端电极相连的函数发生器调至读取电压0.5V，随后将电压调至写入电压，写入电压为1V-10V内任意选取的2V、4V、6V、8V、10V，待电压信息写入后调回至读取电压0.5V。如图2所示，在电压2V、4V、6V、8V、10V写入后，所述的微/纳米阻变存储器具有不同的电阻状态。Sn掺杂的ZnO微/纳米线具有杂质能级、表面态、本征缺陷等陷阱能级，不同的写入电压能够填充不同深度的陷阱能级。当陷阱被电子填充后，所述的微/纳米阻变存储器的电阻状态发生改变。FIG. 2 shows the storage performance test of the micro/nano resistive memory of the present invention after writing in voltages of 2V, 4V, 6V, 8V, and 10V. Adjust the function generator connected to the electrodes at both ends of the micro/nano resistive variable memory to a reading voltage of 0.5V, and then adjust the voltage to a writing voltage, and the writing voltage is 2V, 4V, 6V, 8V, 10V, after the voltage information is written, adjust back to the read voltage of 0.5V. As shown in FIG. 2 , after writing voltages of 2V, 4V, 6V, 8V, and 10V, the micro/nano resistive memory has different resistance states. Sn-doped ZnO micro/nanowires have trap levels such as impurity levels, surface states, and intrinsic defects, and different write voltages can fill trap levels of different depths. When the trap is filled with electrons, the resistance state of the micro/nano resistive memory changes.
实施例2。Example 2.
图3为本发明的微/纳米阻变存储器在2V、4V、6V、8V、10V电压写入后，电流随时间变化图。具体为先将所述的微/纳米阻变存储器两端电极相连的函数发生器调至读取电压0.5V，随后将写入电压分别调至2V、4V、6V、8V、10V，待电压信息写入后调回至读取电压0.5V并测试器电流随时间增加的稳定性。如图3所示，在电压2V、4V、6V、8V、10V写入后，陷阱中的空穴被电子填充，撤去写入电压并施加读取电压，所述的微/纳米阻变存储器的对应特定的写入电压有特定的电阻状态，并且电阻状态可长时间被保持。当陷阱内的空穴被电子填充后，电子收到陷阱局域作用被限制在陷阱中，使得写入电压撤去后，电阻状态能够长时间保持住，实现了良好的存储稳定性。Fig. 3 is a diagram showing the change of current with time after the voltages of 2V, 4V, 6V, 8V and 10V are written in the micro/nano resistive memory of the present invention. Specifically, first adjust the function generator connected to the electrodes at both ends of the micro/nano resistive variable memory to a reading voltage of 0.5V, then adjust the writing voltage to 2V, 4V, 6V, 8V, and 10V respectively, and wait for the voltage information After writing, adjust back to the reading voltage of 0.5V and test the stability of the device current increasing with time. As shown in Figure 3, after the voltages of 2V, 4V, 6V, 8V, and 10V are written, the holes in the traps are filled with electrons, the write voltage is removed and the read voltage is applied, the micro/nano resistive variable memory There is a specific resistance state corresponding to a specific writing voltage, and the resistance state can be maintained for a long time. When the holes in the trap are filled with electrons, the electrons are localized by the trap and confined in the trap, so that the resistance state can be maintained for a long time after the writing voltage is removed, achieving good storage stability.
实施例3。Example 3.
图4至图8为本发明的微/纳米阻变存储器在写入电压为2V、4V、6V、8V、10V情况下的重复性读写性能测试。具体为：步骤一，将所述的微/纳米阻变存储器两端电极相连的函数发生器调至读取电压0.5V，随后将电压分别调至2V、4V、6V、8V、10V进行信息写入；步骤二，将微/纳米阻变存储器两端电压调回至电压0.5V读取信息；步骤三，将所述的微/纳米阻变存储器放置于70℃环境中进行信号擦除过程；步骤四，恢复室温，微/纳米阻变存储器的阻态恢复初始状态；重复循环步骤一到步骤四检测所述的微/纳米阻变存储器的重复性，除写入电压外，所有步骤中的读取电压均为0.5V的直流电压，图4至图8中虚线部分为测试过程中的操作电压。如图4至图8实线部分分别为用2V、4V、6V、8V、10V写入的微/纳米阻变存储器循环读写性能图。将电压写入后的微/纳米阻变存储器能长时间保存阻态，直到放置于70℃环境中擦除信号。Sn元素掺杂的ZnO微/纳米线能形成一系列的陷阱态。在写入电压下，陷阱中的空穴被电子填充，由于陷阱具有局域电子的作用，在写入电压撤去后，微/纳米阻变存储器能长时间保存阻态。将微/纳米阻变存储器放置于70℃环境中，陷阱中的电子受热后逸出陷阱，微/纳米阻变存储器的阻值状态恢复至初始状态，存储信号被擦除。所述的微/纳米阻变存储器对不同的写入电压具有可识别的存储性能和重复读写的性能，使得所述的微/纳米阻变存储器具有良好的重复利用性能。Figures 4 to 8 show the repeatable reading and writing performance tests of the micro/nano resistive memory of the present invention under the conditions of writing voltages of 2V, 4V, 6V, 8V and 10V. Specifically: step 1, adjust the function generator connected to the electrodes at both ends of the micro/nano resistive variable memory to a reading voltage of 0.5V, and then adjust the voltage to 2V, 4V, 6V, 8V, and 10V for information writing input; Step 2, adjusting the voltage across the micro/nano resistive variable memory back to a voltage of 0.5V to read information; Step 3, placing the micro/nano resistive variable memory in a 70°C environment for signal erasing; Step 4, return to room temperature, and the resistance state of the micro/nano resistive variable memory returns to the initial state; repeat the cycle from step 1 to step 4 to detect the repeatability of the micro/nano resistive variable memory, except for the write voltage, all steps The reading voltage is a DC voltage of 0.5V, and the dotted line in Figure 4 to Figure 8 is the operating voltage during the test. As shown in Figure 4 to Figure 8, the solid line parts are the cyclic reading and writing performance diagrams of the micro/nano resistive memory written with 2V, 4V, 6V, 8V, and 10V, respectively. After the voltage is written, the micro/nano resistive memory can keep the resistance state for a long time until it is placed in a 70°C environment to erase the signal. Sn doped ZnO micro/nanowires can form a series of trap states. Under the writing voltage, the holes in the traps are filled with electrons. Since the traps have the effect of localized electrons, the micro/nano resistive memory can keep the resistance state for a long time after the writing voltage is removed. The micro/nano resistive variable memory is placed in an environment of 70°C, the electrons in the trap escape from the trap after being heated, the resistance state of the micro/nano resistive variable memory returns to the initial state, and the stored signal is erased. The micro/nano resistive memory has identifiable storage performance and repeatable reading and writing performance for different write voltages, so that the micro/nano resistive memory has good reusability.
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