技术领域technical field
本发明属于半导体技术领域，特别是涉及一种集成无源元件转接板及其制备方法。The invention belongs to the technical field of semiconductors, and in particular relates to an integrated passive element adapter board and a preparation method thereof.
背景技术Background technique
传统无源器件采用分立式封装，一个封装中只包含一个电子元件。这种封装形式无法满足日益增长的低成本、高集成度的需求，因此集成无源器件得到了快速发展。利用薄膜技术在圆片上制作集成无源器件是一种具有潜力的集成无源器件制作方案。Traditional passive devices are packaged in discrete packages, containing only one electronic component in a package. This type of packaging cannot meet the growing demand for low cost and high integration, so integrated passive devices have been developed rapidly. Fabricating integrated passive devices on wafers using thin-film technology is a potential manufacturing scheme for integrated passive devices.
在未来几年，为了与3D-IC平行发展相适应，集成无源元件发展的另一趋势是集成到硅转接板中。集成硅转接板上的无源元件具有集成度高，性能好，设计和工艺也相对简单，同时可以兼容3D封装。以硅转接板为载体的3D封装可能成为未来电子器件封装的终极形式。In the next few years, in order to adapt to the parallel development of 3D-IC, another trend in the development of integrated passive components is to integrate into silicon interposers. The passive components on the integrated silicon interposer have high integration, good performance, relatively simple design and process, and are compatible with 3D packaging. 3D packaging with silicon interposer as the carrier may become the ultimate form of electronic device packaging in the future.
通过使用三维硅转接板实现2.5D集成是一种必要和现实的过渡方式。转接板由于其灵活性与兼容性，将得到快速发展和普遍应用，并将长期存在。然而，现有技术中的集成硅转接板中，电感线圈位于转接板的表面，且电感线圈与用于互连的电互连结构的成形与填充不能同步形成，不能满足小型化、低成本化的发展趋势。Achieving 2.5D integration through the use of 3D silicon interposers is a necessary and realistic transition. Due to its flexibility and compatibility, the adapter board will be developed rapidly and widely used, and will exist for a long time. However, in the integrated silicon interposer in the prior art, the inductance coil is located on the surface of the interposer, and the forming and filling of the inductance coil and the electrical interconnection structure used for interconnection cannot be formed synchronously, which cannot meet the requirements of miniaturization, low cost, etc. The development trend of costization.
发明内容Contents of the invention
鉴于以上所述现有技术的缺点，本发明提出了一种集成无源元件转接板及其制备方法，用于解决现有技术中集成硅转接板存在的不能满足小型化、低成本化的发展趋势的问题。In view of the shortcomings of the prior art described above, the present invention proposes an integrated passive component adapter board and its preparation method, which are used to solve the problems of the integrated silicon adapter board in the prior art that cannot meet miniaturization and low cost. development trend issues.
为实现上述目的的他相关目的，本发明提供一种集成无源元件转接板的制备方法，所述制备方法包括以下步骤：In order to achieve other related purposes of the above-mentioned purpose, the present invention provides a preparation method of an integrated passive component adapter board, the preparation method comprising the following steps:
1)提供硅基板，所述硅基板包括相对的第一表面及第二表面；1) providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite;
2)在所述硅基板的第一表面形成若干个第一盲孔及第二盲孔，所述第一盲孔的深度小于所述第二盲孔的深度；2) forming several first blind holes and second blind holes on the first surface of the silicon substrate, the depth of the first blind holes is smaller than the depth of the second blind holes;
3)在所述硅基板的第一表面、所述第一盲孔表面及所述第二盲孔表面形成绝缘保护层；3) forming an insulating protective layer on the first surface of the silicon substrate, the surface of the first blind hole, and the surface of the second blind hole;
4)在所述第一盲孔及所述第二盲孔内填充金属，分别形成电感线圈及电互连结构；4) filling metal in the first blind hole and the second blind hole to form an inductance coil and an electrical interconnection structure respectively;
5)在所述硅基板的第一表面形成电容；5) forming a capacitor on the first surface of the silicon substrate;
6)在所述硅基板的第一表面形成第一重新布线层，所述第一重新布线层经由所述电容将所述电感线圈与所述电互连结构相连接；6) forming a first rewiring layer on the first surface of the silicon substrate, the first rewiring layer connects the inductor coil to the electrical interconnection structure via the capacitor;
7)将所述硅基板的第二表面进行减薄，直至裸露出所述电互连结构；7) Thinning the second surface of the silicon substrate until the electrical interconnection structure is exposed;
8)在裸露的所述电互连结构表面及所述硅基板的第二表面形成第二重新布线层。8) Forming a second rewiring layer on the exposed surface of the electrical interconnection structure and the second surface of the silicon substrate.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤1)与步骤2)之间，还包括对所述硅基板进行预处理的步骤。As a preferred solution of the method for preparing an integrated passive component adapter board of the present invention, between step 1) and step 2), a step of pre-treating the silicon substrate is also included.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤2)中，在所述硅基板的第一表面形成第一盲孔及第二盲孔包括如下步骤：As a preferred solution of the preparation method of the integrated passive component adapter board of the present invention, in step 2), forming the first blind hole and the second blind hole on the first surface of the silicon substrate includes the following steps:
21)在所述硅基板的第一表面形成掩膜层；21) forming a mask layer on the first surface of the silicon substrate;
22)在所述掩膜层表面涂覆光刻胶层，图形化所述光刻胶层，图形化的光刻胶层定义出所述第一盲孔及所述第二盲孔的图形；22) Coating a photoresist layer on the surface of the mask layer, patterning the photoresist layer, and the patterned photoresist layer defines the patterns of the first blind hole and the second blind hole;
23)以所述图形化的光刻胶层为掩膜，将所述第一盲孔及所述第二盲孔的图形转移至所述掩膜层内；23) Using the patterned photoresist layer as a mask, transferring the patterns of the first blind hole and the second blind hole into the mask layer;
24)以所述掩膜层为掩膜，采用深反应离子刻蚀工艺在所述硅基板的第一表面形成所述第一盲孔及所述第二盲孔。24) Using the mask layer as a mask, a deep reactive ion etching process is used to form the first blind hole and the second blind hole on the first surface of the silicon substrate.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤3)中，采用热氧化工艺在所述硅基板的第一表面、所述第一盲孔表面及所述第二盲孔表面形成所述绝缘保护层。As a preferred solution of the preparation method of the integrated passive component adapter board of the present invention, in step 3), the first surface of the silicon substrate, the surface of the first blind hole, and the first surface of the first blind hole are formed by using a thermal oxidation process. The insulating protection layer is formed on the surfaces of the two blind holes.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤4)中，采用基于表面张力的液体合金填充工艺在所述第一盲孔及所述第二盲孔内填充金属。As a preferred solution for the preparation method of the integrated passive component adapter plate of the present invention, in step 4), a liquid alloy filling process based on surface tension is used to fill in the first blind hole and the second blind hole Metal.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤4)中，形成的电感线圈的形状为圆螺旋形、多边螺旋形或折线形。As a preferred solution of the method for preparing an integrated passive component adapter board of the present invention, in step 4), the shape of the formed inductance coil is circular spiral, polygonal spiral or zigzag.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤5)中，在所述硅基板的第一表面形成电容包括如下步骤：As a preferred solution of the preparation method of the integrated passive component adapter board of the present invention, in step 5), forming a capacitor on the first surface of the silicon substrate includes the following steps:
51)在所述硅基板的第一表面形成第一电极；51) forming a first electrode on the first surface of the silicon substrate;
52)在所述第一电极表面形成第一介质层；52) forming a first dielectric layer on the surface of the first electrode;
53)在位于所述电感线圈中心及一侧边缘的金属表面、所述电互连结构表面、所述第一介质层表面及所述第一电极表面形成第二电极。53) Forming a second electrode on the metal surface located at the center and one edge of the inductor coil, the surface of the electrical interconnection structure, the surface of the first dielectric layer, and the surface of the first electrode.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤6)中，在所述硅基板的第一表面形成第一重新布线层包括如下步骤：As a preferred solution of the preparation method of the integrated passive component adapter board of the present invention, in step 6), forming a first rewiring layer on the first surface of the silicon substrate includes the following steps:
61)在所述硅基板的第一表面形成第二介质层，所述第二介质层完全覆盖所述电容；61) forming a second dielectric layer on the first surface of the silicon substrate, the second dielectric layer completely covering the capacitor;
62)在所述第二介质层内形成第一开口，所述第一开口暴露出所述第二电极；62) forming a first opening in the second dielectric layer, the first opening exposing the second electrode;
63)在所述第一开口内及所述第二介质层表面形成所述第一重新布线层。63) Forming the first rewiring layer in the first opening and on the surface of the second dielectric layer.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤63)之后，还包括在所述第二介质层表面形成第三介质层的步骤，所述第三介质层完全覆盖位于所述第二介质层表面的所述第一重新布线层。As a preferred solution of the preparation method of the integrated passive component adapter board of the present invention, after step 63), it also includes the step of forming a third dielectric layer on the surface of the second dielectric layer, and the third dielectric layer is completely Covering the first rewiring layer on the surface of the second dielectric layer.
作为本发明的集成无源元件转接板的制备方法的一种优选方案，步骤8)中，在裸露的所述电互连结构表面及所述硅基板的第二表面形成第二重新布线层包括如下步骤：As a preferred solution of the preparation method of the integrated passive component adapter board of the present invention, in step 8), a second rewiring layer is formed on the exposed surface of the electrical interconnection structure and the second surface of the silicon substrate Including the following steps:
81)在所述硅基板的第二表面形成第四介质层；81) forming a fourth dielectric layer on the second surface of the silicon substrate;
82)在所述第四介质层内形成第二开口，所述第二开口暴露出所述电互连结构；82) forming a second opening in the fourth dielectric layer, the second opening exposing the electrical interconnection structure;
83)在所述第二开口内及所述第四介质层表面形成所述第二重新布线层。83) Forming the second rewiring layer in the second opening and on the surface of the fourth dielectric layer.
本发明还提供一种集成无源元件转接板，所述集成无源元件转接板包括：The present invention also provides an integrated passive component adapter board, which includes:
硅基板，所述硅基板包括第一表面及第二表面；a silicon substrate comprising a first surface and a second surface;
电感线圈，自所述硅基板的第一表面嵌入至所述硅基板内部；an inductance coil embedded into the silicon substrate from the first surface of the silicon substrate;
电互连结构，自所述硅基板的第一表面至第二表面贯穿所述硅基板；an electrical interconnection structure penetrating through the silicon substrate from the first surface to the second surface of the silicon substrate;
绝缘保护层，位于所述电感线圈与所述硅基板之间，及所述电互连结构与所述硅基板之间；an insulating protective layer located between the inductance coil and the silicon substrate, and between the electrical interconnection structure and the silicon substrate;
电容，位于所述硅基板的第一表面；a capacitor located on the first surface of the silicon substrate;
第一重新布线层，位于所述电容的表面，且经由所述电容将所述电感线圈与所述电互连结构相连接；a first redistribution layer located on the surface of the capacitor and connecting the inductor coil to the electrical interconnection structure via the capacitor;
第二重新布线层，位于所述硅基板的第二表面及延伸至所述硅基板的第二表面的所述电互连结构的表面。The second rewiring layer is located on the second surface of the silicon substrate and extends to the surface of the electrical interconnection structure on the second surface of the silicon substrate.
作为本发明的集成无源元件转接板的一种优选方案，所述电感线圈的形状为圆螺旋形、多边螺旋形或折线形。As a preferred solution of the integrated passive component adapter board of the present invention, the shape of the inductance coil is circular spiral, polygonal spiral or zigzag.
作为本发明的集成无源元件转接板的一种优选方案，所述电容包括第一电极、第一介质层及第二电极：As a preferred solution of the integrated passive component adapter board of the present invention, the capacitor includes a first electrode, a first dielectric layer and a second electrode:
所述第一电极位于所述硅基板的第一表面；The first electrode is located on the first surface of the silicon substrate;
所述第一介质层位于所述第一电极远离所述硅基板的表面；The first dielectric layer is located on the surface of the first electrode away from the silicon substrate;
所述第二电极位于所述电感线圈中心及一侧边缘的表面、所述电互连结构表面、所述第一介质层表面及所述第一电极表面。The second electrode is located on the surface of the center and one edge of the inductance coil, the surface of the electrical interconnection structure, the surface of the first dielectric layer, and the surface of the first electrode.
作为本发明的集成无源元件转接板的一种优选方案，所述集成无源元件转接板还包括第二介质层，所述第二介质层位于所述硅基板的第一表面，且完全覆盖所述电容；所述第一重新布线层自所述电容的表面延伸至所述第二介质层的表面。As a preferred solution of the integrated passive component adapter board of the present invention, the integrated passive element adapter board further includes a second dielectric layer, the second dielectric layer is located on the first surface of the silicon substrate, and completely covering the capacitor; the first rewiring layer extends from the surface of the capacitor to the surface of the second dielectric layer.
作为本发明的集成无源元件转接板的一种优选方案，所述集成无源元件转接板还包括第三介质层，所述第三介质层位于所述第二介质层远离所述硅基板的表面，且所述第三介质层完全覆盖位于所述第二介质层表面的所述第一重新布线层。As a preferred solution of the integrated passive component adapter board of the present invention, the integrated passive element adapter board further includes a third dielectric layer, and the third dielectric layer is located on the second dielectric layer away from the silicon the surface of the substrate, and the third dielectric layer completely covers the first rewiring layer on the surface of the second dielectric layer.
作为本发明的集成无源元件转接板的一种优选方案，所述集成无源元件转接板还包括第四介质层，所述第四介质层位于所述硅基板的第二表面；所述第二重新布线层自所述硅基板的第二表面及所述电互连结构的表面延伸至所述第四介质层的表面。As a preferred solution of the integrated passive component adapter board of the present invention, the integrated passive element adapter board further includes a fourth dielectric layer, and the fourth dielectric layer is located on the second surface of the silicon substrate; The second rewiring layer extends from the second surface of the silicon substrate and the surface of the electrical interconnection structure to the surface of the fourth dielectric layer.
如上所述，本发明的集成无源元件转接板及其制备方法，具有以下有益效果：在制备的过程中，用于形成电感线圈的第一盲孔及用于形成电互连结构的第二盲孔通过一步刻蚀工艺同时形成，且通过金属填充一次填充形成电感线圈及电互连结构，简化了制备工艺，降低了生产成本；同时，电感线圈嵌入在集成无源元件转接板内部，使得集成无源元件转接板更加小型化。As mentioned above, the integrated passive component adapter board and its preparation method of the present invention have the following beneficial effects: during the preparation process, the first blind hole used to form the inductor coil and the second blind hole used to form the electrical interconnection structure The two blind holes are formed simultaneously through a one-step etching process, and the inductance coil and the electrical interconnection structure are formed by filling the metal once, which simplifies the preparation process and reduces the production cost; at the same time, the inductance coil is embedded in the integrated passive component adapter board , making the integrated passive component adapter board more miniaturized.
附图说明Description of drawings
图1显示为本发明实施例一中提供的集成无源元件转接板的制备方法的流程图。FIG. 1 shows a flow chart of a method for preparing an integrated passive component adapter board provided in Embodiment 1 of the present invention.
图2至图17显示为本发明实施例一中的集成无源元件转接板的制备方法中各步骤的结构示意图。FIG. 2 to FIG. 17 are schematic structural diagrams of each step in the manufacturing method of the integrated passive component adapter board in Embodiment 1 of the present invention.
元件标号说明Component designation description
10 硅基板10 Silicon substrate
101 第一盲孔101 First blind hole
102 第二盲孔102 Second blind hole
11 掩膜层11 mask layer
111 第二通孔111 Second through hole
12 光刻胶层12 photoresist layer
121 第一通孔121 First through hole
13 绝缘保护层13 Insulation protective layer
14 电感线圈14 Inductor coil
15 电互连结构15 Electrical Interconnection Structure
16 电容16 capacitance
161 第一电极161 First electrode
162 第一介质层162 The first medium layer
163 第二电极163 Second electrode
17 第二介质层17 Second dielectric layer
171 第一开口171 First opening
18 第一重新布线层18 First redistribution layer
19 第三介质层19 The third dielectric layer
20 第四介质层20 The fourth dielectric layer
201 第二开口201 Second opening
21 第二重新布线层21 Second redistribution layer
具体实施方式Detailed ways
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1至图17需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。Please refer to FIG. 1 to FIG. 17. It should be noted that the illustrations provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only components related to the present invention are shown in the illustrations rather than actual implementation. The number, shape, and size of the components are drawn, and the type, quantity, and proportion of each component can be changed at will during actual implementation, and the layout of the components may also be more complicated.
实施例一Embodiment one
请参阅图1，本发明还提供一种集成无源元件转接板的制备方法，所述集成无源元件转接板的制备方法包括以下步骤：Please refer to Fig. 1, the present invention also provides a kind of preparation method of integrated passive component adapter plate, the preparation method of described integrated passive element adapter plate comprises the following steps:
1)提供硅基板，所述硅基板包括相对的第一表面及第二表面；1) providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite;
2)在所述硅基板的第一表面形成若干个第一盲孔及第二盲孔，所述第一盲孔的深度小于所述第二盲孔的深度；2) forming several first blind holes and second blind holes on the first surface of the silicon substrate, the depth of the first blind holes is smaller than the depth of the second blind holes;
3)在所述硅基板的第一表面、所述第一盲孔表面及所述第二盲孔表面形成绝缘保护层；3) forming an insulating protective layer on the first surface of the silicon substrate, the surface of the first blind hole, and the surface of the second blind hole;
4)在所述第一盲孔及所述第二盲孔内填充金属，分别形成电感线圈及电互连结构；4) filling metal in the first blind hole and the second blind hole to form an inductance coil and an electrical interconnection structure respectively;
5)在所述硅基板的第一表面形成电容；5) forming a capacitor on the first surface of the silicon substrate;
6)在所述硅基板的第一表面形成第一重新布线层，所述第一重新布线层经由所述电容将所述电感线圈与所述电互连结构相连接；6) forming a first rewiring layer on the first surface of the silicon substrate, the first rewiring layer connects the inductor coil to the electrical interconnection structure via the capacitor;
7)将所述硅基板的第二表面进行减薄，直至裸露出所述电互连结构；7) Thinning the second surface of the silicon substrate until the electrical interconnection structure is exposed;
8)在裸露的所述电互连结构表面及所述硅基板的第二表面形成第二重新布线层。8) Forming a second rewiring layer on the exposed surface of the electrical interconnection structure and the second surface of the silicon substrate.
在步骤1)中，请参阅图1中的S1步骤及图2，提供硅基板10，所述硅基板10包括相对的第一表面及第二表面。In step 1), referring to step S1 in FIG. 1 and FIG. 2 , a silicon substrate 10 is provided, and the silicon substrate 10 includes opposite first and second surfaces.
作为示例，所述硅基板10可以为高阻硅基板，以保证所述后续形成的无源元件及电互连结构的高频传输特性。所述硅基板10的厚度及阻值可以根据实际需要进行选择，优选地，本实施例中，所述硅基板10的厚度可以为但不仅限于420μm，所述硅基板10的阻值可以为但不仅限于1000Ω.cm。As an example, the silicon substrate 10 may be a high-resistance silicon substrate, so as to ensure the high-frequency transmission characteristics of the subsequently formed passive components and electrical interconnection structures. The thickness and resistance value of the silicon substrate 10 can be selected according to actual needs. Preferably, in this embodiment, the thickness of the silicon substrate 10 can be but not limited to 420 μm, and the resistance value of the silicon substrate 10 can be but Not limited to 1000Ω.cm.
作为示例，还包括对所述硅基板10进行预处理的步骤，所述预处理包括对所述硅基板10进行表面清洗，以去除其表面的杂质。As an example, a step of pre-processing the silicon substrate 10 is also included, and the pre-processing includes cleaning the surface of the silicon substrate 10 to remove impurities on the surface thereof.
在步骤2)中，请参阅图1中的S2步骤及图3至图6，在所述硅基板10的第一表面形成若干个第一盲孔101及第二盲孔102，所述第一盲孔101的深度小于所述第二盲孔102的深度。In step 2), referring to step S2 in FIG. 1 and FIG. 3 to FIG. 6, a plurality of first blind holes 101 and second blind holes 102 are formed on the first surface of the silicon substrate 10. The depth of the blind hole 101 is smaller than the depth of the second blind hole 102 .
作为示例，在所述硅基板10的第一表面形成第一盲孔101及第二盲孔102包括如下步骤：As an example, forming the first blind hole 101 and the second blind hole 102 on the first surface of the silicon substrate 10 includes the following steps:
21)在所述硅基板10的第一表面形成掩膜层11；优选地，本实施例中，在所述硅基板10的第一表面沉积一层氧化硅层作为所述掩膜层11，沉积的所述氧化硅层的厚度可以根据实际需要进行设定，在一示例中，所述氧化硅层的厚度可以为但不仅限于2μm；21) Forming a mask layer 11 on the first surface of the silicon substrate 10; preferably, in this embodiment, depositing a silicon oxide layer on the first surface of the silicon substrate 10 as the mask layer 11, The thickness of the deposited silicon oxide layer can be set according to actual needs. In one example, the thickness of the silicon oxide layer can be but not limited to 2 μm;
22)在所述掩膜层11表面涂覆光刻胶层12，图形化所述光刻胶层12，在所述光刻胶层12内形成与后续要形成的所述第一盲孔101及所述第二盲孔102相对应的第一通孔121，图形化的光刻胶层定义出所述第一盲孔101及所述第二盲孔102的图形，如图3所示；22) Coating a photoresist layer 12 on the surface of the mask layer 11, patterning the photoresist layer 12, and forming the first blind hole 101 to be formed in the photoresist layer 12 And the first through hole 121 corresponding to the second blind hole 102, the patterned photoresist layer defines the graphics of the first blind hole 101 and the second blind hole 102, as shown in Figure 3;
23)以所述图形化的光刻胶层为掩膜，将所述第一盲孔101及所述第二盲孔102的图形转移至所述掩膜层11内，如图4所示；具体的，可以采用氧化物刻蚀缓冲液(BOE)腐蚀所述掩膜层11，也可以采用刻蚀工艺刻蚀所述掩膜层11，以在所述掩膜层11内形成与所述第一通孔121相对应的第二通孔111，以将所述第一盲孔101及所述第二盲孔102的图形转移至所述掩膜层11内；去除所述光刻胶层12；23) Using the patterned photoresist layer as a mask, transferring the patterns of the first blind hole 101 and the second blind hole 102 into the mask layer 11, as shown in FIG. 4 ; Specifically, the mask layer 11 can be etched with an oxide etching buffer solution (BOE), or the mask layer 11 can be etched by an etching process, so as to form a The second through hole 111 corresponding to the first through hole 121, so as to transfer the pattern of the first blind hole 101 and the second blind hole 102 into the mask layer 11; remove the photoresist layer 12;
24)以所述掩膜层11为掩膜，采用深反应离子刻蚀工艺(DRIE)在所述硅基板10的第一表面形成所述第一盲孔101及所述第二盲孔102，如图5所示；具体的，所述第一盲孔101及所述第二盲孔102的深度及孔径可以根据实际需要进行设定，优选地，所述第一盲孔101及所述第二盲孔102的孔径为40μm～100μm；更为优选地，本实施例中，所述第一盲孔101及所述第二盲孔102的孔径为60μm，所述第二盲孔102的深度为150μm。24) using the mask layer 11 as a mask, forming the first blind hole 101 and the second blind hole 102 on the first surface of the silicon substrate 10 by using a deep reactive ion etching process (DRIE), As shown in Figure 5; specifically, the depth and diameter of the first blind hole 101 and the second blind hole 102 can be set according to actual needs, preferably, the first blind hole 101 and the second blind hole 101 The diameter of the second blind hole 102 is 40 μm to 100 μm; more preferably, in this embodiment, the diameter of the first blind hole 101 and the second blind hole 102 is 60 μm, and the depth of the second blind hole 102 is is 150 μm.
作为示例，步骤24)之后，还包括去除所述掩膜层11的步骤，如图6所示。As an example, after step 24), a step of removing the mask layer 11 is also included, as shown in FIG. 6 .
在步骤3)中，请参阅图1中的S3步骤及图7，在所述硅基板10的第一表面、所述第一盲孔101表面及所述第二盲孔102表面形成绝缘保护层13。In step 3), referring to step S3 in FIG. 1 and FIG. 7, an insulating protective layer is formed on the first surface of the silicon substrate 10, the surface of the first blind hole 101 and the surface of the second blind hole 102. 13.
作为示例，采用热氧化工艺在所述硅基板10的第一表面、所述第一盲孔101的侧壁与底部及所述第二盲孔102的侧壁与底部形成氧化硅层作为所述绝缘保护层13。所述绝缘保护层13的厚度可以根据实际需要进行设定，优选地，本实施例中，所述绝缘保护层13的厚度可以为但不仅限于2μm。As an example, a silicon oxide layer is formed on the first surface of the silicon substrate 10, the sidewall and bottom of the first blind hole 101, and the sidewall and bottom of the second blind hole 102 by a thermal oxidation process as the Insulation protection layer 13. The thickness of the insulating protection layer 13 can be set according to actual needs. Preferably, in this embodiment, the thickness of the insulating protection layer 13 can be but not limited to 2 μm.
在步骤4)中，请参阅图1中的S4步骤及图8，在所述第一盲孔101及所述第二盲孔102内填充金属，分别形成电感线圈14及电互连结构15。In step 4), referring to step S4 in FIG. 1 and FIG. 8 , metal is filled in the first blind hole 101 and the second blind hole 102 to form the inductor coil 14 and the electrical interconnection structure 15 respectively.
作为示例，采用基于表面张力的液体合金填充工艺在所述第一盲孔101及所述第二盲孔102内填充金属；具体的，先通过压力差将位于一金属槽中的金属吸入到所述第一盲孔101及所述第二盲孔102内，然后根据表面张力原理将已填充在所述第一盲孔101及所述第二盲孔102内的金属与所述金属槽中的金属切断，整个填充过程填充速度比较快，耗时较短，且可实现对所述第一盲孔101及所述第二盲孔102的一次填充，简化了制备工艺，降低了成本。As an example, a liquid alloy filling process based on surface tension is used to fill the first blind hole 101 and the second blind hole 102 with metal; In the first blind hole 101 and the second blind hole 102, and then according to the surface tension principle, the metal filled in the first blind hole 101 and the second blind hole 102 and the metal in the metal slot The metal is cut off, the filling speed of the whole filling process is relatively fast, the time consumption is short, and the first blind hole 101 and the second blind hole 102 can be filled once, which simplifies the manufacturing process and reduces the cost.
作为示例，在所述第一盲孔101及所述第二盲孔102内填充的金属可以为但不仅限于锡。As an example, the metal filled in the first blind hole 101 and the second blind hole 102 may be but not limited to tin.
作为示例，形成的所述电感线圈14的形状可以为圆螺旋形、多边螺旋形或折线形；优选地，本实施例中，所述电感线圈14的形状可以为但不仅限于阿基米德螺旋形，将所述电感线圈14的形状选为阿基米德螺旋形，使得其过渡光滑，高频损耗小。所述电感线圈14的宽度可以根据实际需要进行选定，优选地，所述电感线圈14的宽度为10μm～30μm，更为优选地，所述电感线圈14的宽度为20μm。As an example, the shape of the formed induction coil 14 can be circular spiral, polygonal spiral or zigzag; preferably, in this embodiment, the shape of the induction coil 14 can be but not limited to Archimedes spiral The shape of the inductance coil 14 is selected as an Archimedes spiral, so that its transition is smooth and the high frequency loss is small. The width of the inductance coil 14 can be selected according to actual needs. Preferably, the width of the inductance coil 14 is 10 μm˜30 μm, more preferably, the width of the inductance coil 14 is 20 μm.
在步骤5)中，请参阅图1中的S5步骤及图9至图11，在所述硅基板10的第一表面形成电容16。In step 5), referring to step S5 in FIG. 1 and FIG. 9 to FIG. 11 , a capacitor 16 is formed on the first surface of the silicon substrate 10 .
步骤5)中，在所述硅基板10的第一表面形成电容16包括如下步骤：In step 5), forming the capacitor 16 on the first surface of the silicon substrate 10 includes the following steps:
51)在所述硅基板10的第一表面形成第一电极161，如图9所示；具体的，首先，在所述硅基板10的第一表面溅射一层TiW/Cu金属层，所述TiW/Cu金属层的中各层的厚度可以根据实际需要设定，优选地，本实施例中，所述TiW层的厚度可以为但不仅限于50nm，所述Cu层的厚度可以为但不仅限于350nm；其次，在所述金属层表面涂覆光刻胶层，采用光刻工艺图形化所述光刻胶层，以定义出所述第一电极161的图形；然后，以所述图形化的光刻胶层作为掩膜，通过离子束刻蚀(Ion Beam)工艺刻蚀所述金属层以形成所述第一电极161；最后，去除所述光刻胶层；需要说明的是，所述第一电极161可以位于所述硅基板10第一表面的任意位置，但必须确保所述第一电极161不与所述电互连结构15相接触；51) Form a first electrode 161 on the first surface of the silicon substrate 10, as shown in FIG. 9; specifically, first, sputter a TiW/Cu metal layer on the first surface of the silicon substrate 10, so that The thickness of each layer in the TiW/Cu metal layer can be set according to actual needs. Preferably, in this embodiment, the thickness of the TiW layer can be but not limited to 50nm, and the thickness of the Cu layer can be but not only limited to 350nm; secondly, a photoresist layer is coated on the surface of the metal layer, and the photoresist layer is patterned by a photolithography process to define the pattern of the first electrode 161; then, the patterned The photoresist layer is used as a mask, and the metal layer is etched by an ion beam etching (Ion Beam) process to form the first electrode 161; finally, the photoresist layer is removed; it should be noted that the The first electrode 161 can be located at any position on the first surface of the silicon substrate 10, but it must be ensured that the first electrode 161 is not in contact with the electrical interconnection structure 15;
52)在所述第一电极161表面形成第一介质层162，如图10所示；具体的，采用PECVD(等离子体增强化学气相沉积法)沉积SiN层，采用光刻刻蚀工艺刻蚀所述SiN层以形成所述第一介质层162；所述第一介质层162的宽度小于所述第一电极161的宽度；52) Form a first dielectric layer 162 on the surface of the first electrode 161, as shown in FIG. SiN layer to form the first dielectric layer 162; the width of the first dielectric layer 162 is smaller than the width of the first electrode 161;
53)在位于所述电感线圈14中心及一侧边缘的金属表面、所述电互连结构15表面、所述第一介质层162表面及所述第一电极161表面形成第二电极163，如图11所示；具体的，首先，在步骤52)得到的结构表面溅射一层TiW/Cu金属层，所述TiW/Cu金属层的中各层的厚度可以根据实际需要设定，优选地，本实施例中，所述TiW层的厚度可以为但不仅限于50nm，所述Cu层的厚度可以为但不仅限于350nm；其次，在所述金属层表面涂覆光刻胶层，采用光刻工艺图形化所述光刻胶层，以定义出所述第二电极163的图形；然后，以所述图形化的光刻胶层作为掩膜，通过离子束刻蚀(Ion Beam)工艺刻蚀所述金属层以形成所述第二电极163；最后，去除所述光刻胶层。需要说明的是，由于所述电感线圈14的形状为阿基米德螺旋状，所述电感线圈14的一端位于其中心，另一端位于其一侧边缘，所述第二电极163分别与所述电感线圈14位于其中心的一端及位于其一侧边缘的一端相连接。53) Form a second electrode 163 on the metal surface located at the center and one edge of the inductance coil 14, the surface of the electrical interconnection structure 15, the surface of the first dielectric layer 162, and the surface of the first electrode 161, such as Shown in Fig. 11; Concretely, at first, in step 52) the structure surface that obtains sputters one layer of TiW/Cu metal layer, the thickness of each layer in the described TiW/Cu metal layer can be set according to actual needs, preferably , in this embodiment, the thickness of the TiW layer can be but not limited to 50nm, the thickness of the Cu layer can be but not limited to 350nm; secondly, a photoresist layer is coated on the surface of the metal layer, and photolithography is used to The photoresist layer is patterned by a process to define the pattern of the second electrode 163; then, using the patterned photoresist layer as a mask, the ion beam etching (Ion Beam) process is used to etch the metal layer to form the second electrode 163; finally, remove the photoresist layer. It should be noted that, since the shape of the inductance coil 14 is an Archimedean spiral, one end of the inductance coil 14 is located at its center, and the other end is located at one side edge thereof, and the second electrode 163 is respectively connected to the One end of the inductance coil 14 located at its center is connected to one end located at its side edge.
在步骤6)中，请参阅图1中的S6步骤及图12至图13，在所述硅基板10的第一表面形成第一重新布线层18，所述第一重新布线层18经由所述电容16将所述电感线圈14与所述电互连结构15相连接。In step 6), please refer to step S6 in FIG. 1 and FIG. 12 to FIG. A capacitor 16 connects the inductive coil 14 with the electrical interconnection structure 15 .
作为示例，在所述硅基板10的第一表面形成第一重新布线层18包括如下步骤：As an example, forming the first rewiring layer 18 on the first surface of the silicon substrate 10 includes the following steps:
61)在所述硅基板10的第一表面形成第二介质层17，所述第二介质层17完全覆盖所述电容16；具体的，在所述硅基板10的第一表面旋涂BCB(苯并环丁烯)或PI(聚酰亚胺)作为所述第二介质层17；所述第二介质层17的厚度可以根据实际需要设定，优选地，本实施例中，所述第二介质层17的厚度可以为但不仅限于10μm；61) Form a second dielectric layer 17 on the first surface of the silicon substrate 10, and the second dielectric layer 17 completely covers the capacitor 16; specifically, spin-coat BCB on the first surface of the silicon substrate 10 ( benzocyclobutene) or PI (polyimide) as the second dielectric layer 17; the thickness of the second dielectric layer 17 can be set according to actual needs, preferably, in the present embodiment, the first The thickness of the second dielectric layer 17 can be but not limited to 10 μm;
62)在所述第二介质层17内形成第一开口171，所述第一开口171暴露出所述第二电极163，如图12所示；具体的，采用光刻刻蚀工艺在所述第二介质层17内形成所述第一开口171，而后采用高温固化所述第二介质层17；62) Form a first opening 171 in the second dielectric layer 17, and the first opening 171 exposes the second electrode 163, as shown in FIG. 12; forming the first opening 171 in the second dielectric layer 17, and then curing the second dielectric layer 17 by high temperature;
63)在所述第一开口171内及所述第二介质层17表面形成所述第一重新布线层18，如图13所示；具体的，首先，在所述第二介质层17表面溅射种子层，并在所述种子层表面涂覆光刻胶层；其次，图形化所述光刻胶层及所述溅射种子层，在所述光刻胶层及所述溅射种子层内定义出所述第一重新布线层18的图形；然后，依据所述光刻胶层及所述溅射种子层电镀铜以形成所述第一重新布线层18，所述第一重新布线层18的厚度可以根据实际需要进行选择，优选地，所述第一重新布线层18的厚度为1μm～15μm，更为优选地，本实施例中，所述第一重新布线层18的厚度为7μm；最后，去除所述光刻胶层及所述溅射种子层。63) Form the first rewiring layer 18 in the first opening 171 and on the surface of the second dielectric layer 17, as shown in FIG. 13; specifically, first, sputter Sputtering the seed layer, and coating a photoresist layer on the surface of the seed layer; secondly, patterning the photoresist layer and the sputtering seed layer, and coating the photoresist layer and the sputtering seed layer Define the pattern of the first rewiring layer 18; then, electroplate copper according to the photoresist layer and the sputtering seed layer to form the first rewiring layer 18, the first rewiring layer The thickness of 18 can be selected according to actual needs, preferably, the thickness of the first rewiring layer 18 is 1 μm to 15 μm, more preferably, in this embodiment, the thickness of the first rewiring layer 18 is 7 μm ; Finally, remove the photoresist layer and the sputtering seed layer.
作为示例，请参阅图14，步骤63)之后，还包括在所述第二介质层17表面形成第三介质层19的步骤，所述第三介质层19完全覆盖位于所述第二介质层17表面的所述第一重新布线层18；在所述第二介质层17表面旋涂BCB(苯并环丁烯)或PI(聚酰亚胺)作为所述第三介质层19；所述第三介质层19的厚度可以根据实际需要设定，优选地，所述第三介质层19的厚度可以为1μm～3μm，更为优选地，本实施例中，所述第三介质层19的厚度可以为但不仅限于2μm。As an example, please refer to FIG. 14, after step 63), it also includes the step of forming a third dielectric layer 19 on the surface of the second dielectric layer 17, and the third dielectric layer 19 completely covers the second dielectric layer 17. The first rewiring layer 18 on the surface; spin-coat BCB (benzocyclobutene) or PI (polyimide) on the surface of the second dielectric layer 17 as the third dielectric layer 19; The thickness of the three dielectric layers 19 can be set according to actual needs. Preferably, the thickness of the third dielectric layer 19 can be 1 μm to 3 μm. More preferably, in this embodiment, the thickness of the third dielectric layer 19 It can be but not limited to 2 μm.
在步骤7)中，请参阅图1中的S7步骤及图15，将所述硅基板10的第二表面进行减薄，直至裸露出所述电互连结构15。In step 7), referring to step S7 in FIG. 1 and FIG. 15 , the second surface of the silicon substrate 10 is thinned until the electrical interconnection structure 15 is exposed.
作为示例，采用化学机械抛光工艺对所述硅基板10的第二表面进行减薄。As an example, a chemical mechanical polishing process is used to thin the second surface of the silicon substrate 10 .
在步骤8)中，请参阅图1中的S8步骤及图16至图17，在裸露的所述电互连结构15表面及所述硅基板10的第二表面形成第二重新布线层21。In step 8), referring to step S8 in FIG. 1 and FIG. 16 to FIG. 17 , a second rewiring layer 21 is formed on the exposed surface of the electrical interconnection structure 15 and the second surface of the silicon substrate 10 .
作为示例，在裸露的所述电互连结构15表面及所述硅基板10的第二表面形成第二重新布线层21包括如下步骤：As an example, forming the second rewiring layer 21 on the exposed surface of the electrical interconnection structure 15 and the second surface of the silicon substrate 10 includes the following steps:
81)在所述硅基板10的第二表面形成第四介质层20；具体的，在所述硅基板10的第二表面旋涂BCB(苯并环丁烯)或PI(聚酰亚胺)作为所述第四介质层20；所述第四介质层20的厚度可以根据实际需要设定，优选地，本实施例中，所述第四介质层20的厚度可以为但不仅限于10μm；81) Form a fourth dielectric layer 20 on the second surface of the silicon substrate 10; specifically, spin-coat BCB (benzocyclobutene) or PI (polyimide) on the second surface of the silicon substrate 10 As the fourth dielectric layer 20; the thickness of the fourth dielectric layer 20 can be set according to actual needs, preferably, in this embodiment, the thickness of the fourth dielectric layer 20 can be but not limited to 10 μm;
62)在所述第四介质层20内形成第二开口201，所述第二开口201暴露出所述电互连结构15，如图16所示；具体的，采用光刻刻蚀工艺在所述第四介质层20内形成所述第二开口201，而后采用高温固化所述第四介质层20；62) Form a second opening 201 in the fourth dielectric layer 20, and the second opening 201 exposes the electrical interconnection structure 15, as shown in FIG. 16; Forming the second opening 201 in the fourth dielectric layer 20, and then curing the fourth dielectric layer 20 at high temperature;
63)在所述第二开口201内及所述第四介质层20表面形成所述第二重新布线层21，如图17所示；具体的，首先，在所述第四介质层20表面溅射种子层，并在所述种子层表面涂覆光刻胶层；其次，图形化所述光刻胶层及所述溅射种子层，在所述光刻胶层及所述溅射种子层内定义出所述第二重新布线层21的图形；然后，依据所述光刻胶层及所述溅射种子层电镀铜以形成所述第二重新布线层21，所述第二重新布线层21的厚度可以根据实际需要进行选择，优选地，所述第二重新布线层21的厚度为1μm～15μm，更为优选地，本实施例中，所述第二重新布线层21的厚度为7μm；最后，去除所述光刻胶层及所述溅射种子层。63) Form the second rewiring layer 21 in the second opening 201 and on the surface of the fourth dielectric layer 20, as shown in FIG. 17; specifically, first, sputter Sputtering the seed layer, and coating a photoresist layer on the surface of the seed layer; secondly, patterning the photoresist layer and the sputtering seed layer, and coating the photoresist layer and the sputtering seed layer Define the pattern of the second rewiring layer 21; then, electroplating copper according to the photoresist layer and the sputtering seed layer to form the second rewiring layer 21, the second rewiring layer The thickness of 21 can be selected according to actual needs, preferably, the thickness of the second rewiring layer 21 is 1 μm to 15 μm, more preferably, in this embodiment, the thickness of the second rewiring layer 21 is 7 μm ; Finally, remove the photoresist layer and the sputtering seed layer.
实施例二Embodiment two
请继续参阅图17，本发明还提供一种集成无源元件转接板，所述集成无源元件转接板由实施例一中所述的制备方法制备而得到，所述集成无源元件转接板包括：硅基板10，所述硅基板10包括第一表面及第二表面；电感线圈14，所述电感线圈14自所述硅基板10的第一表面嵌入至所述硅基板10内部；电互连结构15，所述电互连结构15自所述硅基板10的第一表面至第二表面贯穿所述硅基板10；绝缘保护层13，所述绝缘保护层13位于所述电感线圈14与所述硅基板10之间，及所述电互连结构15与所述硅基板10之间；电容16，所述电容16位于所述硅基板10的第一表面；第一重新布线层18，所述第一重新布线层18位于所述电容16的表面，且经由所述电容16将所述电感线圈14与所述电互连结构15相连接；第二重新布线层21，所述第二重新布线层21位于所述硅基板10的第二表面及延伸至所述硅基板10的第二表面的所述电互连结构15的表面。Please continue to refer to Figure 17, the present invention also provides an integrated passive component adapter board, which is prepared by the preparation method described in Embodiment 1, and the integrated passive component adapter board The connecting board includes: a silicon substrate 10, the silicon substrate 10 includes a first surface and a second surface; an inductance coil 14, the inductance coil 14 is embedded into the interior of the silicon substrate 10 from the first surface of the silicon substrate 10; An electrical interconnection structure 15, the electrical interconnection structure 15 penetrates the silicon substrate 10 from the first surface to the second surface of the silicon substrate 10; an insulating protection layer 13, the insulating protection layer 13 is located on the inductance coil 14 and the silicon substrate 10, and between the electrical interconnection structure 15 and the silicon substrate 10; capacitor 16, the capacitor 16 is located on the first surface of the silicon substrate 10; the first rewiring layer 18, the first rewiring layer 18 is located on the surface of the capacitor 16, and connects the inductor coil 14 to the electrical interconnection structure 15 through the capacitor 16; the second rewiring layer 21, the The second redistribution layer 21 is located on the second surface of the silicon substrate 10 and the surface of the electrical interconnection structure 15 extending to the second surface of the silicon substrate 10 .
作为示例，所述硅基板10可以为高阻硅基板，以保证所述后续形成的无源元件及电互连结构的高频传输特性。所述硅基板10的厚度及阻值可以根据实际需要进行选择，优选地，本实施例中，所述硅基板10的厚度可以为但不仅限于420μm，所述硅基板10的阻值可以为但不仅限于1000Ω.cm。As an example, the silicon substrate 10 may be a high-resistance silicon substrate, so as to ensure the high-frequency transmission characteristics of the subsequently formed passive components and electrical interconnection structures. The thickness and resistance value of the silicon substrate 10 can be selected according to actual needs. Preferably, in this embodiment, the thickness of the silicon substrate 10 can be but not limited to 420 μm, and the resistance value of the silicon substrate 10 can be but Not limited to 1000Ω.cm.
作为示例，所述电感线圈14的形状可以为圆螺旋形、多边螺旋形或折线形；优选地，本实施例中，所述电感线圈14的形状可以为但不仅限于阿基米德螺旋形，将所述电感线圈14的形状选为阿基米德螺旋形，使得其过渡光滑，高频损耗小。所述电感线圈14的宽度可以根据实际需要进行选定，优选地，所述电感线圈14的宽度为10μm～30μm，更为优选地，所述电感线圈14的宽度为20μm。As an example, the shape of the induction coil 14 can be circular spiral, polygonal spiral or zigzag; preferably, in this embodiment, the shape of the induction coil 14 can be but not limited to the Archimedes spiral, The shape of the inductance coil 14 is selected as an Archimedes spiral, so that its transition is smooth and the high frequency loss is small. The width of the inductance coil 14 can be selected according to actual needs. Preferably, the width of the inductance coil 14 is 10 μm˜30 μm, more preferably, the width of the inductance coil 14 is 20 μm.
作为示例，所述电容16包括第一电极161、第一介质层162及第二电极163：所述第一电极16位于所述硅基板10的第一表面；所述第一介质层162位于所述第一电极161远离所述硅基板10的表面；所述第二电极163位于所述电感线圈14中心及一侧边缘的表面、所述电互连结构15表面、所述第一介质层162表面及所述第一电极161表面。As an example, the capacitor 16 includes a first electrode 161, a first dielectric layer 162 and a second electrode 163: the first electrode 16 is located on the first surface of the silicon substrate 10; the first dielectric layer 162 is located on the The first electrode 161 is away from the surface of the silicon substrate 10; the second electrode 163 is located on the surface of the center and one edge of the inductance coil 14, the surface of the electrical interconnection structure 15, and the first dielectric layer 162 surface and the surface of the first electrode 161.
作为示例，所述第一电极161及所述第二电极163的材料均为层TiW/Cu金属层，所述TiW/Cu金属层的中各层的厚度可以根据实际需要设定，优选地，本实施例中，所述TiW层的厚度可以为但不仅限于50nm，所述Cu层的厚度可以为但不仅限于350nm。As an example, the material of the first electrode 161 and the second electrode 163 is a TiW/Cu metal layer, and the thickness of each layer in the TiW/Cu metal layer can be set according to actual needs. Preferably, In this embodiment, the thickness of the TiW layer may be but not limited to 50 nm, and the thickness of the Cu layer may be but not limited to 350 nm.
需要说明的是，所述第一电极161可以位于所述硅基板10第一表面的任意位置，但必须确保所述第一电极161不与所述电互连结构15相接触。It should be noted that the first electrode 161 can be located at any position on the first surface of the silicon substrate 10 , but it must be ensured that the first electrode 161 does not contact the electrical interconnection structure 15 .
作为示例，所述第一重新布线层18及所述第二重新布线层21的材料均可以为但不仅限于铜，所述第一重新布线层18及所述第二重新布线层21的厚度可以根据实际需要进行选择，优选地，所述第一重新布线层18及所述第二重新布线层21的厚度为1μm～15μm，更为优选地，本实施例中，所述第一重新布线层18及所述第二重新布线层21的厚度为7μm。As an example, the material of the first rewiring layer 18 and the second rewiring layer 21 can be but not limited to copper, and the thickness of the first rewiring layer 18 and the second rewiring layer 21 can be Select according to actual needs. Preferably, the thickness of the first rewiring layer 18 and the second rewiring layer 21 is 1 μm to 15 μm. More preferably, in this embodiment, the first rewiring layer 18 and the second rewiring layer 21 have a thickness of 7 μm.
作为示例，所述集成无源元件转接板还包括第二介质层17，所述第二介质层17位于所述硅基板10的第一表面，且完全覆盖所述电容16；所述第一重新布线层18自所述电容16的表面延伸至所述第二介质层17的表面。As an example, the integrated passive component adapter board further includes a second dielectric layer 17, the second dielectric layer 17 is located on the first surface of the silicon substrate 10, and completely covers the capacitor 16; The rewiring layer 18 extends from the surface of the capacitor 16 to the surface of the second dielectric layer 17 .
作为示例，所述第二介质层17的材料可以为BCB(苯并环丁烯)或PI(聚酰亚胺)；所述第二介质层17的厚度可以根据实际需要设定，优选地，本实施例中，所述第二介质层17的厚度可以为但不仅限于10μm。As an example, the material of the second dielectric layer 17 can be BCB (benzocyclobutene) or PI (polyimide); the thickness of the second dielectric layer 17 can be set according to actual needs, preferably, In this embodiment, the thickness of the second dielectric layer 17 may be but not limited to 10 μm.
作为示例，所述集成无源元件转接板还包括第三介质层19，所述第三介质层19位于所述第二介质层17远离所述硅基板10的表面，且所述第三介质层19完全覆盖位于所述第二介质层17表面的所述第一重新布线层18。As an example, the integrated passive component adapter board further includes a third dielectric layer 19, the third dielectric layer 19 is located on the surface of the second dielectric layer 17 away from the silicon substrate 10, and the third dielectric layer 19 Layer 19 completely covers the first rewiring layer 18 on the surface of the second dielectric layer 17 .
作为示例，所述第三介质层19的材料可以为BCB(苯并环丁烯)或PI(聚酰亚胺)；所述第三介质层19的厚度可以根据实际需要设定，优选地，所述第三介质层19的厚度可以为1μm～3μm，更为优选地，本实施例中，所述第三介质层19的厚度可以为但不仅限于2μm。As an example, the material of the third dielectric layer 19 can be BCB (benzocyclobutene) or PI (polyimide); the thickness of the third dielectric layer 19 can be set according to actual needs, preferably, The thickness of the third dielectric layer 19 may be 1 μm˜3 μm, more preferably, in this embodiment, the thickness of the third dielectric layer 19 may be but not limited to 2 μm.
作为示例，所述集成无源元件转接板还包括第四介质层20，所述第四介质层20位于所述硅基板10的第二表面；所述第二重新布线层21自所述硅基板10的第二表面及所述电互连结构15的表面延伸至所述第四介质层20的表面。As an example, the integrated passive component adapter board further includes a fourth dielectric layer 20, and the fourth dielectric layer 20 is located on the second surface of the silicon substrate 10; the second rewiring layer 21 is formed from the silicon The second surface of the substrate 10 and the surface of the electrical interconnection structure 15 extend to the surface of the fourth dielectric layer 20 .
作为示例，所述第四介质层20的材料可以为BCB(苯并环丁烯)或PI(聚酰亚胺)；所述第四介质层20的厚度可以根据实际需要设定，优选地，本实施例中，所述第四介质层20的厚度可以为但不仅限于10μm。As an example, the material of the fourth dielectric layer 20 can be BCB (benzocyclobutene) or PI (polyimide); the thickness of the fourth dielectric layer 20 can be set according to actual needs, preferably, In this embodiment, the thickness of the fourth dielectric layer 20 may be but not limited to 10 μm.
综上所述，本发明提供一种集成无源元件转接板及其制备方法，所述集成无源元件转接板的制备方法包括以下步骤：1)提供硅基板，所述硅基板包括相对的第一表面及第二表面；2)在所述硅基板的第一表面形成若干个第一盲孔及第二盲孔，所述第一盲孔的深度小于所述第二盲孔的深度；3)在所述硅基板的第一表面、所述第一盲孔表面及所述第二盲孔表面形成绝缘保护层；4)在所述第一盲孔及所述第二盲孔内填充金属，分别形成电感线圈及电互连结构；5)在所述硅基板的第一表面形成电容；6)在所述硅基板的第一表面形成第一重新布线层，所述第一重新布线层经由所述电容将所述电感线圈与所述电互连结构相连接；7)将所述硅基板的第二表面进行减薄，直至裸露出所述电互连结构；8)在裸露的所述电互连结构表面及所述硅基板的第二表面形成第二重新布线层。在制备的过程中，用于形成电感线圈的第一盲孔及用于形成电互连结构的第二盲孔通过一步刻蚀工艺同时形成，且通过金属填充一次填充形成电感线圈及电互连结构，简化了制备工艺，降低了生产成本；同时，电感线圈嵌入在集成无源元件转接板内部，使得集成无源元件转接板更加小型化。In summary, the present invention provides an integrated passive component adapter board and a preparation method thereof. The preparation method of the integrated passive element adapter board includes the following steps: 1) providing a silicon substrate, and the silicon substrate includes a relatively 2) forming several first blind holes and second blind holes on the first surface of the silicon substrate, the depth of the first blind holes is smaller than the depth of the second blind holes ; 3) forming an insulating protective layer on the first surface of the silicon substrate, the surface of the first blind hole and the surface of the second blind hole; 4) in the first blind hole and the second blind hole Filling metal to form an inductor coil and an electrical interconnection structure respectively; 5) forming a capacitor on the first surface of the silicon substrate; 6) forming a first rewiring layer on the first surface of the silicon substrate, and the first rewiring layer The wiring layer connects the inductor coil to the electrical interconnection structure via the capacitor; 7) thinning the second surface of the silicon substrate until the electrical interconnection structure is exposed; 8) after the exposed The surface of the electrical interconnect structure and the second surface of the silicon substrate form a second rewiring layer. During the manufacturing process, the first blind hole for forming the inductance coil and the second blind hole for forming the electrical interconnection structure are simultaneously formed through a one-step etching process, and the inductance coil and the electrical interconnection are formed by filling with metal once. The structure simplifies the preparation process and reduces the production cost; at the same time, the inductance coil is embedded in the integrated passive component adapter board, making the integrated passive element adapter board more miniaturized.
上述实施例仅例示性说明本发明的原理的功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above-mentioned embodiments are only illustrative to illustrate the effectiveness of the principles of the present invention, but not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.
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| CN201610127706.3ACN105679734B (en) | 2016-03-07 | 2016-03-07 | Integrated passive components pinboard and preparation method thereof |
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