技术领域technical field
本发明涉及一种半导体器件制造方法，具体地，涉及一种FinFET制造方法。The present invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a FinFET.
技术背景technical background
随着半导体器件的尺寸按比例缩小，出现了阈值电压随沟道长度减小而下降的问题，也即，在半导体器件中产生了短沟道效应。为了应对来自半导体涉及和制造方面的挑战，导致了鳍片场效应晶体管，即FinFET的发展。As the size of the semiconductor device is scaled down, there arises a problem that the threshold voltage decreases with the decrease of the channel length, that is, a short channel effect is generated in the semiconductor device. To meet the challenges from semiconductor design and manufacturing, led to the development of Fin Field Effect Transistor, or FinFET.
沟道穿通效应(Channelpunch-througheffect)是场效应晶体管的源结与漏结的耗尽区相连通的一种现象。当沟道穿通，就使源/漏间的势垒显著降低，则从源往沟道即注入大量载流子，并漂移通过源-漏间的空间电荷区、形成一股很大的电流；此电流的大小将受到空间电荷的限制，是所谓空间电荷限制电流。这种空间电荷限制电流是与栅压控制的沟道电流相并联的，因此沟道穿通将使得通过器件的总电流大大增加；并且在沟道穿通情况下,即使栅电压低于阈值电压，源-漏间也会有电流通过。这种效应是在小尺寸场效应晶体管中有可能发生的一种效应，且随着沟道宽度的进一步减小，其对器件特性的影响也越来越显著。Channel punch-through effect (Channelpunch-througheffect) is a phenomenon that the source junction and the depletion region of the drain junction of the field effect transistor are connected. When the channel is penetrated, the potential barrier between the source and the drain is significantly reduced, and a large number of carriers are injected from the source to the channel, and drift through the space charge region between the source and the drain to form a large current; The size of this current will be limited by the space charge, which is the so-called space charge limited current. This space charge limited current is in parallel with the channel current controlled by the gate voltage, so the channel penetration will greatly increase the total current through the device; and in the case of channel penetration, even if the gate voltage is lower than the threshold voltage, the source - There will also be current passing through the drain. This effect is an effect that may occur in small-scale field effect transistors, and its influence on device characteristics becomes more and more significant as the channel width is further reduced.
在FinFET中，通常采用对沟道下方的鳍片部分进行重掺杂来抑制沟道穿通效应。目前通用的掺杂方法是离子注入形成所需重掺杂区，然而，离子注入的深度难以精确控制，同时会对沟道表面造成损伤，为了消除损伤，通常会在沟道表面形成一层薄氧化层，增加了工艺复杂度。同时，杂质的分布难以控制，很难准确的在沟道底部形成超陡倒阱，而是会在沟道中引入杂质和缺陷，影响器件的亚阈值特性。因此，亟需对现有工艺进行改进，解决这一问题。In FinFETs, heavy doping of the portion of the fin below the channel is often used to suppress the channel punch-through effect. The current general doping method is ion implantation to form the required heavily doped region. However, the depth of ion implantation is difficult to control precisely, and at the same time it will cause damage to the channel surface. In order to eliminate the damage, a thin layer is usually formed on the channel surface. The oxide layer increases the process complexity. At the same time, the distribution of impurities is difficult to control, and it is difficult to accurately form an ultra-steep inverted well at the bottom of the channel. Instead, impurities and defects will be introduced into the channel, affecting the subthreshold characteristics of the device. Therefore, it is urgent to improve the existing technology to solve this problem.
发明内容Contents of the invention
本发明旨在提供一种FinFET器件及其制造方法，抑制穿通电流，同时不影响器件的其他参数。The present invention aims to provide a FinFET device and a manufacturing method thereof, which can suppress punch-through current without affecting other parameters of the device.
为解决该技术问题，本发明提供了一种FinFET器件制造方法，该方法包括：In order to solve this technical problem, the present invention provides a method for manufacturing a FinFET device, the method comprising:
a.提供衬底,其上具有鳍片；a. providing a substrate having fins thereon;
b.在所述鳍片两侧的衬底上形成第一浅沟槽隔离；b. forming a first shallow trench isolation on the substrate on both sides of the fin;
c.形成栅极结构覆盖所述鳍片的中部；c. forming a gate structure to cover the middle of the fin;
d.在所述栅极结构两侧的第一浅沟槽隔离上方形成第二浅沟槽隔离；d. forming a second shallow trench isolation above the first shallow trench isolation on both sides of the gate structure;
e.在所述鳍片两端分别形成源区、漏区。e. Forming a source region and a drain region at both ends of the fin respectively.
其中，在步骤c之前，还包括步骤f：在与第一浅沟槽隔离相邻的鳍片中形成穿通阻挡层；形成所述穿通阻挡层的方法为侧向散射。Wherein, before step c, further includes step f: forming a punch-through barrier layer in the fin adjacent to the first shallow trench isolation; the method of forming the punch-through barrier layer is side scattering.
其中，所述第一浅沟槽隔离的厚度大于等于40nm。Wherein, the thickness of the first shallow trench isolation is greater than or equal to 40 nm.
其中，所述第二浅沟槽隔离的厚度为10～40nm。Wherein, the thickness of the second shallow trench isolation is 10-40 nm.
其中，所述鳍片被栅极结构覆盖的区域形成器件的沟道区。Wherein, the region of the fin covered by the gate structure forms a channel region of the device.
其中，在步骤c中，所述栅极结构可以为伪栅叠层。Wherein, in step c, the gate structure may be a dummy gate stack.
相应的，本发明还提供了一种FinFET器件，包括：Correspondingly, the present invention also provides a FinFET device, including:
衬底；Substrate;
鳍片，位于所述衬底上方；a fin located above the substrate;
第一浅沟槽隔离，位于所述鳍片两侧的衬底上；The first shallow trench isolation is located on the substrate on both sides of the fin;
栅极结构，位于所述第一浅沟槽隔离上方，包裹所述鳍片；a gate structure, located above the first shallow trench isolation, wrapping the fin;
第二浅沟槽隔离，位于所述栅极叠层两侧的第一浅沟槽隔离上方；a second shallow trench isolation located above the first shallow trench isolation on both sides of the gate stack;
源区、漏区，分别位于栅极叠层两侧的鳍片两端。The source region and the drain region are respectively located at the two ends of the fins on both sides of the gate stack.
其中，所述第一浅沟槽隔离的厚度大于等于40nm。Wherein, the thickness of the first shallow trench isolation is greater than or equal to 40 nm.
其中，所述第二浅沟槽隔离的厚度为10～40nm。Wherein, the thickness of the second shallow trench isolation is 10-40 nm.
其中，所述鳍片被栅极结构覆盖的区域形成器件的沟道区。Wherein, the region of the fin covered by the gate structure forms a channel region of the device.
本发明提供的FinFET器件，通过在栅极两侧的浅沟槽隔离结构上方再形成一层浅沟槽隔离的方法，减小了源漏区的有效高度，使得源漏诸如完成之后，形成的源漏PN结结深减小，PTSL发生的位置处于栅控之下，能够很有效的抑制器件的穿通电流。与现有技术相比，本发明不需要进行离子注入就可以很好的抑制PTSL，器件性能优越，且不增加工艺复杂度。In the FinFET device provided by the present invention, by forming a layer of shallow trench isolation above the shallow trench isolation structure on both sides of the gate, the effective height of the source and drain regions is reduced, so that after the source and drain are completed, the formed The depth of the source-drain PN junction is reduced, and the position where PTSL occurs is under gate control, which can effectively suppress the punch-through current of the device. Compared with the prior art, the invention can well suppress PTSL without ion implantation, has superior device performance, and does not increase process complexity.
附图说明Description of drawings
图1和图8示意性地示出形成根据本发明的制造半导体鳍片的方法各阶段半导体结构的三维等角图。1 and 8 schematically show three-dimensional isometric views of various stages of forming a semiconductor structure in a method for manufacturing a semiconductor fin according to the present invention.
图2、图3、图4、图5、图6和图7示意性地示出形成根据本发明的制造半导体鳍片的方法各阶段半导体结构的剖面图。Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 and Fig. 7 schematically show cross-sectional views of various stages of forming the semiconductor structure of the method for manufacturing semiconductor fins according to the present invention.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.
本发明提供了一种FinFET器件，包括：衬底100；鳍片200，位于所述衬底100上方；第一浅沟槽隔离300，位于所述鳍片200两侧的衬底100上；栅极结构400，位于所述第一浅沟槽隔离300上方，包裹所述鳍片200；第二浅沟槽隔离310，位于所述栅极叠层400两侧的第一浅沟槽隔离300上方；源区、漏区，分别位于栅极叠层400两侧的鳍片200两端。The present invention provides a FinFET device, comprising: a substrate 100; a fin 200 located above the substrate 100; a first shallow trench isolation 300 located on the substrate 100 on both sides of the fin 200; a gate pole structure 400, located above the first shallow trench isolation 300, wrapping the fin 200; second shallow trench isolation 310, located above the first shallow trench isolation 300 on both sides of the gate stack 400 The source region and the drain region are respectively located at both ends of the fin 200 on both sides of the gate stack 400 .
其中，所述第一浅沟槽隔离300的厚度大于等于40nm；所述第二浅沟槽隔离310的厚度为10～40nm；所述鳍片200被栅极结构400覆盖的区域为器件的沟道区。Wherein, the thickness of the first shallow trench isolation 300 is greater than or equal to 40 nm; the thickness of the second shallow trench isolation 310 is 10-40 nm; the area of the fin 200 covered by the gate structure 400 is the trench of the device. road area.
沟道穿通电流是由于场效应晶体管的源结与漏结的耗尽区相连通而产生的，究其源头，是由于沟道下方的区域栅控能力很弱，无法对该区域的载流子产生有效控制，形成较大的漏电流。因此，本发明从这一点出发，通过在栅极两侧的浅沟槽隔离结构上方再形成一层浅沟槽隔离的方法，减小了源漏区的有效高度，使得源漏诸如完成之后，形成的源漏PN结结深减小，PTSL发生的位置处于栅控之下，能够很有效的抑制器件的穿通电流。与现有技术相比，本发明不需要进行离子注入就可以很好的抑制PTSL，器件性能优越，且不增加工艺复杂度。The channel penetration current is generated due to the connection between the source junction and the depletion region of the drain junction of the field effect transistor. The source is that the gate control ability of the area under the channel is very weak, and the carrier in the area cannot be controlled. Produce effective control and form a larger leakage current. Therefore, starting from this point, the present invention reduces the effective height of the source and drain regions by forming a layer of shallow trench isolation above the shallow trench isolation structures on both sides of the gate, so that after the source and drain are completed, The depth of the formed source-drain PN junction is reduced, and the position where PTSL occurs is under gate control, which can effectively suppress the punch-through current of the device. Compared with the prior art, the invention can well suppress PTSL without ion implantation, has superior device performance, and does not increase process complexity.
相应的，本发明还提供了一种FinFET制造方法，该方法包括以下步骤：Correspondingly, the present invention also provides a FinFET manufacturing method, the method comprising the following steps:
a.提供衬底100和鳍片200；a. providing a substrate 100 and a fin 200;
b.在所述鳍片200两侧的衬底100上形成第一浅沟槽隔离300；b. forming a first shallow trench isolation 300 on the substrate 100 on both sides of the fin 200;
c.形成栅极结构400覆盖所述鳍片200的中部；c. forming a gate structure 400 to cover the middle of the fin 200;
d.在所述栅极结构400两侧的第一浅沟槽隔离300上方形成第二浅沟槽隔离310；d. forming a second shallow trench isolation 310 above the first shallow trench isolation 300 on both sides of the gate structure 400;
e.在所述鳍片200两端的部分分别形成源区、漏区。e. A source region and a drain region are respectively formed at two ends of the fin 200 .
其中，在步骤c之前，还包括步骤f：在与第一浅沟槽隔离300相邻的鳍片200中形成穿通阻挡层220；形成所述穿通阻挡层的方法为侧向散射。Wherein, before step c, further includes step f: forming a penetration barrier layer 220 in the fin 200 adjacent to the first shallow trench isolation 300; the method of forming the penetration barrier layer is side scattering.
其中，所述第一浅沟槽隔离300的厚度大于等于40nm。Wherein, the thickness of the first shallow trench isolation 300 is greater than or equal to 40 nm.
其中，所述第二浅沟槽隔离310的厚度为10～40nm。Wherein, the thickness of the second shallow trench isolation 310 is 10-40 nm.
其中，所述鳍片200被栅极结构400覆盖的区域为器件的沟道区。Wherein, the region of the fin 200 covered by the gate structure 400 is the channel region of the device.
其中，在步骤c中，所述栅极结构400可以为伪栅叠层；所述伪栅叠层在层间介质层形成之后用栅极结构替换。Wherein, in step c, the gate structure 400 may be a dummy gate stack; the dummy gate stack is replaced with a gate structure after the interlayer dielectric layer is formed.
以下将参照附图更详细地描述本实发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various figures, identical elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale.
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“直接在……上面”或“在……上面并与之邻接”的表述方式。If it is to describe the situation directly on another layer or another area, the expression "directly on" or "on and adjacent to" will be used herein.
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。例如，衬底和鳍片的半导体材料可以选自IV族半导体，如Si或Ge，或III-V族半导体，如GaAs、InP、GaN、SiC，或上述半导体材料的叠层。In the following, many specific details of the present invention are described, such as device structures, materials, dimensions, processing techniques and techniques, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. For example, the semiconductor materials of the substrate and the fins can be selected from group IV semiconductors, such as Si or Ge, or group III-V semiconductors, such as GaAs, InP, GaN, SiC, or stacks of the above semiconductor materials.
参见图1，使出了本发明中的第一衬底100。所述第一衬底材料为半导体材料，可以是硅，锗，砷化镓等，优选的，在本实施例中，所用衬底为硅衬底。Referring to FIG. 1 , a first substrate 100 in the present invention is shown. The first substrate material is a semiconductor material, such as silicon, germanium, gallium arsenide, etc. Preferably, in this embodiment, the substrate used is a silicon substrate.
接下来，经过投影，曝光，显影，刻蚀等常规工艺对所述衬底进行刻蚀，形成鳍片200，所述刻蚀方法可以是干法刻蚀或干法/湿法刻蚀。如图2所示，在鳍片(200)刻蚀完成之后，作为硬掩膜的掩膜板(210)暂不去除，便于在后续工艺中可重复使用。Next, the substrate is etched through conventional processes such as projection, exposure, development, and etching to form the fins 200. The etching method may be dry etching or dry/wet etching. As shown in FIG. 2, after the etching of the fins (200) is completed, the mask plate (210) as a hard mask is not removed temporarily, so that it can be reused in subsequent processes.
接下来，对所述半导体结构进行浅沟槽隔离，以形成第一浅沟槽隔离结构300，如图3所示。优选地，首先在半导体鳍片200上成氮化硅和缓冲二氧化硅图形，作为沟槽腐蚀的掩膜。接下来在衬底上腐蚀出具有一定深度和侧墙角度的沟槽。然后生长一薄层二氧化硅，以圆滑沟槽的顶角和去掉刻蚀过程中在硅表面引入的损伤。氧化之后进行沟槽填充，填充介质可以是二氧化硅。接下来使用CMP工艺对半导体衬底表面进行平坦化，氮化硅作为CMP的阻挡层。之后，以氮化硅为掩膜，对半导体结构表面进行刻蚀，为了避免后续工艺中扩散时在鳍片200中引入纵向扩散，所述刻蚀深度大于实际所需鳍片高度，可以为20～60nm。刻蚀完成之后，形成第一浅沟槽隔离结构300，其顶部距离鳍片200顶部20～60nm。最后使用热的磷酸取出暴露出的氮化硅，暴露出鳍片200。Next, shallow trench isolation is performed on the semiconductor structure to form a first shallow trench isolation structure 300 , as shown in FIG. 3 . Preferably, silicon nitride and buffer silicon dioxide are first patterned on the semiconductor fin 200 as a mask for trench etching. Next, trenches with a certain depth and sidewall angles are etched on the substrate. A thin layer of silicon dioxide is then grown to round the top corners of the trenches and remove damage introduced to the silicon surface during the etch process. Oxidation is followed by trench filling, and the filling medium may be silicon dioxide. Next, a CMP process is used to planarize the surface of the semiconductor substrate, and silicon nitride is used as a CMP barrier layer. Afterwards, using silicon nitride as a mask, the surface of the semiconductor structure is etched. In order to avoid introducing vertical diffusion into the fin 200 during diffusion in the subsequent process, the etching depth is greater than the actual required fin height, which can be 20 ~60nm. After the etching is completed, the first shallow trench isolation structure 300 is formed, the top of which is 20-60 nm away from the top of the fin 200 . Finally, the exposed silicon nitride is removed using hot phosphoric acid, exposing the fins 200 .
可选的，如图4所示，在所述第一浅沟槽隔离结构300中进行离子注入，采用侧向散射的方法，在鳍片200与第一浅沟槽隔离结构300相邻的区域的上半部分形成穿通阻挡层220。与离子注入相册穿通阻挡层相比，侧向散射形成穿通阻挡层避免在沟道中引入缺陷和损伤，性能较。完成散射之后的器件结构如图5所示。Optionally, as shown in FIG. 4 , ion implantation is performed in the first shallow trench isolation structure 300 , using the method of side scattering, in the region adjacent to the fin 200 and the first shallow trench isolation structure 300 Form the punch-through barrier layer 220 in the upper half. Compared with ion implantation through the barrier layer, the formation of the side scattering through the barrier layer avoids the introduction of defects and damage in the channel, and the performance is better. The device structure after scattering is shown in Figure 5.
接下来，在沟道上方形成栅极结构400，栅极结构400包括栅介质层、功函数调节层和栅极金属层，如图7所示。具体的，所述栅介质层可以是热氧化层，包括氧化硅、氮氧化硅；也可为高K介质，例如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅介质层的厚度可以为1nm-10nm，例如3nm、5nm或8nm。所述功函数调节层可以采用TiN、TaN等材料制成，其厚度范围为3nm～15nm。所述栅极金属层可以为一层或者多层结构。其材料可以为TaN、TaC、TiN、TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合。其厚度范围例如可以为10nm-40nm，如20nm或30nm。伪栅叠层，并形成源漏区。所述伪栅叠层可以是单层的，也可以是多层的。伪栅叠层可以包括聚合物材料、非晶硅、多晶硅或TiN，厚度可以为10-100nm。可以采用热氧化、化学气相沉积(CVD)、原子层沉积(ALD)等工艺来形成伪栅叠层。所述源漏区形成方法可以是离子注入然后退火激活离子、原位掺杂外延和/或二者的组合。Next, a gate structure 400 is formed above the channel, and the gate structure 400 includes a gate dielectric layer, a work function adjustment layer and a gate metal layer, as shown in FIG. 7 . Specifically, the gate dielectric layer can be a thermal oxide layer, including silicon oxide and silicon oxynitride; it can also be a high-K dielectric, such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al2 O3 , La2 O3 , ZrO2 , LaAlO or a combination thereof, the thickness of the gate dielectric layer may be 1nm-10nm, such as 3nm, 5nm or 8nm. The work function adjustment layer can be made of TiN, TaN and other materials, and its thickness ranges from 3nm to 15nm. The gate metal layer may be a one-layer or multi-layer structure. The material thereof may be one of TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN,RuTax ,NiTax or a combination thereof. Its thickness range may be, for example, 10nm-40nm, such as 20nm or 30nm. Dummy gate stacks and form source and drain regions. The dummy gate stack can be single-layer or multi-layer. The dummy gate stack may include polymer material, amorphous silicon, polysilicon or TiN, and the thickness may be 10-100 nm. Processes such as thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD) can be used to form the dummy gate stack. The method for forming the source and drain regions may be ion implantation followed by annealing to activate ions, in-situ doping epitaxy, and/or a combination of both.
可选地，在栅极叠层的侧壁上形成侧墙，用于将栅极隔开。侧墙可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙可以具有多层结构。侧墙可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。Optionally, sidewalls are formed on the sidewalls of the gate stacks to separate the gates. The sidewalls may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials. The side walls can have a multi-layer structure. The sidewall can be formed by deposition and etching process, and its thickness range can be 10nm-100nm, such as 30nm, 50nm or 80nm.
在所述栅极叠层400两侧的第一浅沟槽隔离300上方形成第二浅沟槽隔离310，如图7所示。所述第二浅沟槽隔离310的作用在于减小了源漏区的有效高度，使得源漏诸如完成之后，形成的源漏PN结结深减小，PTSL发生的位置处于栅控之下，能够很有效的抑制器件的穿通电流。根据器件结构，其厚度为10～40nm。具体的形成方法与形成第一浅沟槽隔离300类似，在此不再赘述。A second shallow trench isolation 310 is formed above the first shallow trench isolation 300 on both sides of the gate stack 400 , as shown in FIG. 7 . The function of the second shallow trench isolation 310 is to reduce the effective height of the source-drain region, so that after the source-drain is completed, the depth of the formed source-drain PN junction is reduced, and the position where PTSL occurs is under gate control. It can effectively suppress the punch-through current of the device. Depending on the device structure, its thickness is 10 to 40 nm. The specific formation method is similar to the formation of the first shallow trench isolation 300 , and will not be repeated here.
接下来，在栅极叠层400两侧的鳍片上形成源漏区。具体的，通过倾斜的离子注入的方法，在鳍片200两端形成所需杂质分布，由于STI被垫高，杂质注入深度相应的减小，源漏结深变浅，使穿通区域位于栅控之下，能够有效地抑制穿通电流。Next, source and drain regions are formed on the fins on both sides of the gate stack 400 . Specifically, the desired impurity distribution is formed at both ends of the fin 200 by means of inclined ion implantation. Since the STI is raised, the depth of impurity implantation is correspondingly reduced, and the depth of the source-drain junction becomes shallower, so that the through region is located at the gate control region. Below, the punch-through current can be effectively suppressed.
接下来，淀积层间介质层500，并并行平坦化，露出伪栅叠层。具体的，层间介质层500可以通过CVD、高密度等离子体CVD、旋涂或其他合适的方法形成。层间介质层500的材料可以采用包括SiO2、碳掺杂SiO2、BPSG、PSG、UGS、氮氧化硅、低k材料或其组合。层间介质层500的厚度范围可以是40nm-150nm，如80nm、100nm或120nm。接下来，执行平坦化处理，使伪栅叠层暴露出来，并与层间介质层500齐平(本发明中的术语“齐平”指的是两者之间的高度差在工艺误差允许的范围内)。Next, an interlayer dielectric layer 500 is deposited and planarized in parallel to expose the dummy gate stack. Specifically, the interlayer dielectric layer 500 can be formed by CVD, high density plasma CVD, spin coating or other suitable methods. The material of the interlayer dielectric layer 500 may include SiO2 , carbon-doped SiO 2 , BPSG, PSG, UGS, silicon oxynitride, low-k materials or combinations thereof. The thickness range of the interlayer dielectric layer 500 may be 40nm-150nm, such as 80nm, 100nm or 120nm. Next, a planarization process is performed to expose the dummy gate stack and be flush with the interlayer dielectric layer 500 (the term "flush" in the present invention refers to that the height difference between the two is within the allowable process error within the range).
本实施例中所采用的是先栅工艺，然而本领域中的技术人员能很清楚的理解，本发明中形成穿通阻挡层的方法同样可以用于先栅工艺，具体过程在此不再赘述。The gate-first process is adopted in this embodiment, but those skilled in the art can clearly understand that the method for forming the punch-through barrier layer in the present invention can also be used in the gate-first process, and the specific process will not be repeated here.
本发明提供的FinFET器件，通过在栅极两侧的浅沟槽隔离结构上方再形成一层浅沟槽隔离的方法，减小了源漏区的有效高度，使得源漏诸如完成之后，形成的源漏PN结结深减小，PTSL发生的位置处于栅控之下，能够很有效的抑制器件的穿通电流。与现有技术相比，本发明不需要进行离子注入就可以很好的抑制PTSL，器件性能优越，且不增加工艺复杂度。In the FinFET device provided by the present invention, by forming a layer of shallow trench isolation above the shallow trench isolation structure on both sides of the gate, the effective height of the source and drain regions is reduced, so that after the source and drain are completed, the formed The depth of the source-drain PN junction is reduced, and the position where PTSL occurs is under gate control, which can effectively suppress the punch-through current of the device. Compared with the prior art, the invention can well suppress PTSL without ion implantation, has superior device performance, and does not increase process complexity.
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。In addition, the scope of application of the present invention is not limited to the process, mechanism, manufacture, material composition, means, method and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, they are implemented in accordance with the present invention Corresponding embodiments described which function substantially the same or achieve substantially the same results may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacture, material compositions, means, methods or steps within their protection scope.
| Application Number | Priority Date | Filing Date | Title |
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| CN201410612511.9ACN105632929A (en) | 2014-11-04 | 2014-11-04 | FinFET device and manufacturing method thereof |
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| CN113140459A (en)* | 2020-01-19 | 2021-07-20 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
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| US20050093082A1 (en)* | 2003-10-31 | 2005-05-05 | Yong-Hoon Son | Fin field effect transistors having capping insulation layers and methods for forming the same |
| US20060244051A1 (en)* | 2005-04-27 | 2006-11-02 | Kabushiki Kaisha Toshiba | Semiconductor manufacturing method and semiconductor device |
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| CN104576383A (en)* | 2013-10-14 | 2015-04-29 | 中国科学院微电子研究所 | FinFET structure and manufacturing method thereof |
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| US20050093082A1 (en)* | 2003-10-31 | 2005-05-05 | Yong-Hoon Son | Fin field effect transistors having capping insulation layers and methods for forming the same |
| US20060244051A1 (en)* | 2005-04-27 | 2006-11-02 | Kabushiki Kaisha Toshiba | Semiconductor manufacturing method and semiconductor device |
| CN102683192A (en)* | 2011-02-22 | 2012-09-19 | 格罗方德半导体公司 | Fin-transistor formed on a patterned sti region by late fin etch |
| CN104576383A (en)* | 2013-10-14 | 2015-04-29 | 中国科学院微电子研究所 | FinFET structure and manufacturing method thereof |
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| CN113140459A (en)* | 2020-01-19 | 2021-07-20 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
| CN113140459B (en)* | 2020-01-19 | 2022-09-20 | 中芯国际集成电路制造（天津）有限公司 | Method of forming a semiconductor device |
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