技术领域technical field
本申请涉及显示器件技术领域，具体涉及一种显示装置及其像素电路和驱动方法。The present application relates to the technical field of display devices, in particular to a display device, a pixel circuit and a driving method thereof.
背景技术Background technique
有机发光二极管(Organic Light-Emitting Diode，OLED)显示因具有高亮度、高发光效率、宽视角和低功耗等优点，近年来被人们广泛研究，并被迅速应用到新一代的显示当中。OLED显示的驱动方式可以分为无源矩阵驱动(Passive Matrix OLED，PMOLED)和有源矩阵驱动(Active Matrix OLED，AMOLED)两种。研究表明，无源矩阵驱动虽然成本低廉，但是存在交叉串扰现象，不能实现高分辨率的显示，且无源矩阵驱动电流大，降低了OLED的使用寿命。相比之下，有源矩阵驱动方式在每个像素上设置数目不同的晶体管作为电流源，避免了交叉串扰，所需的驱动电流较小，功耗较低，使OLED的寿命增加，可以实现高分辨的显示，同时，有源矩阵驱动更容易满足大面积和高灰度级显示的需要。Due to the advantages of high brightness, high luminous efficiency, wide viewing angle and low power consumption, Organic Light-Emitting Diode (OLED) display has been extensively studied in recent years and has been rapidly applied to a new generation of displays. OLED display driving methods can be divided into passive matrix driving (Passive Matrix OLED, PMOLED) and active matrix driving (Active Matrix OLED, AMOLED). Research shows that although the cost of passive matrix driving is low, there is crosstalk phenomenon, which cannot realize high-resolution display, and the passive matrix driving current is large, which reduces the service life of OLED. In contrast, the active matrix driving method sets a different number of transistors on each pixel as a current source, which avoids crosstalk, requires less driving current, and lower power consumption, which increases the life of the OLED and can achieve High-resolution display, at the same time, the active matrix drive is easier to meet the needs of large-area and high-gray-level display.
传统AMOLED的像素电路是简单的两薄膜场效应晶体管(Thin Film Transistor，TFT)结构，这种电路虽然结构简单，但是不能补偿驱动晶体管T1和OLED阈值电压漂移，或因TFT器件采用多晶材料制成而导致面板各处TFT器件的阈值电压不均匀性，也不能补偿驱动管T1的迁移率变化。当驱动晶体管T1阈值电压和迁移率发生漂移或在面板上各处的值不一致时，驱动电流IDS(T1的漏极-源极间电流)出现改变，并且面板上不同的像素因偏置电压的不同而使OLED阈值电压发生不同程度的漂移，从而造成面板显示的不均匀性。The pixel circuit of a traditional AMOLED is a simple two thin film field effect transistor (Thin Film Transistor, TFT) structure. Although this circuit has a simple structure, it cannot compensate the drift of the driving transistor T1 and the threshold voltage of OLED, or because the TFT device is made of polycrystalline material. As a result, the threshold voltage of the TFT devices on the panel is not uniform, and the mobility change of the driving tube T1 cannot be compensated. When the threshold voltage and mobility of the driving transistor T1 drift or the values are inconsistent everywhere on the panel, the driving current IDS (the current between the drain and the source of T1) changes, and different pixels on the panel are affected by the bias voltage. The threshold voltage of the OLED will drift to different degrees due to the difference, thus causing the non-uniformity of the panel display.
发明内容Contents of the invention
本申请提供一种像素电路和驱动方法及其显示装置，以补偿驱动晶体管和发光器件的阈值电压的不均匀或者阈值电压漂移，并且改善驱动晶体管的阈值电压不均匀。The present application provides a pixel circuit, a driving method and a display device thereof, so as to compensate the non-uniformity or threshold voltage drift of the threshold voltage of the driving transistor and the light-emitting device, and improve the non-uniform threshold voltage of the driving transistor.
根据第一方面，本申请一种实施例中提供一种像素电路，包括：驱动晶体管、发光元件、驱动控制晶体管、数据写入晶体管和存储电容，其中，所述驱动晶体管连接所述发光元件，用于驱动所述发光元件发光；所述数据写入晶体管分别连接数据信号线、信号扫描线、所述驱动控制晶体管和所述存储电容，用于在所述扫描信号线的扫描信号为有效时，响应所述数据信号线的数据信号以提供所述数据信号的电压；所述驱动控制晶体管分别连接发光控制信号线、所述驱动晶体管和所述数据写入晶体管，用于在响应所述发光控制信号，完成阈值和迁移率的补偿，以及将所述数据写入晶体管提供的所述数据信号的电压写入所述驱动晶体管；所述存储电容还连接所述发光元件，用于为所述驱动控制晶体管进行阈值补偿时提供所述驱动晶体管的阈值电压。According to the first aspect, an embodiment of the present application provides a pixel circuit, including: a driving transistor, a light emitting element, a driving control transistor, a data writing transistor, and a storage capacitor, wherein the driving transistor is connected to the light emitting element, It is used to drive the light-emitting element to emit light; the data writing transistor is respectively connected to the data signal line, the signal scanning line, the driving control transistor and the storage capacitor, and is used for when the scanning signal of the scanning signal line is valid , to provide the voltage of the data signal in response to the data signal of the data signal line; control signal to complete threshold value and mobility compensation, and write the voltage of the data signal provided by the data write transistor into the drive transistor; the storage capacitor is also connected to the light emitting element for the The threshold voltage of the driving transistor is provided when the driving control transistor performs threshold compensation.
根据第二方面，本申请一种实施例中提供一种像素电路驱动方法，应用于如上所述的像素电路，像素电路的每一驱动周期包括初始化阶段、阈值补偿阶段、数据写入阶段、迁移率补偿阶段和发光阶段，驱动方法包括：在所述初始化阶段，使所述驱动控制晶体管导通，初始化所述存储电容和所述发光元件的连接所述驱动晶体管的一端的电压；在所述阈值补偿阶段，所述驱动控制晶体管保持导通，以便为所述驱动晶体管提供参考电压，对所述驱动晶体管充电直至所述驱动晶体管关断，提取所述驱动晶体管的阈值电压并存储于所述存储电容；在所述数据写入阶段，使所述驱动控制晶体管关断，使所述数据写入晶体管导通，使得所述发光元件的连接所述驱动晶体管的一端的电压被刷新，所述存储电容存储所述数据写入晶体管输出的电压和所述发光元件的连接所述驱动晶体管的一端的电压之间的电压差；在所述迁移率补偿阶段，所述数据写入晶体管保持导通，使所述驱动控制晶体管导通，所述驱动晶体管导通，所述发光元件的连接所述驱动晶体管的一端的电压经所述驱动晶体管抬升，使得所述存储电容的两端形成发光过程的基准电压；在所述发光阶段，使所述数据写入晶体管关断，所述驱动控制晶体管保持导通，所述驱动晶体管根据所述存储电容两端的电压差产生所需要的发光电流，并驱动所述发光元件发光According to the second aspect, an embodiment of the present application provides a pixel circuit driving method, which is applied to the above-mentioned pixel circuit, and each driving cycle of the pixel circuit includes an initialization phase, a threshold compensation phase, a data writing phase, a transition In the rate compensation stage and the light emitting stage, the driving method includes: in the initialization stage, turning on the driving control transistor, and initializing the storage capacitor and the voltage at one end of the light emitting element connected to the driving transistor; In the threshold compensation phase, the driving control transistor is kept on to provide a reference voltage for the driving transistor, the driving transistor is charged until the driving transistor is turned off, and the threshold voltage of the driving transistor is extracted and stored in the storage capacitor; in the data writing phase, the drive control transistor is turned off, the data write transistor is turned on, so that the voltage at one end of the light-emitting element connected to the drive transistor is refreshed, and the The storage capacitor stores the voltage difference between the voltage output by the data writing transistor and the voltage at one end of the light-emitting element connected to the driving transistor; during the mobility compensation phase, the data writing transistor remains turned on , the drive control transistor is turned on, the drive transistor is turned on, and the voltage at one end of the light-emitting element connected to the drive transistor is raised through the drive transistor, so that the two ends of the storage capacitor form a light-emitting process. Reference voltage; in the light-emitting phase, the data write transistor is turned off, the drive control transistor is kept on, and the drive transistor generates the required light-emitting current according to the voltage difference between the two ends of the storage capacitor, and drives The light emitting element emits light
根据第三方面，本申请一种实施例中提供一种显示装置，包括：像素电路矩阵，所述像素电路矩阵包括排列成N行M列矩阵的如上所述的像素电路，N和M为正整数；栅极驱动电路，用于产生扫描信号，并通过沿第一方向形成的各行扫描信号线向所述像素电路提供所需的控制信号；数据驱动电路，用于产生代表灰度信息的数据信号，并通过沿第二方向形成的各数据信号线向所述像素电路提供数据信号；控制器，用于分别向所述栅极驱动电路和所述数据驱动电路提供控制时序。According to a third aspect, an embodiment of the present application provides a display device, including: a pixel circuit matrix, the pixel circuit matrix includes the above-mentioned pixel circuits arranged in a matrix of N rows and M columns, and N and M are positive Integer; gate drive circuit, used to generate scan signals, and provide required control signals to the pixel circuits through each row of scan signal lines formed along the first direction; data drive circuit, used to generate data representing grayscale information signal, and provide data signals to the pixel circuit through the data signal lines formed along the second direction; the controller is used to provide control timing to the gate drive circuit and the data drive circuit respectively.
本申请实施例通过驱动晶体管、驱动控制晶体管、数据写入晶体管和存储电容的相互配合，完成阈值和迁移率的补偿，然后将数据信号写入驱动晶体管，通过驱动晶体管驱动发光元件发光，从而解决显示面板各处驱动晶体管阈值电压不同而导致的显示不均匀问题，可以补偿驱动管迁移率变化造成的显示均匀度降低问题，进一步提高了显示的均匀度。In this embodiment of the present application, the compensation of the threshold value and the mobility is completed through the mutual cooperation of the driving transistor, the driving control transistor, the data writing transistor and the storage capacitor, and then the data signal is written into the driving transistor, and the light-emitting element is driven to emit light through the driving transistor, thereby solving the problem of The problem of display unevenness caused by different threshold voltages of the driving transistors in various parts of the display panel can compensate for the problem of reduced display uniformity caused by changes in the mobility of the driving transistors, thereby further improving the display uniformity.
附图说明Description of drawings
图1为本申请实施例一公开的一种像素电路结构图；FIG. 1 is a structural diagram of a pixel circuit disclosed in Embodiment 1 of the present application;
图2为图1所示像素电路的驱动时序图；FIG. 2 is a driving timing diagram of the pixel circuit shown in FIG. 1;
图3为本申请实施例二公开的一种像素电路结构图；FIG. 3 is a structural diagram of a pixel circuit disclosed in Embodiment 2 of the present application;
图4a为图3所示像素电路的一种驱动时序图；FIG. 4a is a driving timing diagram of the pixel circuit shown in FIG. 3;
图4b为图3所示像素电路的另一种驱动时序图；FIG. 4b is another driving timing diagram of the pixel circuit shown in FIG. 3;
图5为本申请实施例三公开的一种像素电路结构图；FIG. 5 is a structural diagram of a pixel circuit disclosed in Embodiment 3 of the present application;
图6为图5所示像素电路的驱动时序图；FIG. 6 is a driving timing diagram of the pixel circuit shown in FIG. 5;
图7a为本申请实施例四公开的一种像素电路结构图；FIG. 7a is a structural diagram of a pixel circuit disclosed in Embodiment 4 of the present application;
图7b为本申请实施例四公开的另一种像素电路结构图；Fig. 7b is another pixel circuit structure diagram disclosed in Embodiment 4 of the present application;
图7c为本申请实施例四公开的又一种像素电路结构图；FIG. 7c is another pixel circuit structure diagram disclosed in Embodiment 4 of the present application;
图8为图7a所示像素电路的驱动时序图；FIG. 8 is a driving timing diagram of the pixel circuit shown in FIG. 7a;
图9为本申请实施例五公开的一种像素电路结构图；FIG. 9 is a structural diagram of a pixel circuit disclosed in Embodiment 5 of the present application;
图10a为图9所示像素电路的一种驱动时序图；Fig. 10a is a driving timing diagram of the pixel circuit shown in Fig. 9;
图10b为图9所示像素电路的另一种驱动时序图；Fig. 10b is another driving timing diagram of the pixel circuit shown in Fig. 9;
图11为本申请实施例六公开的一种像素电路结构图；FIG. 11 is a structural diagram of a pixel circuit disclosed in Embodiment 6 of the present application;
图12为图11所示像素电路的驱动时序图；FIG. 12 is a driving timing diagram of the pixel circuit shown in FIG. 11;
图13为本申请实施例七公开的一种像素电路结构图；FIG. 13 is a structural diagram of a pixel circuit disclosed in Embodiment 7 of the present application;
图14为图12所示像素电路的驱动时序图；FIG. 14 is a driving timing diagram of the pixel circuit shown in FIG. 12;
图15为本申请一实施例公开的一种显示装置结构原理示意图。FIG. 15 is a schematic diagram of the structural principle of a display device disclosed in an embodiment of the present application.
具体实施方式Detailed ways
下面通过具体实施方式结合附图对本申请作进一步详细说明。其中相同的标号表示相同的元件。The present application will be described in further detail below through specific embodiments in conjunction with the accompanying drawings. Wherein the same reference numerals represent the same elements.
首先对一些术语进行说明。本申请各实施例中的晶体管可以是任何结构的晶体管，比如双极型晶体管(BJT)或者场效应晶体管(FET)。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极，在实际应用过程中，“发射极”和“集电极”可以依据信号流向而互换。当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极，在实际应用过程中，“源极”和“漏极”可以依据信号流向而互换。显示装置中的晶体管通常为薄膜晶体管(TFT)，是一种场效应晶体管。下面以TFT为例对本申请做详细的说明。First some terminology is explained. The transistors in various embodiments of the present application may be transistors of any structure, such as bipolar junction transistors (BJT) or field effect transistors (FET). When the transistor is a bipolar transistor, its control pole refers to the base of the bipolar transistor, the first pole can be the collector or emitter of the bipolar transistor, and the corresponding second pole can be the base of the bipolar transistor. Emitter or collector. In practical applications, "emitter" and "collector" can be interchanged according to the direction of signal flow. When the transistor is a field effect transistor, its control pole refers to the gate of the field effect transistor, the first pole can be the drain or source of the field effect transistor, and the corresponding second pole can be the source or drain of the field effect transistor In practical applications, "source" and "drain" can be interchanged according to the direction of signal flow. A transistor in a display device is usually a thin film transistor (TFT), which is a type of field effect transistor. Hereinafter, the present application will be described in detail by taking TFT as an example.
本申请一实施例中的发光元件为有机发光二极管(Organic Light-EmittingDiode，OLED)，但并不限于此，在其它实施例中，也可以是其它类型的发光元件。发光元件的一端(称为第一端)为阳极，相应地，另一端(称为第二端)为阴极。The light-emitting element in one embodiment of the present application is an organic light-emitting diode (Organic Light-Emitting Diode, OLED), but it is not limited thereto. In other embodiments, it can also be other types of light-emitting elements. One end (referred to as the first end) of the light-emitting element is an anode, and correspondingly, the other end (referred to as a second end) is a cathode.
第一电平端和第二电平端是为像素电路工作所提供的电源的两端。在一种实施例中，第一电平端可以为高电平端VDD，第二电平端为低电平端VSS或地线，在其它实施例中，也可以作适应性地置换。需要说明的是：对于像素电路而言，第一电平端(例如高电平端VDD)和第二电平端(例如低电平端VSS)并非本申请像素电路的一部分，为了使本领域技术人员更好地理解本申请的技术方案，而特别引入第一电平端和第二电平端予以描述。The first level end and the second level end are two ends of the power supply provided for the operation of the pixel circuit. In one embodiment, the first level terminal may be the high level terminal VDD , and the second level terminal may be the low level terminal VSS or the ground line, and in other embodiments, an adaptive replacement may also be made. It should be noted that: for the pixel circuit, the first level terminal (such as the high level terminal VDD ) and the second level terminal (such as the low level terminal VSS ) are not part of the pixel circuit of this application, in order to make those skilled in the art To better understand the technical solution of the present application, the first level terminal and the second level terminal are introduced in particular for description.
需要说明的是，为了描述方便，也为了使本领域技术人员更清楚地理解本申请的技术方案，本申请文件中引入第一节点A和第二节点B对电路结构相关部分进行标识，不能认定为电路中额外引入的端子。此外，为描述方便，高电平采用VH表征，低电平采用VL表征。It should be noted that, for the convenience of description and to enable those skilled in the art to understand the technical solution of the present application more clearly, the first node A and the second node B are introduced in this application document to identify the relevant parts of the circuit structure, and it cannot be determined that It is an additional terminal introduced in the circuit. In addition, for the convenience of description, the high level is represented by VH , and the low level is represented by VL.
本申请实施例中的晶体管是以N型TFT为例进行描述，应理解，根据本申请提供的思想也可以采用相应的基于P型或者N型和P型的像素电路。The transistor in the embodiment of the present application is described by taking an N-type TFT as an example. It should be understood that a corresponding P-type or N-type and P-type pixel circuit can also be used according to the ideas provided in the present application.
如图15所示，本申请一实施例提供了一种显示装置，其包括：显示面板100、栅极驱动电路200、数据驱动电路300和控制器400。As shown in FIG. 15 , an embodiment of the present application provides a display device, which includes: a display panel 100 , a gate driving circuit 200 , a data driving circuit 300 and a controller 400 .
显示面板100包括排列成n行m列矩阵的多个像素电路Pixel[1][1]、……、Pixel[n][m]，与每个像素电路相连的第一方向(例如横向)的多条扫描线Gate[1]、……、Gate[n]，以及与每个像素相连的第二方向(例如纵向)的多条数据线Data[1]、……、Data[m]。其中，n和m为大于0的整数；Pixel[n][m]表征第n行m列的像素电路，在该实施例中，像素电路采用本申请另一实施例提供的像素电路；Gate[n]表示第n行像素电路对应的扫描线，用于向相应行的像素电路提供扫描信号；Data[m]表示第m列像素电路对应的数据线，用于向相应列的像素电路提供数据电压。显示面板100可以是液晶显示面板、有机发光显示面板、电子纸显示面板等，而对应的显示装置可以是液晶显示器、有机发光显示器、电子纸显示器等。The display panel 100 includes a plurality of pixel circuits Pixel[1][1], ..., Pixel[n][m] arranged in a matrix of n rows and m columns, and the first direction (for example, horizontal direction) connected to each pixel circuit A plurality of scanning lines Gate[1], ..., Gate[n], and a plurality of data lines Data[1], ..., Data[m] connected to each pixel in a second direction (for example, vertical direction). Wherein, n and m are integers greater than 0; Pixel[n][m] represents the pixel circuit in the nth row and m column, and in this embodiment, the pixel circuit adopts the pixel circuit provided by another embodiment of the present application; Gate[ n] indicates the scanning line corresponding to the pixel circuit in the nth row, which is used to provide scanning signals to the pixel circuit in the corresponding row; Data[m] indicates the data line corresponding to the pixel circuit in the mth column, which is used to provide data to the pixel circuit in the corresponding column Voltage. The display panel 100 may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, etc., and a corresponding display device may be a liquid crystal display, an organic light emitting display, an electronic paper display, etc.
栅极驱动电路200用于产生扫描脉冲信号，并通过沿第一方向形成的各行扫描线Gate[1]、……、Gate[n]，向相应的像素电路提供所需的控制信号，以完成对像素矩阵的逐行扫描。The gate drive circuit 200 is used to generate scan pulse signals, and provide required control signals to corresponding pixel circuits through each row of scan lines Gate[1], ..., Gate[n] formed along the first direction, to complete Progressive scan of the pixel matrix.
数据驱动电路300的信号输出端耦合到显示面板100中与其对应的数据线Data[1]、……、Data[m]上，数据驱动电路300产生的数据电压信号VDATA通过数据线Data[1]……Data[m]传输到对应的像素单元内以实现图像灰度。The signal output end of the data drive circuit 300 is coupled to the corresponding data lines Data[1], ..., Data[m] in the display panel 100, and the data voltage signal VDATA generated by the data drive circuit 300 passes through the data line Data[1]. ]……Data[m] is transferred to the corresponding pixel unit to achieve image grayscale.
控制器400用于分别向栅极驱动电路200和数据驱动电路300提供控制时序，以控制整个显示装置动作的时序。图示中控制器400与栅极驱动电路200及数据驱动电路300分离，然而在其它实施例中，控制器400也可以分别集成到栅极驱动电路200和数据驱动电路300中。The controller 400 is used to provide control timing to the gate driving circuit 200 and the data driving circuit 300 respectively, so as to control the timing of the operation of the entire display device. In the figure, the controller 400 is separated from the gate driving circuit 200 and the data driving circuit 300 , however, in other embodiments, the controller 400 can also be integrated into the gate driving circuit 200 and the data driving circuit 300 respectively.
以下通过多个实施例详细描述本申请所涉及的像素电路。The pixel circuit involved in this application will be described in detail below through multiple embodiments.
实施例一：Embodiment one:
请参考图1，为本实施例公开的一种像素电路结构图，包括：串联在第一电平端VDD和第二电平端GND之间的驱动晶体管T1和发光元件OLED，以及驱动控制晶体管(为便于结合图示描述，也称其为第二晶体管)T2、数据写入晶体管(为便于结合图示描述，也称其为第三晶体管)T3和存储电容C1。Please refer to FIG. 1 , which is a structure diagram of a pixel circuit disclosed in this embodiment, including: a drive transistor T1 and a light emitting element OLED connected in series between the first level terminalVDD and the second level terminal GND, and a drive control transistor ( For the convenience of description in combination with the diagram, it is also referred to as the second transistor) T2, the data writing transistor (for the convenience of description in conjunction with the diagram, it is also referred to as the third transistor) T3 and the storage capacitor C1.
驱动晶体管T1的第一极耦合至第一电平端VDD，驱动晶体管T1的第二极耦合至发光元件OLED的第一端(本文将二者连接之处称为第二节点B)，发光元件OLED的第二端耦合至第二电平端GND。在一种实施例中，请参考图1，发光元件OLED的第一端为阳极，发光元件OLED的第二端为阴极。The first pole of the driving transistor T1 is coupled to the first level terminal VDD , the second pole of the driving transistor T1 is coupled to the first terminal of the light-emitting element OLED (the connection between the two is referred to as the second node B herein), and the light-emitting element The second terminal of the OLED is coupled to the second level terminal GND. In one embodiment, please refer to FIG. 1 , the first end of the light emitting element OLED is an anode, and the second end of the light emitting element OLED is a cathode.
驱动晶体管T1的控制极耦合至第二晶体管T2的第二电极，第二晶体管T2的第一电极耦合至第三晶体管T3的第二电极(本文将二者连接之处称为第一节点A)，第二晶体管T2的控制极耦合至发光控制信号线，用于响应发光控制信号VEM。The control electrode of the driving transistor T1 is coupled to the second electrode of the second transistor T2, and the first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3 (herein, the connection between the two is referred to as the first node A) , the control electrode of the second transistor T2 is coupled to the light emission control signal line for responding to the light emission control signal VEM .
第三晶体管T3的第一电极耦合至数据信号线，第三晶体管T3的第二电极耦合至第二晶体管T2的第一电极，第三晶体管T3的控制极耦合至扫描信号线，用于响应扫描信号VSCAN。在具体实施例中，数据信号线用于提供数据信号VDATA和参考电压VREF，在其它实施例中，数据信号线还可以用于提供初始化电压。The first electrode of the third transistor T3 is coupled to the data signal line, the second electrode of the third transistor T3 is coupled to the first electrode of the second transistor T2, and the control electrode of the third transistor T3 is coupled to the scanning signal line for responding to scanning Signal VSCAN . In a specific embodiment, the data signal line is used to provide the data signal VDATA and the reference voltage VREF . In other embodiments, the data signal line can also be used to provide the initialization voltage.
存储电容C1耦合于第一节点A和第二节点B之间。The storage capacitor C1 is coupled between the first node A and the second node B.
本实施例中像素电路的驱动信号波形图如图2所示，该像素电路工作过程中一帧时间T(一帧周期)可分为五个阶段：初始化阶段、阈值补偿阶段、数据写入阶段、迁移率补偿阶段和发光阶段。The drive signal waveform diagram of the pixel circuit in this embodiment is shown in Figure 2, and one frame time T (one frame period) in the working process of the pixel circuit can be divided into five stages: initialization stage, threshold value compensation stage, data writing stage , the mobility compensation stage and the luminescence stage.
(1)初始化阶段(1) Initialization phase
在初始化阶段，发光控制信号VEM和扫描信号VSCAN为高电平VH，第二晶体管T2和第三晶体管T3分别响应发光控制信号VEM和扫描信号VSCAN而导通，数据信号线提供的电压为参考电压VREF，第一节点A和驱动晶体管T1的控制极通过导通的晶体管T3和T2初始化到参考电压VREF，与此同时，驱动晶体管T1处于导通状态，第一电平端VDD提供的电压为一初始化低电平信号VDDL，第二节点B的电压通过驱动晶体管T1放电至VDDL。从而，完成了对第一节点A和第二节点B的电压初始化操作。In the initialization stage, the light emission control signal VEM and the scan signal VSCAN are at high level VH , the second transistor T2 and the third transistor T3 are turned on in response to the light emission control signal VEM and the scan signal VSCAN respectively, and the data signal line provides The voltage is the reference voltage VREF , the first node A and the control electrode of the driving transistor T1 are initialized to the reference voltage VREF through the turned-on transistors T3 and T2, and at the same time, the driving transistor T1 is in the turned-on state, and the first level terminal The voltage provided by VDD is an initialization low-level signal VDDL , and the voltage of the second node B is discharged to VDDL through the driving transistor T1 . Thus, the voltage initialization operation on the first node A and the second node B is completed.
(2)在阈值补偿阶段(2) In the threshold compensation stage
发光控制信号VEM和扫描信号VSCAN保持为高电平VH，数据信号线上的电压保持为参考电压VREF，因此，第一节点A和驱动晶体管T1的控制极的电压保持为VREF；第一电平端VDD提供的信号由低电平VDDL转变为高电平VDDH，因此，VDDH通过导通的驱动晶体管T1给第二节点B充电直至驱动晶体管T1截止，此时，第二节点B的电压升高到VREF-VTH，其中VTH为驱动晶体管T1的阈值电压，从而可以提取到驱动晶体管T1的阈值电压VTH信息。也即是说，阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息被存储在存储电容C1两端。为了获得高对比度，此时VREF-VTH可以小于发光元件OLED的阈值电压。The light-emitting control signal VEM and the scanning signal VSCAN are kept at high level VH , the voltage on the data signal line is kept at the reference voltage VREF , therefore, the voltage at the first node A and the control electrode of the driving transistor T1 is kept at VREF ; The signal provided by the first level terminal VDD changes from a low level VDDL to a high level VDDH , therefore, VDDH charges the second node B through the turned-on drive transistor T1 until the drive transistor T1 is turned off. At this time, The voltage of the second node B rises to VREF -VTH , wherein VTH is the threshold voltage of the driving transistor T1 , so that the threshold voltage VTH information of the driving transistor T1 can be extracted. That is to say, after the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored at both ends of the storage capacitor C1. In order to obtain high contrast ratio, VREF -VTH can be lower than the threshold voltage of the light emitting element OLED at this time.
(3)数据写入阶段(3) Data writing stage
发光控制信号VEM为低电平VL，第二晶体管T2在发光控制信号VEM控制下处于截止状态，扫描信号VSCAN为高电平VH，第三晶体管T3响应扫描信号VSCAN的高电平而导通，并向节点A传输数据信号线上提供的数据信号，此时数据信号线上提供的数据信号电压为数据电压VDATA，该数据电压通过导通的第三晶体管T3刷新第一节点A的电压至VDATA，第二节点B的电压在第一节点A的电压从VREF充电到VDATA的过程中，通过存储电容C1和发光元件OLED的本征电容COLED的耦合作用被耦合到VBI：The luminescence control signal VEM is low level VL , the second transistor T2 is in an off state under the control of the luminescence control signal VEM , the scanning signal VSCAN is high level VH , and the third transistor T3 responds to the high level of the scanning signal VSCAN The level is turned on, and the data signal provided on the data signal line is transmitted to node A. At this time, the data signal voltage provided on the data signal line is the data voltage VDATA , and the data voltage is refreshed by the third transistor T3 which is turned on. The voltage of the first node A to VDATA , the voltage of the second node B is in the process of charging the voltage of the first node A from VREF to VDATA , through the coupling effect of the storage capacitor C1 and the intrinsic capacitance C OLED of the light-emitting elementOLED is coupled to VBI :
其中，VBI为第二节点B的电压，C1和COLED分别是存储电容C1和发光元件OLED的本征电容的电容值。因此，此时第一节点A和第二节点B之间的电压差为Wherein, VBI is the voltage of the second node B, C1 and COLED are the capacitance values of the storage capacitor C1 and the intrinsic capacitance of the light emitting element OLED respectively. Therefore, the voltage difference between the first node A and the second node B at this time is
(4)迁移率补偿阶段(4) Mobility compensation stage
发光控制信号VEM为从低电平VL转换为高电平VH，第二晶体管T2从截止状态转换为导通状态，扫描信号VSCAN保持为高电平VH，第三晶体管T3处于导通状态，数据信号线上提供的信号电压保持为数据电压VDATA，因此第一节点A的电压保持为VDATA，驱动晶体管T1的控制极的电压为VDATA，从而驱动晶体管T1导通，并开始对第二节点B充电，使B点的电压抬升ΔVB，ΔVB可以表示为：The light-emitting control signal VEM is switched from low level VL to high level VH , the second transistor T2 is switched from off state to on state, the scanning signal VSCAN is kept at high level VH , and the third transistor T3 is in In the conduction state, the signal voltage provided on the data signal line remains at the data voltage VDATA , so the voltage at the first node A remains at VDATA , and the voltage at the control electrode of the drive transistor T1 is VDATA , so that the drive transistor T1 is turned on, And start to charge the second node B, so that the voltage at point B increases by ΔVB , ΔVB can be expressed as:
其中i(t)为驱动晶体管T1导通过程中的电流。由于迁移率补偿的时间Δt比较短，流过驱动晶体管T1的电流可以看成为恒定的电流IOLED0，该电流由数据写入阶段存储电容两端的电压差决定，IOLED0可以表示为：Wherein i(t) is the current during the conduction process of the driving transistor T1. Since the mobility compensation time Δt is relatively short, the current flowing through the driving transistor T1 can be regarded as a constant current IOLED0 , which is determined by the voltage difference across the storage capacitor during the data writing phase. IOLED0 can be expressed as:
其中，μ、COX和W/L分别为驱动晶体管T1的迁移率、单位面积栅氧化层电容和宽长比。因此，ΔVB可以进一步表示为：Wherein, μ, COX and W/L are respectively the mobility of the driving transistor T1, the capacitance of the gate oxide layer per unit area, and the width-to-length ratio. Therefore, ΔVB can be further expressed as:
其中IOLED0为如公式(4)中所示，可以看出IOLED0与驱动晶体管T1的阈值电压无关，与驱动晶体管T1的迁移率有关，如果驱动晶体管T1的迁移率大，则ΔVB增大，否则，ΔVB减小。C1两端(即第一节点A和第二节点B之间)形成了发光过程中的基准电压，该基准电压为Where IOLED0 is as shown in the formula (4), it can be seen that IOLED0 has nothing to do with the threshold voltage of the driving transistor T1, and is related to the mobility of the driving transistor T1. If the mobility of the driving transistor T1 is large, then ΔVB increase, otherwise, ΔVB decreases. The two ends of C1 (that is, between the first node A and the second node B) form a reference voltage during the light emitting process, and the reference voltage is
其中，ΔVB如公式(5)中所示，该基准电压会维持整个发光周期。Wherein, ΔVB is as shown in the formula (5), and the reference voltage will maintain the whole light-emitting period.
(5)发光阶段(5) Lighting stage
发光控制信号VEM保持为高电平VH，第二晶体管T2处于导通状态，扫描信号VSCAN为低电平VL，第三晶体管T3关断(即处于截止状态)，使得第一节点A悬，迁移率补偿阶段形成的基准电压驱动发光元件OLED开始发光，第二节点B的电压抬升至OLED发光时的电压VOLED。此时，由于第二晶体管T2导通，驱动晶体管T1的控制极的电压等于第一节点A的电压，由于第一节点A是悬空的，因此，当B点的电压抬升时，A点的电压也有相应的抬升，从而使第一节点A和第二节点B之间的电压差保持公式(6)中的基准电压不变，由于此时驱动晶体管T1工作在饱和区，因此流过OLED的电流可以表示为：The luminescence control signal VEM is kept at a high level VH , the second transistor T2 is in an on state, the scanning signal VSCAN is at a low level VL , and the third transistor T3 is turned off (that is, in a cut-off state), so that the first node A is suspended, and the reference voltage formed in the mobility compensation stage drives the light-emitting element OLED to start emitting light, and the voltage of the second node B rises to the voltage VOLED when the OLED emits light. At this time, since the second transistor T2 is turned on, the voltage of the control electrode of the driving transistor T1 is equal to the voltage of the first node A, and since the first node A is suspended, when the voltage of point B rises, the voltage of point A There is also a corresponding rise, so that the voltage difference between the first node A and the second node B keeps the reference voltage in formula (6) unchanged. Since the driving transistor T1 is working in the saturation region at this time, the current flowing through the OLED It can be expressed as:
由于ΔVB与驱动晶体管T1的阈值电压无关，因此，从(7)中可以看出，最终流过发光元件OLED的电流与驱动晶体管T1的阈值电压以及OLED本身的阈值电压都无关，从而，本实施例的像素电路可以很好地补偿驱动晶体管T1和OLED的阈值电压的变化造成的不均匀性。Since ΔVB has nothing to do with the threshold voltage of the drive transistor T1, it can be seen from (7) that the current flowing through the light-emitting element OLED has nothing to do with the threshold voltage of the drive transistor T1 and the threshold voltage of the OLED itself. The pixel circuit of the embodiment can well compensate the inhomogeneity caused by the variation of the threshold voltage of the driving transistor T1 and the OLED.
关于对迁移率的补偿，从公式(4)和(5)可以知道，当迁移率μ增大时，ΔVB增大，公式(7)中的平方项减小，补偿了因迁移率增大造成的OLED电流变大；为了得到合理的迁移率补偿时间，利用|dIOLED/dμ|2<ε，ε为某一很小的量(如，0<ε<0.1)，通过解方程可以得到合适的迁移率补偿时间，该迁移率补偿时间是利用发光控制信号线和扫描信号线来实现的，并没有引入多余的控制信号线。Regarding the compensation for mobility, it can be known from formulas (4) and (5) that when the mobility μ increases, ΔVB increases, and the square term in formula (7) decreases, compensating for the increased mobility The resulting OLED current becomes larger; in order to obtain a reasonable mobility compensation time, use |dIOLED /dμ | The appropriate mobility compensation time is realized by using the light emitting control signal line and the scanning signal line, and no redundant control signal line is introduced.
通过以上分析可知，本实施例的优点是，电路结构相对简单，只采用三个晶体管和一个存储电容，即可增加像素开口率，能够减小发光元件OLED的电流密度，以此为提高发光元件OLED使用寿命提供可能；像素电路采用充电式的阈值提取方式，即源跟随器结构，对于正负阈值都有补偿作用，所以这种方法对于采用耗尽型的晶体管也同样有效；此外该像素电路还可以补偿驱动管的迁移率变化造成的不均匀。From the above analysis, it can be seen that the advantage of this embodiment is that the circuit structure is relatively simple, and only three transistors and one storage capacitor are used to increase the pixel aperture ratio and reduce the current density of the light-emitting element OLED. The service life of OLED is possible; the pixel circuit adopts a charging threshold extraction method, that is, the source follower structure, which has a compensation effect on positive and negative thresholds, so this method is also effective for depletion-type transistors; in addition, the pixel circuit It is also possible to compensate for inhomogeneities caused by changes in the mobility of the drive tube.
实施例二：Embodiment two:
本实施例与上述实施例一不同之处在于，本实施例公开的像素电路中还包括第一初始化晶体管(为便于结合图示描述，也称其为第四晶体管)T4，用以向第二节点B提供相应的初始化电压，而实施例一中，第二节点B的初始化电压是通过第一电平端VDD提供。请参考图3，为本实施例公开的一种像素电路结构图。The difference between this embodiment and the first embodiment above is that the pixel circuit disclosed in this embodiment also includes a first initialization transistor (for the convenience of description in conjunction with the figure, it is also called a fourth transistor) T4, which is used to The node B provides a corresponding initialization voltage, and in the first embodiment, the initialization voltage of the second node B is provided through the first level terminal VDD . Please refer to FIG. 3 , which is a structure diagram of a pixel circuit disclosed in this embodiment.
第四晶体管T4的第二电极耦合至第二节点B，第四晶体管T4的第一电极用于输入初始化电压VR，第四晶体管T4的控制极耦合至初始化扫描信号线，用于响应初始化扫描信号VINT。在初始化阶段，第四晶体管T4响应初始化扫描信号VINT而导通，从而在初始化阶段，第四晶体管T4的第一电极输入的初始化电位由VR提供，第二节点B的电压通过第四晶体管T4初始化到初始化低电压VR。The second electrode of the fourth transistor T4 is coupled to the second node B, the first electrode of the fourth transistor T4 is used to input the initialization voltage VR , the control electrode of the fourth transistor T4 is coupled to the initialization scanning signal line, and is used for responding to the initialization scanning signal VINT . In the initialization phase, the fourth transistor T4 is turned on in response to the initialization scanning signal VINT , so that in the initialization phase, the initialization potential input by the first electrode of the fourth transistor T4 is provided byVR , and the voltage of the second node B passes through the fourth transistor T4 is initialized to the initialization low voltageVR .
本实施例中像素电路的驱动信号波形图如图4a和图4b所示，该像素电路工作过程中一帧时间T(一帧周期)可分为五个阶段：初始化阶段、阈值补偿阶段、数据写入阶段、迁移率补偿阶段和发光阶段。以本实施例结合驱动波形图4a为例进行说明。The drive signal waveform diagrams of the pixel circuit in this embodiment are shown in Figure 4a and Figure 4b, one frame time T (one frame period) in the working process of the pixel circuit can be divided into five stages: initialization stage, threshold value compensation stage, data Writing phase, mobility compensation phase and light emitting phase. The present embodiment is described in conjunction with the driving waveform Fig. 4a as an example.
(1)初始化阶段(1) Initialization phase
在初始化阶段，发光控制信号VEM和扫描信号VSCAN为高电平VH，第二晶体管T2和第三晶体管T3分别响应发光控制信号VEM和扫描信号VSCAN而导通，数据信号线提供的电压为参考电压VREF，第一节点A和驱动晶体管T1的控制极通过导通的晶体管T3和T2初始化到参考电压VREF，与此同时，初始化扫描信号VINT为高电平VH，第四晶体管T4处于导通状态，第二节点B的电压通过第四晶体管T4放电至低电压VR。从而，完成了对第一节点A和第二节点B的电压初始化。In the initialization stage, the light emission control signal VEM and the scan signal VSCAN are at high level VH , the second transistor T2 and the third transistor T3 are turned on in response to the light emission control signal VEM and the scan signal VSCAN respectively, and the data signal line provides The voltage is the reference voltage VREF , the first node A and the control electrode of the drive transistor T1 are initialized to the reference voltage VREF through the turned-on transistors T3 and T2, and at the same time, the initialization scanning signal VINT is a high level VH , The fourth transistor T4 is turned on, and the voltage of the second node B is discharged to the low voltageVR through the fourth transistor T4. Thus, voltage initialization of the first node A and the second node B is completed.
(2)在阈值补偿阶段(2) In the threshold compensation stage
发光控制信号VEM和扫描信号VSCAN保持为高电平VH，数据信号线Data Line上的电压保持为参考电压VREF，因此，第一节点A和驱动晶体管T1的控制极的电压保持为VREF；初始化扫描信号VINT从高电平VH转换为低电平VL，第四晶体管T4关断，第一电平端VDD通过导通的驱动晶体管T1对第二节点B充电直至驱动晶体管截止，此时，第二节点B的电压升高到VREF-VTH，其中VTH为驱动晶体管T1的阈值电压。阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息被存储在存储电容C1两端。为了获得高对比度，此时VREF-VTH可以小于发光元件OLED的阈值电压。The light emission control signal VEM and the scanning signal VSCAN are kept at high level VH , the voltage on the data signal line Data Line is kept at the reference voltage VREF , therefore, the voltage at the first node A and the gate electrode of the driving transistor T1 is kept as VREF ; the initialization scan signal VINT is switched from high level VH to low level VL , the fourth transistor T4 is turned off, and the first level terminal VDD charges the second node B through the turned-on driving transistor T1 until it is driven The transistor is turned off, and at this moment, the voltage of the second node B rises to VREF -VTH , where VTH is the threshold voltage of the driving transistor T1. After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored at both ends of the storage capacitor C1. In order to obtain high contrast ratio, VREF -VTH can be lower than the threshold voltage of the light emitting element OLED at this time.
其他阶段与实施例一的相应阶段相似，不再赘述。The other stages are similar to the corresponding stages in Embodiment 1, and will not be repeated here.
采用本实施例的像素点路结合驱动波形图4b的分析与上述过程类似，不同在于，初始化阶段第一节点A是悬空的，其电压会被初始化的B点电压拉低。The analysis of the pixel point circuit combined with the drive waveform in Figure 4b of this embodiment is similar to the above process, the difference is that the first node A is suspended in the initialization phase, and its voltage will be pulled down by the voltage of point B for initialization.
通过以上分析可知，除了可以补偿阈值电压变化和迁移率变化之外，本实施例的优点还在于，第一电平端VDD为恒定的高电平电源信号，不再为脉冲信号。当第一电平端VDD为恒定电压时，时序控制更易实现。From the above analysis, it can be known that, in addition to compensating for changes in threshold voltage and mobility, the advantage of this embodiment is that the first level terminal VDD is a constant high-level power supply signal and no longer a pulse signal. Timing control is easier to implement when the first level terminal VDD is a constant voltage.
实施例三：Embodiment three:
请参考图5，为本实施例公开的像素电路结构图，与上述实施例二不同之处在于，第四晶体管T4的控制极耦合至同一扫描帧内前一级扫描信号线(即上一行像素电路的扫描信号线)，第四晶体管T4响应上一行的扫描信号完成对第二节点B的初始化。Please refer to FIG. 5 , which is a structural diagram of the pixel circuit disclosed in this embodiment. The difference from the second embodiment above is that the control electrode of the fourth transistor T4 is coupled to the previous scan signal line in the same scan frame (that is, the previous row of pixels The scanning signal line of the circuit), the fourth transistor T4 completes the initialization of the second node B in response to the scanning signal of the previous row.
请参考图6，为图5所示像素电路的驱动时序图，本实施例像素电路的驱动过程与上述实施例一、实施例二大体相同，不同之处在于，初始化阶段发生在当前行(第n行)扫描信号VSCAN[n]到来之前，且第二节点B的初始化在上一行的扫描信号VSCAN[n-1]有效时进行，此时没有对A点初始化，A点的电压会被初始化的B点电压拉低。Please refer to FIG. 6 , which is a driving sequence diagram of the pixel circuit shown in FIG. 5 . The driving process of the pixel circuit in this embodiment is basically the same as that of the first and second embodiments above, except that the initialization phase occurs in the current row (the first row). Line n) before the scan signal VSCAN[n] arrives, and the initialization of the second node B is performed when the scan signal VSCAN[n-1] of the previous line is valid, at this time point A is not initialized, and the voltage of point A will be The initialized point B voltage is pulled down.
图5所示像素电路工作过程中一帧时间T(一帧周期)可分为五个阶段：初始化阶段、阈值补偿阶段、数据写入阶段、迁移率补偿阶段和发光阶段。下面将图5所示像素电路结合驱动波形图6进行说明，实际上，实施例二结合时序图4b的驱动过程与本实施例的大致相同。One frame time T (one frame period) in the working process of the pixel circuit shown in FIG. 5 can be divided into five stages: initialization stage, threshold value compensation stage, data writing stage, mobility compensation stage and light emitting stage. Next, the pixel circuit shown in FIG. 5 will be described in conjunction with the driving waveform in FIG. 6 . In fact, the driving process of the second embodiment combined with the timing diagram in FIG. 4 b is roughly the same as that of the present embodiment.
(1)初始化阶段(1) Initialization phase
在初始化阶段，发光控制信号VEM为高电平VH，第二晶体管T2导通，当前行的扫描信号VSCAN[n]为低电平VL，第三晶体管T3关断，上一行的第一扫描信号VSCAN[n-1]为高电平VH，第四晶体管T4打开，第二节点B的电压通过第四晶体管T4放电至低电压VR，由于第一节点A是悬空的，因此，第一节点A的电压也被初始化电压拉低到某一低电平，从而完成了对第一节点A和第二节点B的初始化。In the initialization phase, the light emission control signal VEM is at a high level VH , the second transistor T2 is turned on, the scan signal VSCAN[n] of the current row is at a low level VL , the third transistor T3 is turned off, and the The first scan signal VSCAN[n-1] is at a high level VH , the fourth transistor T4 is turned on, and the voltage of the second node B is discharged to a low voltageVR through the fourth transistor T4, since the first node A is floating , therefore, the voltage of the first node A is also pulled down to a certain low level by the initialization voltage, thereby completing the initialization of the first node A and the second node B.
(2)阈值补偿阶段(2) Threshold compensation stage
上一行的扫描信号VSCAN[n-1]为从高电平VH转换为低电平VL，第四晶体管T4关断，第三晶体管T3响应当前行的扫描信号VSCAN[n]打开，发光控制信号VEM保持为高电平VH，因此第二晶体管T2打开，驱动晶体管T1的控制极与第一节点A耦合在一起，由于此时数据信号线Data Line上的电压为参考电压VREF，因此，第一节点A和驱动管的控制极的电压为VREF；第一电平端VDD通过导通的驱动晶体管T1对第二节点B充电直至驱动晶体管截止，此时，第二节点B的电压升高到VREF-VTH，其中VTH为驱动晶体管T1的阈值电压。阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息被存储在存储电容C1两端。需要注意的是，VREF-VTH小于发光元件OLED的阈值电压以获得高对比度。The scan signal VSCAN[n-1] of the previous row is converted from high level VH to low level VL , the fourth transistor T4 is turned off, and the third transistor T3 is turned on in response to the scan signal VSCAN[n] of the current row , the light emission control signal VEM is kept at a high level VH , so the second transistor T2 is turned on, and the control electrode of the drive transistor T1 is coupled with the first node A. Since the voltage on the data signal line Data Line is the reference voltage at this time VREF , therefore, the voltage of the first node A and the control electrode of the driving transistor is VREF ; the first level terminal VDD charges the second node B through the turned-on driving transistor T1 until the driving transistor is turned off, at this time, the second The voltage at node B rises to VREF -VTH , where VTH is the threshold voltage of drive transistor T1. After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored at both ends of the storage capacitor C1. It should be noted that VREF -VTH is smaller than the threshold voltage of the light-emitting element OLED to obtain high contrast.
其他阶段与实施例一的相应阶段相似，不再赘述。The other stages are similar to the corresponding stages in Embodiment 1, and will not be repeated here.
通过以上分析可知，除了可以补偿阈值电压变化和迁移率变化之外，本实施例的优点还在于减少了一根扫描信号线，其用上一行的扫描信号来完成当前行的初始化，可以增大像素的开口率，减少外围电路的复杂度。From the above analysis, it can be seen that, in addition to compensating for changes in threshold voltage and mobility, the advantage of this embodiment is that one scanning signal line is reduced, and the scanning signal of the previous line is used to complete the initialization of the current line, which can increase The aperture ratio of the pixel reduces the complexity of the peripheral circuit.
实施例四：Embodiment four:
请参考图7a、图7b和图7c，为本实施例公开的三种像素电路结构图，与上述实施例二不同之处在于，本实施例中第四晶体管T4的第一电极耦合至数据信号线(如图7a所示)，或者第四晶体管T4的第一电极耦合至第二晶体管T2的第一电极(如图7b所示)，或者第四晶体管T4的第一电极耦合至第二晶体管T2的第二电极(如图7c所示)，第四晶体管T4响应初始化控制信号VRST，从而在初始化阶段第四晶体管T4的第一电极输入的初始化电位由数据信号线提供，由此利用数据信号线提供的初始化电压信号VR完成对第一节点A和第二节点B的初始化。Please refer to FIG. 7a, FIG. 7b and FIG. 7c, which are three pixel circuit structure diagrams disclosed in this embodiment. The difference from the second embodiment above is that the first electrode of the fourth transistor T4 in this embodiment is coupled to the data signal line (as shown in Figure 7a), or the first electrode of the fourth transistor T4 is coupled to the first electrode of the second transistor T2 (as shown in Figure 7b), or the first electrode of the fourth transistor T4 is coupled to the second transistor The second electrode of T2 (as shown in Figure 7c), the fourth transistor T4 responds to the initialization control signal VRST , so that the initialization potential input by the first electrode of the fourth transistor T4 in the initialization phase is provided by the data signal line, thereby using the data The initialization voltage signalVR provided by the signal line completes the initialization of the first node A and the second node B.
请参考图8，为本实施例所示像素电路的驱动时序图，本实施例像素电路的驱动过程与上述实施例大体相似，不同之处在于，在初始化阶段，初始化电压信号由数据信号线提供，第四晶体管T4响应初始化扫描信号，完成对像素电路的初始化。Please refer to FIG. 8 , which is a driving sequence diagram of the pixel circuit shown in this embodiment. The driving process of the pixel circuit in this embodiment is generally similar to that of the above-mentioned embodiment. The difference is that in the initialization stage, the initialization voltage signal is provided by the data signal line. , the fourth transistor T4 responds to the initialization scan signal to complete the initialization of the pixel circuit.
本实施例的像素电路工作过程中一帧时间T(一帧周期)可分为五个阶段：初始化阶段、阈值补偿阶段、数据写入阶段、迁移率补偿阶段和发光阶段。下面将图7a所示像素电路结合驱动波形图8对本实施例的像素电路的具体操作进行说明，图7b和图7c所示像素电路的具体操作与此类似，故不做重述。One frame time T (one frame period) in the working process of the pixel circuit in this embodiment can be divided into five stages: initialization stage, threshold value compensation stage, data writing stage, mobility compensation stage and light emitting stage. Next, the specific operation of the pixel circuit shown in FIG. 7a will be described in combination with the driving waveform shown in FIG. 8. The specific operations of the pixel circuit shown in FIG. 7b and FIG. 7c are similar, so they will not be repeated.
(1)初始化阶段(1) Initialization phase
在初始化阶段，数据信号线上的电压信号为低电平信号VR。发光控制信号VEM、扫描信号VSCAN和初始化控制信号VRST均为高电平VH，因此，第二晶体管T2、第三晶体管T3和第四晶体管T4都导通，因此，第一节点A和第二节点B的电压都被初始化到低电平信号VR，从而完成了对第一节点A和第二节点B的初始化。In the initialization stage, the voltage signal on the data signal line is a low-level signalVR . The light emission control signal VEM , the scan signal VSCAN and the initialization control signal VRST are all at a high level VH , therefore, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned on, therefore, the first node A Both the voltages of the first node A and the second node B are initialized to the low-level signalVR , thereby completing the initialization of the first node A and the second node B.
(2)在阈值补偿阶段(2) In the threshold compensation stage
初始化扫描信号从高电平VH转换为低电平VL，第四晶体管T4关断，扫描信号VSCAN和发光控制信号VEM保持为高电平VH以使第二晶体管T2和第三晶体管T3保持导通，驱动晶体管T1的控制极与第一节点A耦合在一起，由于此时数据信号线上的电压为参考电压VREF，因此，第一节点A和驱动晶体管T1的控制极的电压为VREF；第一电平端VDD通过导通的驱动晶体管T1对第二节点B充电直至驱动晶体管T1截止，此时，第二节点B的电压升高到VREF-VTH，其中VTH为驱动晶体管T1的阈值电压。阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息被存储在存储电容C1两端。为获得高对比度，VREF-VTH可以小于发光元件OLED的阈值电压。The initialization scanning signal is converted from high level VH to low level VL , the fourth transistor T4 is turned off, and the scanning signal VSCAN and the light-emitting control signal VEM are kept at high level VH to make the second transistor T2 and the third transistor T2 Transistor T3 remains turned on, and the control electrode of the driving transistor T1 is coupled with the first node A. Since the voltage on the data signal line is the reference voltage VREF at this time, the connection between the first node A and the control electrode of the driving transistor T1 The voltage is VREF ; the first level terminal VDD charges the second node B through the turned-on drive transistor T1 until the drive transistor T1 is cut off, at this time, the voltage of the second node B rises to VREF -VTH , where VTH is the threshold voltage of the driving transistor T1. After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored at both ends of the storage capacitor C1. To obtain high contrast, VREF -VTH can be less than the threshold voltage of the light emitting element OLED.
其他阶段与实施例一的相应阶段相似，不再赘述。The other stages are similar to the corresponding stages in Embodiment 1, and will not be repeated here.
通过以上分析可知，除了可以补偿阈值电压变化和迁移率变化之外，本实施例的优点还在于，通过利用数据信号线提供的初始化电压信号可以使面板减少一个低电平电压。From the above analysis, it can be seen that, in addition to compensating for changes in threshold voltage and mobility, the advantage of this embodiment is that the panel can be reduced by a low-level voltage by using the initialization voltage signal provided by the data signal line.
实施例五：Embodiment five:
请参考图9，为本实施例公开的像素电路结构图，与上述各实施例不同之处在于，第四晶体管T4的控制极耦合至第四晶体管T4的第二电极；第四晶体管T4的第一电极耦合至初始化控制信号VRET，第二节点B的电压通过二极管接法的第四晶体管T4放电，完成对第二节点B的初始化。完成初始化以后，初始化控制信号保持高电平使得第四晶体管T4关断，不再影响电路的工作。Please refer to FIG. 9 , which is a structural diagram of the pixel circuit disclosed in this embodiment. The difference from the above-mentioned embodiments is that the control electrode of the fourth transistor T4 is coupled to the second electrode of the fourth transistor T4; the second electrode of the fourth transistor T4 One electrode is coupled to the initialization control signal VRET , and the voltage of the second node B is discharged through the diode-connected fourth transistor T4 to complete the initialization of the second node B. After the initialization is completed, the initialization control signal maintains a high level so that the fourth transistor T4 is turned off, which no longer affects the operation of the circuit.
请参考图10，为图9所示电路的驱动过程时序图，本实施例像素电路的驱动过程与实施例二的驱动过程大致相似，不同之处在于，初始化阶段第二节点B的初始化电压提供方式和阈值补偿阶段第四晶体管T4的关闭方式。下面结合驱动时序图10a以及图9所示像素电路对像素电路的工作过程进行描述。该像素电路工作过程中一帧时间T(一帧周期)可分为五个阶段：初始化阶段、阈值补偿阶段、数据写入阶段、迁移率补偿阶段和发光阶段。Please refer to FIG. 10, which is a timing diagram of the driving process of the circuit shown in FIG. mode and the closing mode of the fourth transistor T4 in the threshold compensation stage. The working process of the pixel circuit will be described below in conjunction with the driving timing diagram 10 a and the pixel circuit shown in FIG. 9 . One frame time T (one frame period) in the working process of the pixel circuit can be divided into five stages: initialization stage, threshold value compensation stage, data writing stage, mobility compensation stage and light emitting stage.
(1)初始化阶段(1) Initialization phase
当前行的扫描信号VSCAN[n]和发光控制信号VEM为高电平VH，因此，第二晶体管T2和第三晶体管T3导通，第一节点A和驱动管T1的控制极被数据信号线上的电压VREF初始化到VREF；初始化脉冲电压信号VRET为低电平，第二节点B的电压被二极管接法的第四晶体管T4放电至低电平完成对第二节点B的初始化，从而完成了对第一节点A和第二节点B的初始化。The scanning signal VSCAN[n] and the light emission control signal VEM of the current row are at a high level VH , therefore, the second transistor T2 and the third transistor T3 are turned on, and the first node A and the gate electrode of the driving transistor T1 are controlled by the data The voltage VREF on the signal line is initialized to VREF ; the initialization pulse voltage signal VRET is at a low level, and the voltage of the second node B is discharged to a low level by the diode-connected fourth transistor T4 to complete the second node B initialization, thus completing the initialization of the first node A and the second node B.
(2)在阈值补偿阶段(2) In the threshold compensation stage
初始化脉冲电压信号VRET从低电平转换为高电平，则第四晶体管T4关断，第三晶体管T3和第二晶体管T2响应当前行的扫描信号VSCAN和发光控制信号VEM的高电平VH而打开，由于驱动晶体管T1的控制极与第一节点A耦合在一起，此时数据信号线上的电压为参考电压VREF，因此，第一节点A和驱动管的控制极的电压为VREF；第一电平端VDD通过导通的驱动晶体管T1对第二节点B充电直至驱动晶体管T1截止，此时，第二节点B的电压升高到VREF-VTH，其中VTH为驱动晶体管T1的阈值电压。阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息被存储在存储电容C1两端。为获得高对比度，VREF-VTH可以小于发光元件OLED的阈值电压。When the initialization pulse voltage signal VRET changes from low level to high level, the fourth transistor T4 is turned off, and the third transistor T3 and the second transistor T2 respond to the high level of the scanning signal VSCAN and the light emission control signal VEM of the current row. VH is turned on, since the control electrode of the drive transistor T1 is coupled with the first node A, the voltage on the data signal line is the reference voltage VREF at this time, therefore, the voltage of the first node A and the control electrode of the drive transistor is VREF ; the first level terminal VDD charges the second node B through the turned-on drive transistor T1 until the drive transistor T1 is cut off, at this time, the voltage of the second node B rises to VREF -VTH , where VTH is the threshold voltage of the driving transistor T1. After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored at both ends of the storage capacitor C1. To obtain high contrast, VREF -VTH can be less than the threshold voltage of the light emitting element OLED.
其他阶段与实施例一的相应阶段相似，不再赘述。The other stages are similar to the corresponding stages in Embodiment 1, and will not be repeated here.
在另一具体实施例中，其驱动时序如图10(b)所示。初始化时T3管保持关断，此时T4导通，B点被初始化到某一低电平，则A点也被初始化到低电平，完成初始化以后VRET为高电平，T4管关断，电路开始进入阈值提取阶段；在阈值提取阶段，第三晶体管T3和第二晶体管T2响应当前行的扫描信号VSCAN和发光控制信号VEM的高电平VH而打开，由于驱动晶体管T1的控制极与第一节点A耦合在一起，此时数据信号线上的电压为参考电压VREF，因此，第一节点A和驱动管的控制极的电压为VREF；第一电平端VDD通过导通的驱动晶体管T1对第二节点B充电直至驱动晶体管T1截止，此时，第二节点B的电压升高到VREF-VTH，其中VTH为驱动晶体管T1的阈值电压。阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息被存储在存储电容C1两端。为获得高对比度，VREF-VTH可以小于发光元件OLED的阈值电压。其他阶段与实施例一的相应阶段相似，不再赘述。In another specific embodiment, its driving sequence is shown in FIG. 10( b ). During initialization, the T3 tube remains off, at this time, T4 is turned on, point B is initialized to a certain low level, then point A is also initialized to a low level, after the initialization is completed, VRET is high level, and T4 tube is turned off , the circuit starts to enter the threshold value extraction phase; in the threshold value extraction phase, the third transistor T3 and the second transistor T2 are turned on in response to the high level VH of the scanning signal VSCAN and the light emission control signal VEM of the current row, due to the driving transistor T1 The control electrode is coupled with the first node A. At this time, the voltage on the data signal line is the reference voltage VREF , therefore, the voltage on the first node A and the control electrode of the drive transistor is VREF ; the first level terminal VDD passes through The turned-on driving transistor T1 charges the second node B until the driving transistor T1 is turned off, at this time, the voltage of the second node B rises to VREF -VTH , where VTH is the threshold voltage of the driving transistor T1 . After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored at both ends of the storage capacitor C1. To obtain high contrast, VREF -VTH can be less than the threshold voltage of the light emitting element OLED. The other stages are similar to the corresponding stages in Embodiment 1, and will not be repeated here.
通过以上分析可知，除了可以补偿阈值电压变化和迁移率变化之外，本实施例的优点还在于少了一根电源线，进而可以减少工艺复杂度，并简化结构。From the above analysis, it can be known that, in addition to compensating for changes in threshold voltage and mobility, the advantage of this embodiment is that there is one less power line, thereby reducing process complexity and simplifying the structure.
实施例六：Embodiment six:
请参考图11，为本实施例公开的一种像素电路结构图，与上述各实施例不同之处在于，本实施例公开的像素电路中还包括第二初始化晶体管(为便于结合图示描述，也称其为第五晶体管)T5，其作用为在阈值提取阶段为像素电路提供参考电压VREF。第一节点A所需的参考电压VREF和/或初始化电压由第五晶体管T5传输，数据信号线只提供数据信号VDATA，由此简化数据线的时序控制，通过合理的设计可以使像素电路的行时间减少，进一步容易满足高分辨率和高帧频的显示需求。上述实施例一至五均可以在其像素电路结构上作出适当的修改，以设计出包括第五晶体管T5的对应像素电路，例如，图11所示像素电路即是在实施例三的像素电路基础上增加第五晶体管T5而得到的具体电路结构，其它实施例也可以按类似方式设计得到。Please refer to FIG. 11 , which is a structural diagram of a pixel circuit disclosed in this embodiment. The difference from the above-mentioned embodiments is that the pixel circuit disclosed in this embodiment also includes a second initialization transistor (for convenience of description in conjunction with illustrations, It is also called the fifth transistor) T5, and its function is to provide the reference voltage VREF for the pixel circuit in the threshold value extraction stage. The reference voltage VREF and/or the initialization voltage required by the first node A are transmitted by the fifth transistor T5, and the data signal line only provides the data signal VDATA , thereby simplifying the timing control of the data line, and the pixel circuit can be made The line time is reduced, and it is further easy to meet the display requirements of high resolution and high frame rate. The above-mentioned embodiments 1 to 5 can be appropriately modified in the structure of the pixel circuit to design a corresponding pixel circuit including the fifth transistor T5. For example, the pixel circuit shown in FIG. 11 is based on the pixel circuit of the third embodiment The specific circuit structure obtained by adding the fifth transistor T5 can also be designed in a similar manner in other embodiments.
为了减少像素电路的控制信号，可以充分利用上面若干行的扫描信号来进行像素电路的初始化和阈值提取过程，如果设置每行的行时间等于阈值提取的时间，当前行像素为第n行，则第四晶体管的控制极可以耦合至第n-2行的扫描信号，第五晶体管T5的控制极耦合至第n-1行的扫描信号。In order to reduce the control signal of the pixel circuit, the scanning signals of several rows above can be fully used to perform the initialization of the pixel circuit and the threshold extraction process. If the row time of each row is set equal to the threshold extraction time, and the current row of pixels is the nth row, then The control electrode of the fourth transistor can be coupled to the scan signal of the n-2th row, and the control electrode of the fifth transistor T5 is coupled to the scan signal of the n-1th row.
具体地，本实施例的像素电路与实施例三中的像素电路的不同之处包括：像素电路还包括第五晶体管T5，第五晶体管T5的控制极耦合至第n-1行的扫描信号VSCAN[n-1]，第五晶体管T5的第一电极耦合至参考电压源信号VREF，第五晶体管T5的第二电极耦合至第一节点A；第四晶体管T4的控制极耦合至第n-2行的扫描信号VSCAN[n-2]。Specifically, the difference between the pixel circuit in this embodiment and the pixel circuit in the third embodiment includes: the pixel circuit further includes a fifth transistor T5, and the control electrode of the fifth transistor T5 is coupled to the scanning signal V of the n-1th rowSCAN[n-1] , the first electrode of the fifth transistor T5 is coupled to the reference voltage source signal VREF , the second electrode of the fifth transistor T5 is coupled to the first node A; the control electrode of the fourth transistor T4 is coupled to the nth - Scan signal VSCAN[n-2] for 2 lines.
图11所示像素电路工作过程中一帧时间T(一帧周期)可分为五个阶段：初始化阶段、阈值补偿阶段、数据写入阶段、迁移率补偿阶段和发光阶段。结合驱动波形图12对于该实施例与实施例三不同的地方进行说明。One frame time T (one frame period) in the working process of the pixel circuit shown in FIG. 11 can be divided into five stages: initialization stage, threshold compensation stage, data writing stage, mobility compensation stage and light emitting stage. The differences between this embodiment and the third embodiment will be described with reference to the driving waveforms in FIG. 12 .
(1)初始化阶段(1) Initialization phase
在初始化阶段，发光控制信号VEM为高电平VH，第二晶体管T2导通，当前行的扫描信号VSCAN[n]和第n-1行的扫描信号VSCAN[n-1]为低电平VL，第三晶体管T3和T5晶体管关断，第n-2行的扫描信号VSCAN[n-2]为高电平VH，第四晶体管T4打开，第二节点B的电压通过第四晶体管T4放电至低电压VR，由于第一节点A是悬空的，因此，第一节点A的电压也被初始化电压拉低到某一低电平，从而完成了对第一节点A和第二节点B的初始化。In the initialization phase, the light emission control signal VEM is at a high level VH , the second transistor T2 is turned on, and the scanning signal VSCAN[n] of the current row and the scanning signal VSCAN[n-1] of the n-1th row are Low level VL , the third transistor T3 and T5 transistors are turned off, the scanning signal VSCAN[n-2] of the n-2th row is high level VH , the fourth transistor T4 is turned on, the voltage of the second node B The fourth transistor T4 discharges to the low voltageVR , since the first node A is suspended, the voltage of the first node A is also pulled down to a low level by the initialization voltage, thereby completing the first node A and initialization of the second Node B.
(2)在阈值补偿阶段(2) In the threshold compensation stage
第n-2行的扫描信号VSCAN[n-2]从高电平VH转换为低电平VL，第四晶体管T4关断，当前行的扫描信号VSCAN[n]为低电平VL，第三晶体管T3关断，第五晶体管T5响应第n-1行的扫描信号VSCAN[n-1]导通，发光控制信号VEM保持为高电平VH，第二晶体管T2导通，驱动晶体管T1的控制极与第一节点A耦合在一起，因此，第一节点A和驱动晶体管T1的控制极的电压为VREF；第一电平端VDD通过导通的驱动晶体管T1对第二节点B充电直至驱动晶体管T1截止，此时，第二节点B的电压升高到VREF-VTH，其中VTH为驱动晶体管T1的阈值电压。阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息被存储在存储电容C1两端。为获得高对比度，VREF-VTH可以小于发光元件OLED的阈值电压。The scanning signal VSCAN[n-2] of the n-2th row is switched from high level VH to low level VL , the fourth transistor T4 is turned off, and the scanning signal VSCAN[n] of the current row is low level VL , the third transistor T3 is turned off, the fifth transistor T5 is turned on in response to the scanning signal VSCAN[n-1] of the n-1th row, the light emission control signal VEM is kept at a high level VH , the second transistor T2 is turned on, the control electrode of the drive transistor T1 is coupled with the first node A, therefore, the voltage of the first node A and the control electrode of the drive transistor T1 is VREF ; the first level terminal VDD passes through the conduction drive transistor T1 The second node B is charged until the driving transistor T1 is turned off, at this time, the voltage of the second node B rises to VREF -VTH , wherein VTH is the threshold voltage of the driving transistor T1 . After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored at both ends of the storage capacitor C1. To obtain high contrast, VREF -VTH can be less than the threshold voltage of the light emitting element OLED.
(3)数据写入阶段(3) Data writing stage
发光控制信号VEM为低电平VL，第二晶体管T2关断，第n-1行的扫描信号VSCAN[n-1]和第n-2行的扫描信号VSCAN[n-2]均为低电平VL，第四晶体管T4和第五晶体管T5关断；当前行的扫描信号VSCAN[n]为高电平VH，第三晶体管T3处于导通状态，数据信号线上提供的信号电压为数据电压VDATA，该数据电压通过导通的第三晶体管T3刷新第一节点A的电压至VDATA，第二节点B的电压在第一节点A的电压从VREF充电到VDATA的过程中，通过存储电容C1和发光元件OLED的本征电容COLED的耦合作用被耦合到VBI：The luminescence control signal VEM is low level VL , the second transistor T2 is turned off, the scanning signal VSCAN[n-1] of the n-1th row and the scanning signal VSCAN[n-2] of the n-2th row Both are low level VL , the fourth transistor T4 and the fifth transistor T5 are turned off; the scan signal VSCAN[n] of the current row is high level VH , the third transistor T3 is in the conduction state, and the data signal line The signal voltage provided is the data voltage VDATA , the data voltage refreshes the voltage of the first node A to VDATA through the turned-on third transistor T3, and the voltage of the second node B is charged from the voltage of the first node A from VREF to In the process of VDATA , it is coupled to VBI through the coupling effect of the storage capacitor C1 and the intrinsic capacitance COLED of the light-emitting element OLED:
其中，VBI为第二节点B的电压，C1和COLED分别是存储电容C1和发光元件OLED的本征电容的电容值。因此，此时第一节点A和第二节点B之间的电压差为Wherein, VBI is the voltage of the second node B, C1 and COLED are the capacitance values of the storage capacitor C1 and the intrinsic capacitance of the light emitting element OLED respectively. Therefore, the voltage difference between the first node A and the second node B at this time is
其他阶段与实施例一的相应阶段相似，不再赘述。The other stages are similar to the corresponding stages in Embodiment 1, and will not be repeated here.
通过以上分析可知，除了可以补偿阈值电压变化和迁移率变化之外，，本实施例虽然多了一个晶体管，但其充分利用了前面行的扫描信号线，减少了行时间，使得电路相对更适合大面积高分辨率显示。From the above analysis, it can be seen that, in addition to compensating for changes in threshold voltage and mobility, although this embodiment has one more transistor, it makes full use of the scanning signal lines in the previous row and reduces the row time, making the circuit relatively more suitable for Large area high resolution display.
实施例七：Embodiment seven:
请参考图13，为本实施例公开的一种像素电路结构图，与上述实施例六不同之处在于，本实施例公开的像素电路中的第五晶体管T5的控制极耦合至扫描控制信号线，第四晶体管T4的控制极耦合至前面某一行的扫描信号线。随着显示面板频率和分辨率的提高，每行的行时间越来越短，行时间不足以提供足够的时间来进行阈值提取，因为如果阈值提取的时间比较短，补偿的精度就会大大降低，因此希望的阈值提取的时间比较长又不增大行时间，采用本实施例可以满足高分辨率和高帧频的显示需求。Please refer to FIG. 13 , which is a structural diagram of a pixel circuit disclosed in this embodiment. The difference from the sixth embodiment above is that the control electrode of the fifth transistor T5 in the pixel circuit disclosed in this embodiment is coupled to the scanning control signal line. , the control electrode of the fourth transistor T4 is coupled to the scanning signal line of a certain row in front. With the increase of display panel frequency and resolution, the line time of each line is getting shorter and shorter, and the line time is not enough to provide enough time for threshold extraction, because if the threshold extraction time is relatively short, the compensation accuracy will be greatly reduced , so the desired threshold extraction time is relatively long without increasing the line time, and this embodiment can meet the display requirements of high resolution and high frame rate.
假设阈值提取的时间为行时间的a倍，a为整数，则第四晶体管的控制极耦合至第n-(a+1)行的扫描信号。本实施例以阈值提取时间为行时间的3倍设置(应理解，该倍数不限于3，其可以是其它数值的倍数)，则第四晶体管T4的控制极耦合至第n-4行的扫描信号，第五晶体管的控制极耦合至扫描控制信号VSC。为了提高阈值提取的精度，可以增大阈值提取时间。Assuming that the threshold extraction time is a times the row time, a is an integer, then the control electrode of the fourth transistor is coupled to the scan signal of the n-(a+1)th row. In this embodiment, the threshold value extraction time is set as 3 times of the row time (it should be understood that the multiple is not limited to 3, and it can be a multiple of other values), then the control electrode of the fourth transistor T4 is coupled to the scanning of the n-4th row signal, the control electrode of the fifth transistor is coupled to the scan control signal VSC . In order to improve the accuracy of threshold value extraction, the threshold value extraction time can be increased.
图14为本实施例的像素电路的驱动波形图，下面结合驱动波形图14对本实施例与实施例六不同的地方进行说明。图13所示像素电路工作过程中一帧时间T(一帧周期)可分为五个阶段：初始化阶段、阈值补偿阶段、数据写入阶段、迁移率补偿阶段和发光阶段。FIG. 14 is a driving waveform diagram of the pixel circuit of the present embodiment. The difference between the present embodiment and the sixth embodiment will be described below in conjunction with the driving waveform diagram 14 . One frame time T (one frame period) in the working process of the pixel circuit shown in FIG. 13 can be divided into five stages: initialization stage, threshold value compensation stage, data writing stage, mobility compensation stage and light emitting stage.
(1)初始化阶段(1) Initialization phase
在初始化阶段，发光控制信号VEM为高电平VH，第二晶体管T2导通，当前行的扫描信号VSCAN[n]和扫描控制信号VSC均为低电平VL，第三晶体管T3和T5晶体管关断，第n-4行的扫描信号VSCAN[n-4]为高电平VH，第四晶体管T4导通，第二节点B的电压通过第四晶体管T4放电至低电压VR，由于第一节点A是悬空的，因此，第一节点A的电压也被初始化电压拉低到某一低电平，从而完成了对第一节点A和第二节点B的初始化。In the initialization phase, the light-emitting control signal VEM is high level VH , the second transistor T2 is turned on, the scan signal VSCAN[n] of the current row and the scan control signal VSC are both low level VL , the third transistor Transistors T3 and T5 are turned off, the scanning signal VSCAN[n-4] of row n-4 is high level VH , the fourth transistor T4 is turned on, and the voltage of the second node B is discharged to a low level through the fourth transistor T4 As for the voltage VR , since the first node A is suspended, the voltage of the first node A is also pulled down to a low level by the initialization voltage, thereby completing the initialization of the first node A and the second node B.
(2)在阈值补偿阶段(2) In the threshold compensation stage
第n-4行的扫描控制信号VSCAN[n-4]从高电平VH转换为低电平VL，第四晶体管T4关断，当前行的第一扫描控制信号VSCAN[n]为低电平VL，第三晶体管T3关断，第五晶体管T5响应当前行的扫描控制信号VSC的高电平导通，发光控制信号VEM保持为高电平VH，第二晶体管T2打开，驱动晶体管T1的控制极与第一节点A耦合在一起，因此，第一节点A和驱动管的控制极的电压为VREF；第一电平端VDD通过导通的驱动晶体管T1对第二节点B充电直至驱动晶体管T1截止，此时，第二节点B的电压升高到VREF-VTH，其中VTH为驱动晶体管T1的阈值电压。阈值补偿阶段结束后，驱动晶体管T1的阈值电压信息被存储在存储电容C1两端。为获得高对比度，VREF-VTH可以小于发光元件OLED的阈值电压。The scan control signal VSCAN[n-4] of the n-4th row is switched from high level VH to low level VL , the fourth transistor T4 is turned off, and the first scan control signal VSCAN[n] of the current row is a low level VL , the third transistor T3 is turned off, the fifth transistor T5 is turned on in response to the high level of the scanning control signal VSC of the current row, the light emission control signal VEM is kept at a high level VH , the second transistor T5 T2 is turned on, and the control electrode of the drive transistor T1 is coupled with the first node A, therefore, the voltage of the first node A and the control electrode of the drive transistor is VREF ; the first level terminal VDD is connected to The second node B is charged until the driving transistor T1 is turned off, at this time, the voltage of the second node B rises to VREF -VTH , where VTH is the threshold voltage of the driving transistor T1 . After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored at both ends of the storage capacitor C1. To obtain high contrast, VREF -VTH can be less than the threshold voltage of the light emitting element OLED.
(3)数据写入阶段(3) Data writing stage
发光控制信号VEM为低电平VL，第二晶体管T2关断，第n-4行的扫描信号VSCAN[n-4]为低电平VL，第四晶体管T4关断；当前行的扫描控制信号VSC为低电平VL，第五晶体管T5关断；当前行的扫描信号VSCAN[n]为高电平VH，第三晶体管T3处于导通状态，数据信号线上提供的信号电压为数据电压VDATA，该数据电压通过导通的第三晶体管T3刷新第一节点A的电压至VDATA，第二节点B的电压在第一节点A的电压从VREF充电到VDATA的过程中，通过存储电容C1和发光元件OLED的本征电容COLED的耦合作用被耦合到VBI：The luminescence control signal VEM is low level VL , the second transistor T2 is turned off, the scanning signal VSCAN[n-4] of the n-4th row is low level VL , and the fourth transistor T4 is turned off; the current row The scanning control signal VSC of the current line is low level VL , the fifth transistor T5 is turned off; the scanning signal VSCAN[n] of the current line is high level VH , the third transistor T3 is in the conducting state, and the data signal line The signal voltage provided is the data voltage VDATA , the data voltage refreshes the voltage of the first node A to VDATA through the turned-on third transistor T3, and the voltage of the second node B is charged from the voltage of the first node A from VREF to In the process of VDATA , it is coupled to VBI through the coupling effect of the storage capacitor C1 and the intrinsic capacitance COLED of the light-emitting element OLED:
其中，VBI为第二节点B的电压，C1和COLED分别是存储电容C1和发光元件OLED的本征电容的电容值。因此，此时第一节点A和第二节点B之间的电压差为Wherein, VBI is the voltage of the second node B, C1 and COLED are the capacitance values of the storage capacitor C1 and the intrinsic capacitance of the light emitting element OLED respectively. Therefore, the voltage difference between the first node A and the second node B at this time is
其他阶段与实施例一的相应阶段相似，不再赘述。The other stages are similar to the corresponding stages in Embodiment 1, and will not be repeated here.
通过以上分析可知，除了可以补偿阈值电压变化和迁移率变化之外，本实施例虽然多了一根控制信号线，但行时间进一步缩短为数据写入和迁移率补偿的时间，使得电路相对更适合大面积高分辨率显示。From the above analysis, it can be seen that in addition to compensating for changes in threshold voltage and mobility, although this embodiment has an additional control signal line, the line time is further shortened to the time for data writing and mobility compensation, making the circuit relatively more efficient. Suitable for large area high resolution display.
以上各实施例还可根据具体的情况采用同时发光或者分组驱动的形式来完成电路的驱动操作，采用同时发光和分组驱动的过程中整个面板或者同组的像素电路的阈值提取是同时进行的，这样可以缩短每行的有效变成时间，跟适合大面积和高分辨率的显示器需求。The above embodiments can also use simultaneous lighting or group driving to complete the driving operation of the circuit according to the specific situation. In the process of simultaneous lighting and group driving, the threshold value extraction of the entire panel or the same group of pixel circuits is performed simultaneously. In this way, the effective conversion time of each row can be shortened, which is suitable for the display requirements of large area and high resolution.
此外，以上实施例应用于本申请实施例的显示装置时，在一种实施例中，扫描线向对应像素电路提供的扫描信号可以是例如初始化控制信号VRST、扫描信号VSCAN、发光控制信号VEM等。其它实施例中，像素电路所需的有些扫描信号也可以通过全局线(例如图15所示)的方式来提供，比如第一电平端所需的电源线、初始化控制信号VINT所需的初始化控制线VR等，本领域技术人员可以依据具体像素电路的需求进行调整。In addition, when the above embodiments are applied to the display device of the embodiment of the present application, in one embodiment, the scan signal provided by the scan line to the corresponding pixel circuit can be, for example, the initialization control signal VRST , the scan signal VSCAN , the light emission control signalVEM et al. In other embodiments, some scanning signals required by the pixel circuit can also be provided through global lines (such as shown in FIG. 15 ), such as the power line required for the first level end, the initialization required for the initialization control signal VINT Those skilled in the art can adjust the control lineVR and the like according to the requirements of specific pixel circuits.
基于上述实施例公开的像素电路，本申请一实施例还公开了一种显示电路驱动方法，该显示电路采用上述实施例的像素电路，其中像素电路的每一驱动周期包括初始化阶段、阈值补偿阶段、数据写入阶段，迁移率补偿阶段和发光阶段，驱动方法包括：Based on the pixel circuit disclosed in the above embodiment, an embodiment of the present application also discloses a display circuit driving method. The display circuit adopts the pixel circuit in the above embodiment, wherein each driving cycle of the pixel circuit includes an initialization phase and a threshold compensation phase. , data writing stage, mobility compensation stage and light emitting stage, the driving method includes:
在初始化阶段，第二晶体管T2导通和第三晶体管T3导通，分别初始化存储电容C1两端的电压和驱动晶体管T1控制极的电压。在其它实施例中，还可以通过导通的第四晶体管T4和第五晶体管T5辅助初始化存储电容C1两端的电压。In the initialization phase, the second transistor T2 and the third transistor T3 are turned on, respectively initializing the voltage at both ends of the storage capacitor C1 and the voltage at the control electrode of the driving transistor T1 . In other embodiments, the turned-on fourth transistor T4 and fifth transistor T5 can also assist in initializing the voltage across the storage capacitor C1.
在阈值补偿阶段，第三晶体管T3和/或第五晶体管T5导通，向驱动晶体管T1控制极提供参考电压，读取驱动晶体管T1的阈值电压信息并通过存储电容C1存储。在一种实施例中，可以通过第三晶体管T3提供参考电压；在另一种实施例中，也可以通过第五晶体管T5提供参考电压。In the threshold compensation phase, the third transistor T3 and/or the fifth transistor T5 are turned on to provide a reference voltage to the control electrode of the driving transistor T1, read the threshold voltage information of the driving transistor T1 and store it through the storage capacitor C1. In one embodiment, the reference voltage may be provided through the third transistor T3; in another embodiment, the reference voltage may also be provided through the fifth transistor T5.
在数据写入阶段，第三晶体管T3导通传输数据电压VDATA，通过串联的存储电容和发光器件的本征电容的分压将数据电压VDATA和阈值电压VTH存储于存储电容C1两端。In the data writing stage, the third transistor T3 is turned on to transmit the data voltage VDATA , and the data voltage VDATA and the threshold voltage VTH are stored at both ends of the storage capacitor C1 through the voltage division of the storage capacitor connected in series and the intrinsic capacitance of the light emitting device. .
在迁移率补偿阶段，第三晶体管T3导通使第一节点A的电压保持为数据电压VDATA，第二晶体管T2导通使驱动管导通给B点充电，B点电压的改变量只与驱动管的迁移率有关，与阈值电压无关，通过合理的控制导通时间完成迁移率的补偿。In the mobility compensation stage, the third transistor T3 is turned on to keep the voltage of the first node A at the data voltage VDATA , the second transistor T2 is turned on to turn on the drive transistor to charge point B, and the change of the voltage of point B is only the same as The mobility of the drive tube is related to the threshold voltage, and the compensation of the mobility is completed through reasonable control of the conduction time.
在发光阶段，驱动晶体管T1根据存储电容C1两端的压差驱动产生驱动电流，并驱动发光元件OLED发光。In the light-emitting phase, the driving transistor T1 is driven to generate a driving current according to the voltage difference across the storage capacitor C1, and drives the light-emitting element OLED to emit light.
本申请实施例提供的像素电路通过源跟随的形式产生驱动晶体管的阈值电压信息，通过电荷分压的形式在存储电容两端产生驱动晶体管的阈值电压和灰度信息有关的电压信息以补偿驱动晶体管的阈值电压，完成数据写入以后保持电路其他状态不变提前打开发光控制管，存储电容两端的信息将改变ΔV最终形成发光过程中的基准电压。其中，ΔV与阈值电压无关，只与驱动晶体管的迁移率有关从而补偿的迁移率变化。发光过程中，该基准电压保持不变，使得流过发光器件的驱动电流与驱动晶体管和发光元件的阈值电压无关，并且利用控制信号交叠改善驱动管的迁移率变化对像素电路亮度均匀性的影响，解决了显示面板由于阈值电压和迁移率变化造成的显示不均匀问题。The pixel circuit provided by the embodiment of the present application generates the threshold voltage information of the driving transistor in the form of source follower, and generates the threshold voltage of the driving transistor and the voltage information related to the grayscale information at both ends of the storage capacitor in the form of charge division to compensate the driving transistor. After the completion of data writing, keep the other states of the circuit unchanged and turn on the light-emitting control tube in advance. The information at both ends of the storage capacitor will change ΔV and finally form the reference voltage during the light-emitting process. Among them, ΔV has nothing to do with the threshold voltage, but is only related to the mobility of the driving transistor so as to compensate for the mobility change. During the light-emitting process, the reference voltage remains unchanged, so that the driving current flowing through the light-emitting device has nothing to do with the threshold voltage of the driving transistor and the light-emitting element, and the influence of the mobility change of the driving transistor on the brightness uniformity of the pixel circuit is improved by using the control signal overlap Influence, it solves the problem of display unevenness caused by the variation of threshold voltage and mobility of the display panel.
以上应用了具体各例对本申请进行阐述，只是用于帮助理解本申请，并不用以限制本申请。具体实施例中晶体管均采用N型TFT，但是，根据本申请的思想，并在不脱离本申请的范围内，也可以设计出其他结合P型或者N、P型TFT的像素电路。而且，对于本申请所属技术领域的技术人员，在不脱离本发明构思的前提下，还可以做出若干简单推演、变形或替换。The above uses specific examples to illustrate the present application, which is only used to help the understanding of the present application, and is not intended to limit the present application. The transistors in the specific embodiments all use N-type TFTs. However, according to the idea of the present application and without departing from the scope of the present application, other pixel circuits combined with P-type or N and P-type TFTs can also be designed. Moreover, for those skilled in the technical field to which the present application belongs, some simple deduction, deformation or substitution can also be made without departing from the concept of the present invention.
| Application Number | Priority Date | Filing Date | Title |
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| CN201510890674.8ACN105489167B (en) | 2015-12-07 | 2015-12-07 | Display device and its pixel circuit and driving method |
| Application Number | Priority Date | Filing Date | Title |
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| CN201510890674.8ACN105489167B (en) | 2015-12-07 | 2015-12-07 | Display device and its pixel circuit and driving method |
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| CN201510890674.8AActiveCN105489167B (en) | 2015-12-07 | 2015-12-07 | Display device and its pixel circuit and driving method |
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