技术领域technical field
本发明涉及显示技术领域，具体涉及一种像素结构及其制作方法、阵列基板及显示装置。The present invention relates to the field of display technology, in particular to a pixel structure and a manufacturing method thereof, an array substrate and a display device.
背景技术Background technique
液晶显示装置是目前使用最广泛的一种平板显示装置，可为各种电子设备如移动电话、个人数字助理(PDA)、数字相机以及计算机等提供具有高分辨率彩色屏幕。其中FFS(FringeFieldSwitching，边缘场开关技术)液晶显示装置以其观看视角广以及开口率高等特点受到广大用户的喜爱。目前普遍采用的FFS液晶显示装置，通常包括彩膜基板、阵列基板以及设置在彩膜基板和阵列基板之间的液晶层。其中在阵列基板上设置有多条数据线、栅线以及由多条数据线栅线交叉限定的多个像素结构。The liquid crystal display device is currently the most widely used flat panel display device, which can provide high-resolution color screens for various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, and computers. Among them, the FFS (Fringe Field Switching, fringe field switching technology) liquid crystal display device is favored by the majority of users for its wide viewing angle and high aperture ratio. The FFS liquid crystal display device commonly used at present generally includes a color filter substrate, an array substrate, and a liquid crystal layer arranged between the color filter substrate and the array substrate. Wherein the array substrate is provided with a plurality of data lines, gate lines and a plurality of pixel structures defined by intersections of the plurality of data lines and gate lines.
如图1所示，传统FFS显示技术的像素结构包括衬底基板3＇，在衬底基板3＇上设置有薄膜晶体管4＇、第一透明电极层1＇、第二透明电极层2＇。其中，第一透明电极层1＇为面状结构电极，第二透明电极层2＇包括若干个条状电极，第一透明电极层1＇与第二透明电极层2＇之间存在重叠区域。具体的排布结构如图2所示。由图1以及图2可以看出传统的像素结构第一透明电极层1＇与第二透明电极层2＇的重叠区域较大，因此第一透明电极层1＇与第二透明电极层2＇之间形成的存储电容(Cst)较大。较大的存储电容延长了像素的充电时间，使像素单元易出现充电不足的现象，导致显示面板亮度下降，严重影响了显示质量。As shown in FIG. 1 , the pixel structure of the traditional FFS display technology includes a base substrate 3 ′, on which a thin film transistor 4 ′, a first transparent electrode layer 1 ′, and a second transparent electrode layer 2 ′ are arranged. Wherein, the first transparent electrode layer 1' is a planar structure electrode, the second transparent electrode layer 2' includes several strip electrodes, and there is an overlapping area between the first transparent electrode layer 1' and the second transparent electrode layer 2'. The specific arrangement structure is shown in Fig. 2 . It can be seen from Figure 1 and Figure 2 that the traditional pixel structure has a relatively large overlapping area between the first transparent electrode layer 1' and the second transparent electrode layer 2', so the first transparent electrode layer 1' and the second transparent electrode layer 2' The storage capacitance (Cst) formed between them is relatively large. A large storage capacitor prolongs the charging time of the pixel, making the pixel unit prone to insufficient charging, resulting in a decrease in the brightness of the display panel, which seriously affects the display quality.
发明内容Contents of the invention
本发明要解决的技术问题是：解决如何降低现有的像素结构中第一透明电极层以及第二透明电极层之间的存储电容的问题。The technical problem to be solved by the present invention is: how to reduce the storage capacitance between the first transparent electrode layer and the second transparent electrode layer in the existing pixel structure.
为实现上述的发明目的，本发明提供了一种像素结构及其制作方法、阵列基板及显示装置。In order to achieve the above object of the invention, the present invention provides a pixel structure and a manufacturing method thereof, an array substrate and a display device.
依据本发明的第一方面，提供了一种像素结构：包括衬底基板以及设置在所述衬底基板上的第一透明电极层和第二透明电极层，所述第二透明电极层包括多个条状电极，其特征在于，所述第一透明电极层包括至少一个狭缝，且每一个所述狭缝至少部分位于所述条状电极在所述衬底基板的投影内。According to the first aspect of the present invention, a pixel structure is provided: comprising a base substrate and a first transparent electrode layer and a second transparent electrode layer disposed on the base substrate, the second transparent electrode layer comprising multiple A strip-shaped electrode, wherein the first transparent electrode layer includes at least one slit, and each of the slits is at least partially located within the projection of the strip-shaped electrode on the base substrate.
优选地，每一个所述狭缝全部位于所述条状电极在所述衬底基板的投影内。Preferably, each of the slits is located within the projection of the strip electrode on the base substrate.
优选地，对于每一个所述狭缝，其宽度与其相对的条状电极的宽度之比为10％～100％。Preferably, for each of the slits, the ratio of its width to the width of the strip electrode opposite it is 10%-100%.
优选地，所述第一透明电极层中所述狭缝的数量与所述第二透明电极层中所述条状电极的数量之比为1:50～1:2。Preferably, the ratio of the number of the slits in the first transparent electrode layer to the number of the strip electrodes in the second transparent electrode layer is 1:50˜1:2.
依据本发明的第二方面，提供了一种阵列基板，包括上述所述的像素结构。According to a second aspect of the present invention, an array substrate is provided, including the above-mentioned pixel structure.
依据本发明的第三方面，提供了一种显示装置，包括上述所述的阵列基板。According to a third aspect of the present invention, a display device is provided, including the above-mentioned array substrate.
依据本发明的第四方面，提供了一种像素结构的制作方法，包括：According to a fourth aspect of the present invention, a method for manufacturing a pixel structure is provided, including:
在衬底基板上形成第一透明电极层和第二透明电极层，其中，所述第二透明电极层包括多个条状电极，所述第一透明电极层包括至少一个狭缝，且每一个所述狭缝至少部分位于所述条状电极在所述衬底基板的投影内。A first transparent electrode layer and a second transparent electrode layer are formed on the base substrate, wherein the second transparent electrode layer includes a plurality of strip electrodes, the first transparent electrode layer includes at least one slit, and each The slit is at least partially located within the projection of the strip electrode on the base substrate.
优选地，每一个所述狭缝全部位于所述条状电极在所述衬底基板的投影内。Preferably, each of the slits is located within the projection of the strip electrode on the base substrate.
优选地，对于每一个所述狭缝，其宽度与其相对的条状电极的宽度之比为10％～100％。Preferably, for each of the slits, the ratio of its width to the width of the strip electrode opposite it is 10%-100%.
优选地，所述第一透明电极层中所述狭缝的数量与所述第二透明电极层中所述条状电极的数量之比为1:50～1:2。Preferably, the ratio of the number of the slits in the first transparent electrode layer to the number of the strip electrodes in the second transparent electrode layer is 1:50˜1:2.
本发明提供的该像素结构，通过在第一透明电极层上形成狭缝，并使狭缝至少部分位于条形电极在衬底基板上的投影内，有效减小了第一透明电极层与第二透明电极层的重叠区域，从而降低了其间形成的存储电容，提高像素的充电效率以及显示装置的显示质量。In the pixel structure provided by the present invention, by forming slits on the first transparent electrode layer and making the slits at least partly located in the projection of the strip electrodes on the base substrate, the distance between the first transparent electrode layer and the second transparent electrode layer is effectively reduced. The overlapping area of the two transparent electrode layers reduces the storage capacitance formed therebetween, improves the charging efficiency of the pixel and the display quality of the display device.
附图说明Description of drawings
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same components. In the attached picture:
图1是现有技术的像素结构截面示意图；FIG. 1 is a schematic cross-sectional view of a pixel structure in the prior art;
图2是现有技术的像素结构俯视图；FIG. 2 is a top view of a pixel structure in the prior art;
图3是本发明提供的像素结构截面示意图；3 is a schematic cross-sectional view of a pixel structure provided by the present invention;
图4是本发明提供的一种像素结构俯视图；Fig. 4 is a top view of a pixel structure provided by the present invention;
图5是本发明提供的另一种像素结构俯视图；Fig. 5 is a top view of another pixel structure provided by the present invention;
图6是本发明提供的不同狭缝设置比率对应的电压-透过率曲线示意图；Fig. 6 is a schematic diagram of voltage-transmittance curves corresponding to different slit setting ratios provided by the present invention;
图7是本发明提供的不同狭缝设置比率对应的存储电容比率示意图。FIG. 7 is a schematic diagram of storage capacitor ratios corresponding to different slit setting ratios provided by the present invention.
具体实施方式detailed description
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
本发明提供了一种像素结构，包括衬底基板以及设置在衬底基板上的第一透明电极层和第二透明电极层，第二透明电极层包括多个条状电极，第一透明电极层包括至少一个狭缝，且每一个狭缝至少部分位于条状电极在衬底基板的投影内。The present invention provides a pixel structure, including a base substrate and a first transparent electrode layer and a second transparent electrode layer arranged on the base substrate, the second transparent electrode layer includes a plurality of strip electrodes, the first transparent electrode layer At least one slit is included, and each slit is at least partially located within the projection of the strip electrode on the base substrate.
本发明提供的像素结构通过在第一透明电极层上形成狭缝，并使狭缝至少部分位于条形电极在衬底基板上的投影内，有效减小了第一透明电极层与第二透明电极层的重叠区域，从而降低了其间形成的存储电容，提高像素的充电效率以及显示装置的显示质量。In the pixel structure provided by the present invention, by forming slits on the first transparent electrode layer and making the slits at least partly located within the projection of the strip electrodes on the base substrate, the gap between the first transparent electrode layer and the second transparent electrode layer is effectively reduced. The overlapping area of the electrode layers reduces the storage capacitance formed therebetween, improves the charging efficiency of the pixel and the display quality of the display device.
参见图3，图3为本发明实施方式提供的像素结构，包括衬底基板3，衬底基板3上设置有薄膜晶体管4、第一透明电极层1、第二透明电极层2，以及位于第一透明电极层1与第二透明电极层2之间的钝化层5。其中，薄膜晶体管4包括栅极41、栅极绝缘层42、有源层43、源极44和漏极45，第一透明电极层1为面状电极，第二透明电极层2包括多个条状电极6，在第一透明电极层1和第二透明电极层2之间存在有重叠区域。为了减小重叠区域从而降低其间形成的存储电容，在第一透明电极层1上还设置有至少一个狭缝7，且狭缝7至少部分位于条状电极6在衬底基板3的投影内。狭缝7的设置减小了第一透明电极层1和第二透明电极层2之间的重叠区域，从而降低了第一透明电极层1和第二透明电极层2之间形成的存储电容。Referring to Fig. 3, Fig. 3 is a pixel structure provided by an embodiment of the present invention, including a base substrate 3, on which a thin film transistor 4, a first transparent electrode layer 1, a second transparent electrode layer 2, and A passivation layer 5 between the first transparent electrode layer 1 and the second transparent electrode layer 2 . Wherein, the thin film transistor 4 includes a gate 41, a gate insulating layer 42, an active layer 43, a source 44 and a drain 45, the first transparent electrode layer 1 is a planar electrode, and the second transparent electrode layer 2 includes a plurality of strips There is an overlapping area between the first transparent electrode layer 1 and the second transparent electrode layer 2 . In order to reduce the overlapping area and thereby reduce the storage capacitance formed therebetween, at least one slit 7 is further provided on the first transparent electrode layer 1 , and the slit 7 is at least partially located within the projection of the strip electrodes 6 on the base substrate 3 . The setting of the slit 7 reduces the overlapping area between the first transparent electrode layer 1 and the second transparent electrode layer 2 , thereby reducing the storage capacitance formed between the first transparent electrode layer 1 and the second transparent electrode layer 2 .
其中，如图3所示，第一透明电极层1上形成的狭缝7可以全部位于条状电极6在衬底基板3的投影内。对于每一个狭缝7，其宽度与其上方正对的条状电极6的宽度之比可以在10％～100％之内，例如，可以如图4所示，狭缝7的宽度小于其上对应的条状电极6的宽度，还可以如图5所示，狭缝7的宽度与其上对应的条状电极6的宽度相同，狭缝7与条状电极6之间的宽度之比可以根据实际情况做相应的调整。Wherein, as shown in FIG. 3 , the slits 7 formed on the first transparent electrode layer 1 may all be located within the projection of the strip electrodes 6 on the base substrate 3 . For each slit 7, the ratio of its width to the width of the strip electrode 6 facing above it can be within 10% to 100%. For example, as shown in Figure 4, the width of the slit 7 is smaller than the corresponding one The width of the strip electrode 6 can also be shown in Figure 5, the width of the slit 7 is the same as the width of the corresponding strip electrode 6, and the ratio of the width between the slit 7 and the strip electrode 6 can be determined according to the actual situation. Adjust accordingly.
为了进一步降低存储电容的大小，优选地，第一透明电极层1上可以设置多个狭缝7，例如，可以使第一透明电极层中狭缝的数量与第二透明电极层中条状电极的数量之比为1:50～1:2，例如可以为1:25等。In order to further reduce the size of the storage capacitor, preferably, a plurality of slits 7 can be set on the first transparent electrode layer 1, for example, the number of slits in the first transparent electrode layer can be compared with that of the strip electrodes in the second transparent electrode layer. The ratio of the quantity is 1:50˜1:2, for example, it can be 1:25 or the like.
对于像素结构来说，存储电容只是影响显示效果的一个因素，还有一个较为重要的因素就是光透过率。本发明提供的像素结构可以在保证不影响光透过率的前提下有效降低存储电容。例如，当第二透明电极层中条状电极6的宽度为2.5μm，相邻的两个条状电极6之间的间距为5.5μm时，第一透明电极层中狭缝的数量与第二透明电极层中条状电极的数量之比为1:3(即在第一透明电极层上每对应3个条状电极的位置设置一个狭缝)，对狭缝与条形电极的宽度比为67％的结构和狭缝与条形电极的宽度比为100％的结构分别进行测试，具体参见图6，当第一透明电极层中狭缝与第二透明电极层中条状电极的宽度比为67％或100％时，其在不同电压下的光透光率与现有的像素结构基本保持一致，而本发明提供的像素结构通过在第一透明电极层上设置狭缝可以有效的降低存储电容，如图7所示，当狭缝与条形电极宽度比为67％时，存储电容相比于现有的像素结构下降了2.7％；当狭缝与条形电极宽度比为100％时，存储电容下降了11.6％。存储电容的降低可以有效提高像素的充电效率，提高显示质量。For the pixel structure, the storage capacitor is only one factor affecting the display effect, and another important factor is the light transmittance. The pixel structure provided by the present invention can effectively reduce the storage capacitance without affecting the light transmittance. For example, when the width of the strip electrodes 6 in the second transparent electrode layer is 2.5 μm, and the distance between two adjacent strip electrodes 6 is 5.5 μm, the number of slits in the first transparent electrode layer is the same as that of the second The ratio of the number of strip electrodes in the transparent electrode layer is 1:3 (that is, a slit is arranged at a position corresponding to 3 strip electrodes on the first transparent electrode layer), and the width ratio of the slit to the strip electrodes is 67% of the structure and the structure with a width ratio of slits and strip electrodes of 100% were tested respectively. See Figure 6 for details. When the width ratio of the slits in the first transparent electrode layer to the width ratio of the strip electrodes in the second transparent electrode layer When it is 67% or 100%, its light transmittance under different voltages is basically consistent with the existing pixel structure, and the pixel structure provided by the present invention can effectively reduce the Storage capacitance, as shown in Figure 7, when the ratio of the width of the slit to the strip electrode is 67%, the storage capacitance is reduced by 2.7% compared with the existing pixel structure; when the ratio of the width of the slit to the strip electrode is 100% , the storage capacitance dropped by 11.6%. The reduction of the storage capacitance can effectively improve the charging efficiency of the pixel and improve the display quality.
需要说明的是，本发明实施方式提供的像素结构中，第一透明电极层可以为公共电极，也可以为像素电极(即与薄膜晶体管的漏极相连)，当第一透明电极层为公共电极时，第二透明电极层为像素电极当第一透明电极层为像素电极时，第二透明电极层为公共电极，此外，第一透明电极层的材料与第二透明电极层的材料可以为ITO(氧化铟锡)，也可以为其他透明导电材料，本发明对此不做具体限定。It should be noted that, in the pixel structure provided by the embodiment of the present invention, the first transparent electrode layer can be a common electrode, or a pixel electrode (that is, connected to the drain of the thin film transistor). When the first transparent electrode layer is a common electrode When the second transparent electrode layer is a pixel electrode, when the first transparent electrode layer is a pixel electrode, the second transparent electrode layer is a common electrode. In addition, the material of the first transparent electrode layer and the material of the second transparent electrode layer can be ITO (indium tin oxide) may also be other transparent conductive materials, which are not specifically limited in the present invention.
综上所述，本发明实施方式提供了一种像素结构，该像素结构通过在第一透明电极层上形成狭缝，并使狭缝至少部分位于条形电极在衬底基板上投影内，有效减小了第一透明电极层与第二透明电极层的重叠区域，从而降低了其间形成的存储电容，提高像素的充电效率以及显示装置的显示质量。To sum up, the embodiment of the present invention provides a pixel structure, which effectively The overlapping area of the first transparent electrode layer and the second transparent electrode layer is reduced, thereby reducing the storage capacitance formed therebetween, improving the charging efficiency of the pixel and the display quality of the display device.
本发明实施方式还提供了一种阵列基板，包括上述的像素结构。The embodiment of the present invention also provides an array substrate, including the above-mentioned pixel structure.
此外，本发明实施方式还提供了一种显示装置，该显示装置包括上述的阵列基板。其中，该显示装置可以为FFS模式的显示装置，其中，本发明实施方式提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。In addition, an embodiment of the present invention also provides a display device, which includes the above-mentioned array substrate. Wherein, the display device can be a display device in FFS mode, wherein, the display device provided by the embodiment of the present invention can be any product with a display function such as a notebook computer display screen, a liquid crystal display, a liquid crystal TV, a digital photo frame, a mobile phone, a tablet computer, etc. or parts.
进一步地，本发明实施方式提供一种像素结构的制作方法，该方法包括：Further, an embodiment of the present invention provides a method for manufacturing a pixel structure, the method comprising:
在衬底基板上形成第一透明电极层和第二透明电极层，其中，所述第二透明电极层包括多个条状电极，所述第一透明电极层包括至少一个狭缝，且每一个所述狭缝至少部分位于所述条状电极在所述衬底基板的投影内。A first transparent electrode layer and a second transparent electrode layer are formed on the base substrate, wherein the second transparent electrode layer includes a plurality of strip electrodes, the first transparent electrode layer includes at least one slit, and each The slit is at least partially located within the projection of the strip electrode on the base substrate.
优选地，在第一透明电极层上形成狭缝时，可以使每一个狭缝全部位于条状电极在衬底基板的投影内。同时，对于每一个所述狭缝，其宽度与其相对的条状电极的宽度之比可以为10％～100％。，例如可以为67％或100％。为了进一步降低第一透明电极层与第二透明电极层形成的存储电容，在第一透明电极层上可以形成多个狭缝，并使所述第一透明电极层中所述狭缝的数量与所述第二透明电极层中所述条状电极的数量之比为1:50～1:2。Preferably, when the slits are formed on the first transparent electrode layer, each slit can be completely located within the projection of the strip electrodes on the base substrate. At the same time, for each of the slits, the ratio of its width to the width of the strip electrode opposite to it may be 10%-100%. , such as 67% or 100%. In order to further reduce the storage capacitance formed by the first transparent electrode layer and the second transparent electrode layer, a plurality of slits can be formed on the first transparent electrode layer, and the number of the slits in the first transparent electrode layer is equal to The ratio of the number of the strip electrodes in the second transparent electrode layer is 1:50˜1:2.
本发明提供的像素电极的制作方法，通过在第一透明电极层上形成狭缝并使该狭缝位于条形电极在衬底基板的投影内，有效地减小了第一透明电极层与第二透明电极层重叠区域的面积，降低了其间形成的存储电容，提高显示效果。The manufacturing method of the pixel electrode provided by the present invention effectively reduces the distance between the first transparent electrode layer and the second transparent electrode layer by forming a slit on the first transparent electrode layer and making the slit located in the projection of the strip electrode on the base substrate. The area of the overlapping region of the two transparent electrode layers reduces the storage capacitance formed therebetween and improves the display effect.
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610064421.XACN105487311A (en) | 2016-01-29 | 2016-01-29 | Pixel structure and making method thereof, array substrate and display device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610064421.XACN105487311A (en) | 2016-01-29 | 2016-01-29 | Pixel structure and making method thereof, array substrate and display device |
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| CN105487311Atrue CN105487311A (en) | 2016-04-13 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201610064421.XAPendingCN105487311A (en) | 2016-01-29 | 2016-01-29 | Pixel structure and making method thereof, array substrate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108508661A (en)* | 2017-02-24 | 2018-09-07 | 三菱电机株式会社 | Liquid crystal display panel and liquid crystal display device |
| CN110441965A (en)* | 2019-08-23 | 2019-11-12 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009181091A (en)* | 2008-02-01 | 2009-08-13 | Epson Imaging Devices Corp | Liquid crystal display |
| CN102830557A (en)* | 2012-09-05 | 2012-12-19 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN203405655U (en)* | 2013-08-30 | 2014-01-22 | 京东方科技集团股份有限公司 | A kind of array substrate and display device |
| CN103676353A (en)* | 2013-12-04 | 2014-03-26 | 京东方科技集团股份有限公司 | Pixel structure, array substrate and display device |
| US20150014694A1 (en)* | 2013-07-02 | 2015-01-15 | Boe Technology Group Co., Ltd. | Pixel Structure, Array Substrate and Display Device |
| CN105137681A (en)* | 2015-10-22 | 2015-12-09 | 重庆京东方光电科技有限公司 | Array substrate as well as manufacturing method and display device thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009181091A (en)* | 2008-02-01 | 2009-08-13 | Epson Imaging Devices Corp | Liquid crystal display |
| CN102830557A (en)* | 2012-09-05 | 2012-12-19 | 京东方科技集团股份有限公司 | Array substrate and display device |
| US20150014694A1 (en)* | 2013-07-02 | 2015-01-15 | Boe Technology Group Co., Ltd. | Pixel Structure, Array Substrate and Display Device |
| CN203405655U (en)* | 2013-08-30 | 2014-01-22 | 京东方科技集团股份有限公司 | A kind of array substrate and display device |
| CN103676353A (en)* | 2013-12-04 | 2014-03-26 | 京东方科技集团股份有限公司 | Pixel structure, array substrate and display device |
| CN105137681A (en)* | 2015-10-22 | 2015-12-09 | 重庆京东方光电科技有限公司 | Array substrate as well as manufacturing method and display device thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108508661A (en)* | 2017-02-24 | 2018-09-07 | 三菱电机株式会社 | Liquid crystal display panel and liquid crystal display device |
| CN108508661B (en)* | 2017-02-24 | 2021-11-16 | 三菱电机株式会社 | Liquid crystal display panel and liquid crystal display device |
| CN110441965A (en)* | 2019-08-23 | 2019-11-12 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and display device |
| Publication | Publication Date | Title |
|---|---|---|
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| RJ01 | Rejection of invention patent application after publication | Application publication date:20160413 |