技术领域technical field
本发明涉及显示技术领域，具体涉及一种栅极驱动器以及应用该栅极驱动器的显示面板。The present invention relates to the field of display technology, in particular to a gate driver and a display panel using the gate driver.
背景技术Background technique
随着光学技术与半导体技术的发展，液晶显示面板(LiquidCrystalDisplay，LCD)以及有机发光二极管显示面板(OrganicLightEmittingDiode，OLED)等平板显示面板由于具有形体更轻薄、成本和能耗更低、反应速度更快、色纯度和亮度更优以及对比度更高等特点，已经被广泛应用于各类电子产品上。但是，现有技术中的显示产品仍存在有待改进之处。例如：With the development of optical technology and semiconductor technology, flat display panels such as liquid crystal display panels (Liquid Crystal Display, LCD) and organic light emitting diode display panels (Organic Light Emitting Diode, OLED) have thinner and thinner shapes, lower cost and energy consumption, and faster response speeds. , better color purity and brightness, and higher contrast, have been widely used in various electronic products. However, the display products in the prior art still have room for improvement. For example:
显示面板主要通过像素矩阵实现显示，通常而言，各行像素均耦接至对应的扫描栅线。在显示面板工作过程中，通过栅极驱动器将输入的时钟信号等信号经过移位寄存器单元转换成控制像素开启/关断的栅极扫描信号，例如，栅极开启信号和栅极关断信号；将栅极扫描信号顺次施加到显示面板的各行像素的扫描栅线，即可对各行像素进行选通。The display panel mainly implements display through a pixel matrix, and generally speaking, each row of pixels is coupled to a corresponding scanning gate line. During the working process of the display panel, the gate driver converts the input clock signal and other signals through the shift register unit into gate scanning signals that control the on/off of pixels, for example, gate turn-on signals and gate turn-off signals; Each row of pixels can be gated by sequentially applying the gate scanning signal to the scanning gate lines of each row of pixels of the display panel.
如图1中所示，为一种栅极驱动器的结构示意图。该栅极驱动器包括级联的5级移位寄存器单元SR1～SR5，移位寄存器单元SR1的第一输入端VIN1接收起始信号STV，移位寄存器单元SR2～SR5的第一输入端VIN1接收前一级移位寄存器单元的输出信号，移位寄存器单元SR1～SR4的第二输入端VIN2接收后一级移位寄存器单元的输出信号作为复位信号；此外，各移位寄存器单元还接收第一时钟信号CK1以及第二时钟信号CKB1。每一移位寄存器单元根据接收的信号在其输出端VOUT提供一输出信号，因此图1中的栅极驱动器可以提供5行栅极驱动信号。As shown in FIG. 1 , it is a schematic structural diagram of a gate driver. The gate driver includes cascaded 5-stage shift register units SR1-SR5, the first input terminal VIN1 of the shift register unit SR1 receives the start signal STV, and the first input terminal VIN1 of the shift register units SR2-SR5 receives the start signal STV The output signal of the shift register unit of the first stage, the second input terminal VIN2 of the shift register unit SR1～SR4 receives the output signal of the shift register unit of the next stage as the reset signal; in addition, each shift register unit also receives the first clock The signal CK1 and the second clock signal CKB1. Each shift register unit provides an output signal at its output terminal VOUT according to the received signal, so the gate driver in FIG. 1 can provide 5 rows of gate driving signals.
随着平板显示技术的发展，高分辨率以及窄边框产品得到了越来越多的关注，上述栅极驱动器中数量众多的移位寄存器单元会占据很大的版图面积，不利于增加有效显示面积以及窄边框设计。With the development of flat panel display technology, more and more attention has been paid to high-resolution and narrow-frame products. The large number of shift register units in the above-mentioned gate driver will occupy a large layout area, which is not conducive to increasing the effective display area. And narrow bezel design.
此外，由于栅极驱动器最末级的移位寄存器单元，即移位寄存器单元SR5的第二输入端VIN2没有作为复位信号输入信号，因此其输出端可能会输出错误的信号。参考图2中所示，为栅极驱动器最末级(例如第5级)的移位寄存器单元的输出信号的模拟波形，可以明显看出相比前一级(例如第4级)会有多次输出。In addition, because the shift register unit at the last stage of the gate driver, that is, the second input terminal VIN2 of the shift register unit SR5 does not receive a signal as a reset signal, its output terminal may output an erroneous signal. Referring to Figure 2, which is the simulated waveform of the output signal of the shift register unit at the last stage (e.g., stage 5) of the gate driver, it can be clearly seen that there will be more output.
参考图3中所示，一种解决方案是在栅极驱动器最末级的移位寄存器单元之后设置一虚拟(Dummy)移位寄存器单元DSR1，利用虚拟移位寄存器单元DSR1的输出信号DS1向最末级的移位寄存器单元SR5提供复位信号；同时，由于在反向扫描时，原本第1级的移位寄存器单元SR1将成为最末级的移位寄存器单元，因此，在栅极驱动器第1级的移位寄存器单元SR1之前同样需要设置一虚拟移位寄存器单元DSR2。这样无疑进一步增加了栅极驱动器的面积；而且虚拟移位寄存器单元的输出信号DS1以及DS2无法作为有效栅极扫描信号输入至显示区域，即为无效栅极扫描信号，因此还需要为虚拟移位寄存器单元的输出信号DS1以及DS2额外设置负载。Referring to Fig. 3, a solution is to set a dummy (Dummy) shift register unit DSR1 after the shift register unit of the last stage of the gate driver, and use the output signal DS1 of the dummy shift register unit DSR1 to the last The last-stage shift register unit SR5 provides a reset signal; at the same time, since the original first-stage shift register unit SR1 will become the last-stage shift register unit during reverse scanning, therefore, in the first stage of the gate driver A dummy shift register unit DSR2 also needs to be set before the shift register unit SR1 of the first stage. This will undoubtedly further increase the area of the gate driver; and the output signals DS1 and DS2 of the virtual shift register unit cannot be input to the display area as valid gate scanning signals, that is, invalid gate scanning signals, so it is necessary to provide a virtual shift The output signals DS1 and DS2 of the register unit additionally set the load.
需要说明的是，在上述背景技术部分发明的信息仅用于加强对本发明的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.
发明内容Contents of the invention
本发明的目的在于提供一种栅极驱动器以及应用该栅极驱动器的显示面板，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或多个问题。An object of the present invention is to provide a gate driver and a display panel using the gate driver to overcome one or more problems caused by limitations and defects of related technologies at least to a certain extent.
本发明的其他特性和优点将通过下面的详细描述变得清晰，或部分地通过本发明的实践而习得。Other features and advantages of the invention will become apparent from the following detailed description, or in part, be learned by practice of the invention.
本发明实施例的一方面提供一种栅极驱动器，包括：An aspect of the embodiments of the present invention provides a gate driver, including:
至少一移位寄存器组，每一所述移位寄存器组包括级联的N级移位寄存器单元，其中，N为正整数，且N≥3；At least one shift register group, each of which includes cascaded N-stage shift register units, where N is a positive integer, and N≥3;
所述移位寄存器单元接收第一输入信号、第二输入信号以及时钟信号并根据所述第一输入信号、第二输入信号以及时钟信号提供一输出信号；The shift register unit receives a first input signal, a second input signal and a clock signal and provides an output signal according to the first input signal, the second input signal and the clock signal;
其中，第m级移位寄存器单元接收的所述第一输入信号为第m-1级移位寄存器单元的输出信号，第m级移位寄存器单元接收的所述第二输入信号为所述第m+1级移位寄存器单元的输出信号，其中，m为正整数，且1<m<N；Wherein, the first input signal received by the shift register unit of the mth stage is the output signal of the shift register unit of the m-1th stage, and the second input signal received by the shift register unit of the mth stage is the output signal of the shift register unit of the mth stage The output signal of the m+1 stage shift register unit, where m is a positive integer, and 1<m<N;
其中，第1级移位寄存器单元接收的所述第一输入信号为一第一起始信号，至少第1级至第N-1级所述移位寄存器单元的输出信号均用作有效栅极扫描信号，并且利用所述第一起始信号提供一所述有效栅极扫描信号。Wherein, the first input signal received by the shift register unit of the first stage is a first start signal, and at least the output signals of the shift register units of the first stage to the N-1th stage are used as effective gate scanning signal, and using the first start signal to provide a valid gate scan signal.
本发明实施例的另一方面提供一种栅极驱动器，包括：Another aspect of the embodiments of the present invention provides a gate driver, including:
至少一移位寄存器组，每一所述移位寄存器组包括级联的N级移位寄存器单元，其中，N为正整数，且N≥3；At least one shift register group, each of which includes cascaded N-stage shift register units, where N is a positive integer, and N≥3;
所述移位寄存器单元接收输入信号以及时钟信号并根据所述输入信号以及时钟信号提供一输出信号；The shift register unit receives an input signal and a clock signal and provides an output signal according to the input signal and the clock signal;
其中，第m级移位寄存器单元接收的所述输入信号为第m-1级移位寄存器单元的所述输出信号，其中，m为正整数，且1<m≤N；Wherein, the input signal received by the shift register unit of the mth stage is the output signal of the shift register unit of the m-1th stage, wherein, m is a positive integer, and 1<m≤N;
其中，第1级移位寄存器单元接收的所述输入信号为一起始信号，所有所述移位寄存器单元的输出信号均用作有效栅极扫描信号，并且利用所述起始信号提供一所述有效栅极扫描信号。Wherein, the input signal received by the shift register unit of the first stage is a start signal, and the output signals of all the shift register units are used as effective gate scanning signals, and the start signal is used to provide a start signal. Active gate scan signal.
本发明实施例的再一方面提供一种显示面板，包括上述任意一种栅极驱动器。Still another aspect of the embodiments of the present invention provides a display panel, including any one of the above-mentioned gate drivers.
综上所述，本发明的示例实施方式中，通过利用起始信号提供有效栅极扫描信号，可以有效减少移位寄存器单元的数量，进而可以使得栅极驱动器的版图面积减小，为实现更高分辨率和更窄边框的显示面板提供了技术支持；同时，由于节省了移位寄存器单元的数量，从而可以简化制备工艺，压缩制备成本。To sum up, in the exemplary embodiment of the present invention, by using the start signal to provide an effective gate scanning signal, the number of shift register units can be effectively reduced, and the layout area of the gate driver can be reduced. The display panel with high resolution and narrower frame provides technical support; at the same time, because the number of shift register units is saved, the manufacturing process can be simplified and the manufacturing cost can be reduced.
附图说明Description of drawings
通过参照附图详细描述其示例性实施例，本发明的上述和其它特征及优点将变得更加明显。The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings.
图1是现有技术中一种栅极驱动器的结构示意图；FIG. 1 is a schematic structural diagram of a gate driver in the prior art;
图2是图1中栅极驱动器部分输出信号的波形图；FIG. 2 is a waveform diagram of part of the output signal of the gate driver in FIG. 1;
图3是现有技术中另一种栅极驱动器的结构示意图；FIG. 3 is a schematic structural diagram of another gate driver in the prior art;
图4是本发明实施例提供的一种栅极驱动器的结构图；FIG. 4 is a structural diagram of a gate driver provided by an embodiment of the present invention;
图5是图2中栅极驱动器输出信号的波形示意图；FIG. 5 is a schematic waveform diagram of the output signal of the gate driver in FIG. 2;
图6是本发明实施例提供的又一种栅极驱动器的结构示意图；FIG. 6 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention;
图7是本发明实施例提供的又一种栅极驱动器的结构示意图；FIG. 7 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention;
图8是本发明实施例提供的又一种栅极驱动器的结构示意图；FIG. 8 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention;
图9是本发明实施例提供的又一种栅极驱动器的结构示意图；FIG. 9 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention;
图10是本发明实施例提供的又一种栅极驱动器的结构示意图；FIG. 10 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention;
图11是本发明实施例提供的又一种栅极驱动器的结构示意图；FIG. 11 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention;
图12是本发明实施例提供的又一种栅极驱动器的结构示意图。FIG. 12 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention.
具体实施方式detailed description
现在将参考附图更全面地描述示例性实施例。然而，示例性实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本发明将全面和完整，并将示例性实施例的构思全面地传达给本领域的技术人员。在图中，为了清晰，夸大、变形或简化了形状尺寸。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。Exemplary embodiments will now be described more fully with reference to the accompanying drawings. Exemplary embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the exemplary embodiments. communicated to those skilled in the art. In the drawings, shapes and dimensions are exaggerated, distorted or simplified for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
此外，所描述的特征、结构或步骤可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本发明的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本发明的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、步骤、结构等。Furthermore, the described features, structures, or steps may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate that the technical solutions of the present invention may be practiced without one or more of the specific details, or that other methods, steps, structures, etc. may be employed.
本示例实施方式中首先提供了一种栅极驱动器。栅极驱动器包括至少一个移位寄存器组。参考图4，图4是本发明实施例提供的一种栅极驱动器的结构示意图，其中，栅极驱动器包括一个移位寄存器组，移位寄存器组包括级联的N级移位寄存器单元，其中，N为正整数，且N≥3；图4中以N等于5为例进行说明，即移位寄存器组包括级联的第1级移位寄存器单元SR1至第5级移位寄存器单元SR5；但本领域技术人员容易理解的是，N实际上可以为任意大于2的正整数。In this example embodiment, a gate driver is firstly provided. The gate driver includes at least one shift register bank. Referring to FIG. 4, FIG. 4 is a schematic structural diagram of a gate driver provided by an embodiment of the present invention, wherein the gate driver includes a shift register group, and the shift register group includes cascaded N-stage shift register units, wherein , N is a positive integer, and N≥3; Figure 4 takes N equal to 5 as an example for illustration, that is, the shift register group includes cascaded first-stage shift register unit SR1 to fifth-stage shift register unit SR5; However, those skilled in the art can easily understand that N can actually be any positive integer greater than 2.
每一上述移位寄存器单元均包括第一输入端VIN1、第二输入端VIN2、时钟信号端CK1、时钟信号端CKB1以及输出端VOUT，其中，每一移位寄存器单元的第一输入端VIN1可以接收一第一输入信号，第二输入端VIN2可以接收一第二输入信号，时钟信号端CK1以及时钟信号端CKB1可以用于接收第一时钟信号CK1以及第二时钟信号CKB1，并且，每一移位寄存器单元根据接收的第一输入信号、第二输入信号以及时钟信号在其输出端VOUT提供一输出信号。本示例实施方式中，移位寄存器单元可以由多个开关晶体管以及电容等元件构成，移位寄存器单元可以为非晶硅(AlphaSilica)半导体移位寄存器单元，即其中的开关晶体管为非晶硅型薄膜晶体管(a-SiTFT)；也可以是氧化物(Oxide)半导体移位寄存器单元，即其中的开关晶体管为氧化物型薄膜晶体管(oxideTFT)；或者是低温多晶硅(LTPS)半导体移位寄存器单元，即其中的开关晶体管为低温多晶硅型薄膜晶体管(LTPS-TFT)等其他类型的移位寄存器单元，本示例性实施例中对此不做特殊限定。Each of the shift register units includes a first input terminal VIN1, a second input terminal VIN2, a clock signal terminal CK1, a clock signal terminal CKB1, and an output terminal VOUT, wherein the first input terminal VIN1 of each shift register unit can be Receiving a first input signal, the second input terminal VIN2 can receive a second input signal, the clock signal terminal CK1 and the clock signal terminal CKB1 can be used to receive the first clock signal CK1 and the second clock signal CKB1, and each shift The bit register unit provides an output signal at its output terminal VOUT according to the received first input signal, second input signal and clock signal. In this exemplary embodiment, the shift register unit may be composed of a plurality of switching transistors and capacitors, and the shift register unit may be an amorphous silicon (AlphaSilica) semiconductor shift register unit, that is, the switching transistors thereof are amorphous silicon type Thin-film transistor (a-SiTFT); it can also be an oxide (Oxide) semiconductor shift register unit, that is, the switch transistor is an oxide-type thin-film transistor (oxideTFT); or a low-temperature polysilicon (LTPS) semiconductor shift register unit, That is, the switching transistors are other types of shift register units such as low-temperature polysilicon thin-film transistors (LTPS-TFT), which are not specifically limited in this exemplary embodiment.
其中，第m级移位寄存器单元的第一输入端VIN1接收的第一输入信号为第m-1级移位寄存器单元输出端的输出信号，第m级移位寄存器单元的第二输入端VIN2接收的第二输入信号为第m+1级移位寄存器单元输出端VOUT的输出信号，其中，m为正整数，且1<m<N。例如，第2级移位寄存器单元的第一输入端VIN1接收的第一输入信号为第1级移位寄存器单元输出端VOUT的输出信号，第2级移位寄存器单元的第二输入端VIN2接收的第二输入信号为第3级移位寄存器单元输出端VOUT的输出信号；第3级移位寄存器单元的第一输入端VIN1接收的第一输入信号为第2级移位寄存器单元输出端VOUT的输出信号，第3级移位寄存器单元的第二输入端VIN2接收的第二输入信号为第4级移位寄存器单元输出端VOUT的输出信号等等。Wherein, the first input signal received by the first input terminal VIN1 of the shift register unit of the mth stage is the output signal of the output terminal of the shift register unit of the m-1th stage, and the second input terminal VIN2 of the shift register unit of the mth stage receives The second input signal of is the output signal of the output terminal VOUT of the shift register unit of the m+1st stage, wherein, m is a positive integer, and 1<m<N. For example, the first input signal received by the first input terminal VIN1 of the second-stage shift register unit is the output signal of the output terminal VOUT of the first-stage shift register unit, and the second input terminal VIN2 of the second-stage shift register unit receives The second input signal of the second input signal is the output signal of the output terminal VOUT of the third-stage shift register unit; the first input signal received by the first input terminal VIN1 of the third-stage shift register unit is the output terminal VOUT of the second-stage shift register unit The output signal of the second input terminal VIN2 of the third-stage shift register unit receives the second input signal is the output signal of the output terminal VOUT of the fourth-stage shift register unit, and so on.
继续参考图4，本示例实施方式中，第1级移位寄存器单元SR1的第一输入端VIN1接收的第一输入信号为一第一起始信号STV1，第1级至第5级移位寄存器单元输出端VOUT的输出信号均用作有效栅极扫描信号，即栅极扫描信号S2～S6；本示例实施方式中，有效栅极扫描信号是指输入到显示区域，用于开启/关断与栅极驱动电路连接的像素行中的开关晶体管的扫描信号，即区别于背景技术中的无效栅极扫描信号。进一步的，本示例实施方式中还可以利用第一起始信号STV1提供一有效栅极扫描信号，因此，参考图5，图5是图2中栅极驱动器输出信号的波形示意图，从图中可知，图4中的栅极驱动器可以利用5级移位寄存器单元生成6个有效栅极扫描信号S1～S6。Continuing to refer to FIG. 4 , in this exemplary embodiment, the first input signal received by the first input terminal VIN1 of the shift register unit SR1 of the first stage is a first start signal STV1, and the shift register units of the first stage to the fifth stage The output signals of the output terminal VOUT are all used as effective gate scanning signals, that is, gate scanning signals S2 to S6; The scanning signal of the switch transistor in the pixel row connected to the electrode driving circuit is different from the invalid gate scanning signal in the background art. Further, in this exemplary embodiment, the first start signal STV1 can also be used to provide an effective gate scanning signal. Therefore, referring to FIG. 5, FIG. 5 is a schematic waveform diagram of the output signal of the gate driver in FIG. 2. It can be seen from the figure that The gate driver in FIG. 4 can generate 6 effective gate scan signals S1-S6 by using a 5-stage shift register unit.
由上述描述可知，本示例实施方式中的栅极驱动器通过利用起始信号提供有效栅极扫描信号，可以有效减少移位寄存器单元的数量，进而可以使得栅极驱动器的版图面积减小，为实现更高分辨率和更窄边框的显示面板提供了技术支持；同时，由于节省了移位寄存器单元的数量，从而可以简化制备工艺，压缩制备成本。It can be seen from the above description that the gate driver in this exemplary embodiment can effectively reduce the number of shift register units by using the start signal to provide an effective gate scan signal, thereby reducing the layout area of the gate driver, and achieving The display panel with higher resolution and narrower frame provides technical support; at the same time, because the number of shift register units is saved, the manufacturing process can be simplified and the manufacturing cost can be reduced.
参考图6，图6是本发明实施例提供的又一种栅极驱动器的结构示意图，如图中所示，在反向扫描时，原本第1级的移位寄存器单元SR1将成为最末级的移位寄存器单元；此时，图示中VIN2为第一输入端，VIN1为第二输入端，并且原本最末级的移位寄存器单元SR5将成为第1级移位寄存器单元，其输入端VIN2接收第一起始信号STV1。如上所述，本示例实施方式中可以利用第一起始信号STV1提供有效栅极扫描信号。即无论在正向扫描还是反向扫描中，凡是利用起始信号提供有效栅极扫描信号均属本发明的保护范围。Referring to FIG. 6, FIG. 6 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention. As shown in the figure, during reverse scanning, the shift register unit SR1 of the first stage will become the last stage At this time, VIN2 in the figure is the first input terminal, VIN1 is the second input terminal, and the original last-stage shift register unit SR5 will become the first-stage shift register unit, and its input terminal VIN2 receives the first start signal STV1. As described above, the effective gate scan signal may be provided using the first start signal STV1 in this example embodiment. That is, no matter in forward scanning or reverse scanning, any use of the start signal to provide an effective gate scanning signal falls within the protection scope of the present invention.
本发明的其他示例实施方式中，还可以在正向扫描结束时利用一第二起始信号STV2输入至最末级，即第N级移位寄存器单元的第二输入端VIN2。例如，参考图7，图7是本发明实施例提供的又一种栅极驱动器的结构示意图，其中，第5级移位寄存器单元接收的第二输入信号为一第二起始信号STV2。通过利用第二起始信号STV2作为最末级移位寄存器单元的第二输入信号，则可以无需在第N级移位寄存器单元之后设置虚拟移位寄存器单元提供第二输入信号，进而可以使得栅极驱动器的版图面积进一步的减小。In other exemplary embodiments of the present invention, a second start signal STV2 may also be used to input to the last stage, ie, the second input terminal VIN2 of the shift register unit of the Nth stage, at the end of the forward scan. For example, refer to FIG. 7 , which is a schematic structural diagram of another gate driver provided by an embodiment of the present invention, wherein the second input signal received by the fifth-stage shift register unit is a second start signal STV2 . By using the second start signal STV2 as the second input signal of the last-stage shift register unit, it is not necessary to set a dummy shift register unit after the N-stage shift register unit to provide the second input signal, thereby making the gate The layout area of the pole driver is further reduced.
本示例实施方式中，第二起始信号STV2与第一起始信号STV1间隔一帧(Frame)，例如，第一起始信号STV1为第X帧的起始信号，第二起始信号STV2为第X+1帧的起始信号。本示例实施方式中，一帧是指栅极驱动器从第1级到第N级移位寄存器单元全部正向扫描一次或者全部反向扫描一次。在画面显示上，可以是图像刷新一次。In this exemplary embodiment, the second start signal STV2 is separated from the first start signal STV1 by one frame (Frame). For example, the first start signal STV1 is the start signal of the Xth frame, and the second start signal STV2 is the Xth frame. +1 start signal for frame. In this example embodiment, one frame means that the gate driver scans all the shift register units from the first stage to the Nth stage once in the forward direction or scans all the shift register units in the reverse direction once. On the screen display, the image may be refreshed once.
进一步的，本示例实施方式中还可以利用第二起始信号提供一有效栅极扫描信号，即除了所有移位寄存器本身输出的有效栅极扫描信号，本示例实施方式中还可以利用第一起始信号以及第二起始信号额外提供两个有效栅极扫描信号。例如，图7中的栅极驱动器可以利用5级移位寄存器单元生成7个有效栅极扫描信号。相比现有技术，可以在避免设置虚拟(Dummy)移位寄存单元的同时，进一步有效减少移位寄存器单元的数量，可以使得栅极驱动器的版图面积进一步的减小。Further, in this example embodiment, the second start signal can also be used to provide an effective gate scan signal, that is, in addition to the effective gate scan signal output by all shift registers themselves, the first start signal can also be used in this example embodiment signal and the second start signal additionally provide two valid gate scan signals. For example, the gate driver in FIG. 7 can generate 7 valid gate scan signals using a 5-stage shift register unit. Compared with the prior art, while avoiding setting dummy shift register units, the number of shift register units can be further effectively reduced, and the layout area of the gate driver can be further reduced.
参考图8，图8是本发明实施例提供的又一种栅极驱动器的结构示意图；本示例实施方式中各移位寄存器单元还可以包括一复位信号端RST。复位信号端RST用于接收一复位信号，从而可以利用复位信号对各个移位寄存器单元进行复位，例如，可以在当前帧开始扫描之前，利用复位信号清除上一帧的残留电压信号，避免栅极驱动器输出错误的栅极扫描信号，以及提升输出的栅极扫描信号的波形准确度。Referring to FIG. 8 , FIG. 8 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention; each shift register unit in this exemplary embodiment may further include a reset signal terminal RST. The reset signal terminal RST is used to receive a reset signal, so that each shift register unit can be reset by using the reset signal. For example, before the current frame starts scanning, the reset signal can be used to clear the residual voltage signal of the previous frame to avoid gate The driver outputs wrong gate scan signals, and improves the waveform accuracy of the output gate scan signals.
此外，本示例实施方式中所述栅极驱动器可以无需设置虚拟移位寄存器单元，而且各级移位寄存器单元均可以正确输出，因此本示例实施方式的栅极驱动器中每个移位寄存单元的输出端可以均与显示面板中的一条栅极线电连接，为该栅极线连接的像素行提供开启电压，避免生成的信号的浪费。In addition, the gate driver in this example embodiment does not need to set a virtual shift register unit, and the shift register units at all levels can output correctly, so the gate driver in this example embodiment of each shift register unit The output ends can all be electrically connected to a gate line in the display panel, and provide a turn-on voltage for the pixel row connected to the gate line, so as to avoid waste of generated signals.
在本示例的上述实施方式中，以栅极驱动器包括一个移位寄存器组为例进行说明。在本示例的其他实施方式中，栅极驱动器也可以包括多于一个的移位寄存器组。例如，参考图9，图9是本发明实施例提供的又一种栅极驱动器的结构示意图，其中，栅极驱动器包括第一移位寄存器组和第二移位寄存器组，第一移位寄存器组包括移位寄存器单元SR1A至SR5A，第二移位寄存器组包括移位寄存器单元SR1B至SR5B，第一移位寄存器组中的移位寄存器单元与第二移位寄存器组中的移位寄存器单元交错间隔排列，举例而言，图9中栅极驱动器中移位寄存器单元的排列顺序可以为SR1A、SR1B、SR2A、SR2B、SR3A、SR3B、SR4A、SR4B、SR5A、SR5B，通过上述排列顺序，可以交错输出栅极扫描信号，减少相邻两个栅极扫描信号之间的时间间隔。但本领域技术人员容易理解的是，当栅极驱动器包括三个或三个以上的移位寄存器组时，上述排列方式同样适用，例如，栅极驱动器还可以包括第三移位寄存器组，第三移位寄存器组可以包括移位寄存器单元SR1C至SR5C，则移位寄存器单元的排列顺序可以为SR1A、SR1B、SR1C、SR2A、SR2B、SR2C等。In the above-mentioned implementation manner of this example, the gate driver includes a shift register group as an example for description. In other implementations of this example, the gate driver may also include more than one shift register group. For example, referring to FIG. 9, FIG. 9 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention, wherein the gate driver includes a first shift register group and a second shift register group, and the first shift register The group includes shift register cells SR1A to SR5A, the second shift register group includes shift register cells SR1B to SR5B, the shift register cells in the first shift register group are connected to the shift register cells in the second shift register group Arranged in a staggered interval. For example, the order of the shift register units in the gate driver in Figure 9 can be SR1A, SR1B, SR2A, SR2B, SR3A, SR3B, SR4A, SR4B, SR5A, SR5B. Interleaved output gate scan signals reduce the time interval between two adjacent gate scan signals. However, those skilled in the art can easily understand that when the gate driver includes three or more shift register groups, the above arrangement is also applicable. For example, the gate driver may also include a third shift register group, the first The three shift register groups may include shift register units SR1C to SR5C, and the arrangement order of the shift register units may be SR1A, SR1B, SR1C, SR2A, SR2B, SR2C and so on.
本示例实施方式中还提供了另一种栅极驱动器。该栅极驱动器包括至少一个移位寄存器组。参考图10，图10是本发明实施例提供的又一种栅极驱动器的结构示意图，其中，栅极驱动器可以包括一个移位寄存器组，移位寄存器组可以包括级联的N级移位寄存器单元，其中，N为正整数，且N≥2；图10中以N等于5为例进行说明，即移位寄存器组可以包括级联的第1级移位寄存器单元SR1至第5级移位寄存器单元SR5；但本领域技术人员容易理解的是，N实际上可以为任意大于1的正整数。Another gate driver is also provided in this example embodiment. The gate driver includes at least one shift register set. Referring to FIG. 10, FIG. 10 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention, wherein the gate driver may include a shift register group, and the shift register group may include cascaded N-stage shift registers unit, where N is a positive integer, and N≥2; Figure 10 takes N equal to 5 as an example for illustration, that is, the shift register group can include cascaded first-stage shift register units SR1 to fifth-stage shift register unit SR5; however, those skilled in the art can easily understand that N can actually be any positive integer greater than 1.
每一移位寄存器单元均包括输入端VIN、时钟信号端CK1、时钟信号端CKB1以及输出端VOUT，其中，每一移位寄存器单元的输入端VIN可以接收一输入信号，时钟信号端CK1以及时钟信号端CKB1可以用于接收第一时钟信号CK1以及第二时钟信号CKB1，并且，每一移位寄存器单元根据接收的输入信号以及时钟信号在其输出端VOUT提供一输出信号。本示例实施方式中，移位寄存器单元可以由多个开关晶体管以及电容等元件构成，移位寄存器单元可以为非晶硅(AlphaSilica)半导体移位寄存器单元，也可以是氧化物半导体移位寄存器单元、低温多晶硅移位寄存器单元等其他类型的移位寄存器单元，本示例性实施例中对此不做特殊限定。Each shift register unit includes an input terminal VIN, a clock signal terminal CK1, a clock signal terminal CKB1 and an output terminal VOUT, wherein the input terminal VIN of each shift register unit can receive an input signal, the clock signal terminal CK1 and the clock The signal terminal CKB1 can be used to receive the first clock signal CK1 and the second clock signal CKB1, and each shift register unit provides an output signal at its output terminal VOUT according to the received input signal and the clock signal. In this exemplary embodiment, the shift register unit may be composed of a plurality of switching transistors and capacitors, and the shift register unit may be an amorphous silicon (AlphaSilica) semiconductor shift register unit, or an oxide semiconductor shift register unit. , low-temperature polysilicon shift register units and other types of shift register units, which are not specifically limited in this exemplary embodiment.
其中，第m级移位寄存器单元的输入端VIN接收的第一输入信号为第m-1级移位寄存器单元输出端VOUT的输出信号，其中，m为正整数，且1<m<N。例如，第2级移位寄存器单元的输入端VIN接收的输入信号为第1级移位寄存器单元输出端VOUT的输出信号，第3级移位寄存器单元的输入端VIN接收的输入信号为第2级移位寄存器单元输出端VOUT的输出信号等等。Wherein, the first input signal received by the input terminal VIN of the shift register unit of the mth stage is the output signal of the output terminal VOUT of the shift register unit of the m-1th stage, wherein m is a positive integer, and 1<m<N. For example, the input signal received by the input terminal VIN of the shift register unit of the second stage is the output signal of the output terminal VOUT of the shift register unit of the first stage, and the input signal received by the input terminal VIN of the shift register unit of the third stage is the output signal of the second stage shift register unit. The output signal of the output terminal VOUT of the stage shift register unit and the like.
继续参考图10，本示例实施方式中，第1级移位寄存器单元SR1的第一输入端VIN接收的输入信号为一起始信号STV，第1级至第5级移位寄存器单元输出端VOUT的输出信号均用作有效栅极扫描信号，即栅极扫描信号S2～S6。进一步的，本示例实施方式中还利用起始信号STV提供一有效栅极扫描信号，因此，图10中的栅极驱动器可以利用5级移位寄存器单元生成6个有效栅极扫描信号。Continuing to refer to FIG. 10 , in this exemplary embodiment, the input signal received by the first input terminal VIN of the first-stage shift register unit SR1 is a start signal STV, and the output terminal VOUT of the first-stage to fifth-stage shift register units The output signals are all used as effective gate scanning signals, that is, gate scanning signals S2 - S6 . Further, in this exemplary embodiment, the start signal STV is also used to provide an effective gate scan signal. Therefore, the gate driver in FIG. 10 can generate 6 effective gate scan signals by using a 5-stage shift register unit.
由上述描述可知，本示例实施方式中的栅极驱动器通过利用起始信号STV提供有效栅极扫描信号，可以有效减少移位寄存器单元的数量，进而可以使得栅极驱动器的版图面积减小，为实现更高分辨率和更窄边框的显示面板提供了技术支持；同时，由于节省了移位寄存器单元的数量，从而可以简化制备工艺，压缩制备成本。It can be seen from the above description that the gate driver in this exemplary embodiment can effectively reduce the number of shift register units by using the start signal STV to provide an effective gate scanning signal, thereby reducing the layout area of the gate driver, as A display panel that achieves higher resolution and narrower frame provides technical support; at the same time, because the number of shift register units is saved, the manufacturing process can be simplified and the manufacturing cost can be reduced.
参考图11，图11是本发明实施例提供的又一种栅极驱动器的结构示意图，其中，本示例实施方式中各移位寄存器单元还可以包括一复位信号端RST。复位信号端RST用于接收一复位信号，从而可以利用复位信号对各个移位寄存器单元进行复位，从而可以在当前帧信号开始扫描之前，利用复位信号清除上一帧信号的残留电压信号，避免栅极驱动器输出错误的栅极扫描信号以及提升输出的栅极扫描信号的波形准确度。Referring to FIG. 11 , FIG. 11 is a schematic structural diagram of another gate driver provided by an embodiment of the present invention, wherein each shift register unit in this exemplary embodiment may further include a reset signal terminal RST. The reset signal terminal RST is used to receive a reset signal, so that the reset signal can be used to reset each shift register unit, so that the reset signal can be used to clear the residual voltage signal of the previous frame signal before the current frame signal starts scanning, so as to avoid gate The electrode driver outputs wrong gate scan signals and improves the waveform accuracy of the output gate scan signals.
此外，本示例实施方式中所述栅极驱动器可以无需设置虚拟移位寄存器单元，而且各级移位寄存器单元均可以正确输出，因此本示例实施方式的栅极驱动器中每个移位寄存单元的输出端可以均与显示面板中的一条栅极线电连接，为该栅极线连接的像素行提供开启电压，避免生成的信号的浪费。In addition, the gate driver in this example embodiment does not need to set a virtual shift register unit, and the shift register units at all levels can output correctly, so the gate driver in this example embodiment of each shift register unit The output ends can all be electrically connected to a gate line in the display panel, and provide a turn-on voltage for the pixel row connected to the gate line, so as to avoid waste of generated signals.
在本示例的上述实施方式中，以栅极驱动器包括一个移位寄存器组为例进行说明。在本示例的其他实施方式中，栅极驱动器也可以包括多于一个的移位寄存器组。例如，参考图12，图12是本发明实施例提供的又一种栅极驱动器的结构示意图，其中，栅极驱动器可以包括第一移位寄存器组和第二移位寄存器组，第一移位寄存器组可以包括移位寄存器单元SR1A至SR5A，第二移位寄存器组可以包括移位寄存器单元SR1B至SR5B，第一移位寄存器组中的移位寄存器单元与第二移位寄存器组中的移位寄存器单元交错间隔排列，举例而言，图12中栅极驱动器中移位寄存器单元的排列顺序可以为SR1A、SR1B、SR2A、SR2B、SR3A、SR3B、SR4A、SR4B、SR5A、SR5B，通过上述排列顺序，可以交错输出栅极扫描信号，减少相邻两个栅极扫描信号之间的时间间隔。但本领域技术人员容易理解的是，当栅极驱动器包括三个或三个以上的移位寄存器组时，上述排列方式同样适用，例如，栅极驱动器还可以包括第三移位寄存器组，第三移位寄存器组可以包括移位寄存器单元SR1C至SR5C，则移位寄存器单元的排列顺序可以为SR1A、SR1B、SR1C、SR2A、SR2B、SR2C等。In the above-mentioned implementation manner of this example, the gate driver includes a shift register group as an example for description. In other implementations of this example, the gate driver may also include more than one shift register group. For example, refer to FIG. 12, which is a schematic structural diagram of another gate driver provided by an embodiment of the present invention, wherein the gate driver may include a first shift register group and a second shift register group, and the first shift register group The register group may include shift register units SR1A to SR5A, the second shift register group may include shift register units SR1B to SR5B, the shift register units in the first shift register group are connected to the shift register units in the second shift register group The bit register units are arranged in a staggered interval. For example, the arrangement order of the shift register units in the gate driver in FIG. Sequentially, the gate scan signals can be staggered to reduce the time interval between two adjacent gate scan signals. However, those skilled in the art can easily understand that when the gate driver includes three or more shift register groups, the above arrangement is also applicable. For example, the gate driver may also include a third shift register group, the first The three shift register groups may include shift register units SR1C to SR5C, and the arrangement order of the shift register units may be SR1A, SR1B, SR1C, SR2A, SR2B, SR2C and so on.
进一步的，本示例实施方式还提供了一种显示面板，该显示面板包括上述的任意一种栅极驱动器，但是不限于此。由于使用的栅极驱动器具有更小的版图面积，因此该显示面板的有效显示面积得以增加，有利于提升显示面板的分辨率；同时，该显示面板的边框可以做的更窄。本示例性实施例中，该显示面板可以为液晶显示面板或者OLED显示面板，在本发明的其他示例性实施例中，该显示面板也可能是PLED(PolymerLight-EmittingDiode，高分子发光二极管)显示面板、PDP(PlasmaDisplayPanel，等离子显示)显示面板等其他平板显示面板，即本示例实施方式中并不特别局限适用范围。Further, this exemplary embodiment also provides a display panel, which includes any one of the above-mentioned gate drivers, but is not limited thereto. Since the gate driver used has a smaller layout area, the effective display area of the display panel is increased, which is beneficial to improving the resolution of the display panel; at the same time, the frame of the display panel can be made narrower. In this exemplary embodiment, the display panel may be a liquid crystal display panel or an OLED display panel. In other exemplary embodiments of the present invention, the display panel may also be a PLED (Polymer Light-Emitting Diode, polymer light-emitting diode) display panel. , PDP (Plasma Display Panel, plasma display) display panel and other flat display panels, that is, the scope of application is not particularly limited in this exemplary embodiment.
综上所述，本发明的示例实施方式中，通过利用起始信号提供有效栅极扫描信号，可以有效减少移位寄存器单元的数量，进而可以使得栅极驱动器的版图面积减小，为实现更高分辨率和更窄边框的显示面板提供了技术支持；同时，由于节省了移位寄存器单元的数量，从而可以简化制备工艺，压缩制备成本。To sum up, in the exemplary embodiment of the present invention, by using the start signal to provide an effective gate scanning signal, the number of shift register units can be effectively reduced, and the layout area of the gate driver can be reduced. The display panel with high resolution and narrower frame provides technical support; at the same time, because the number of shift register units is saved, the manufacturing process can be simplified and the manufacturing cost can be reduced.
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已揭露的实施例并未限制本发明的范围。相反地，在不脱离本发明的精神和范围内所作的更动与润饰，均属本发明的专利保护范围。The present invention has been described by the above-mentioned related embodiments, however, the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, changes and modifications made without departing from the spirit and scope of the present invention all belong to the scope of patent protection of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510992177.9ACN105448258B (en) | 2015-12-25 | 2015-12-25 | Gate drivers and display panel |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510992177.9ACN105448258B (en) | 2015-12-25 | 2015-12-25 | Gate drivers and display panel |
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| CN105448258Atrue CN105448258A (en) | 2016-03-30 |
| CN105448258B CN105448258B (en) | 2019-01-04 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201510992177.9AActiveCN105448258B (en) | 2015-12-25 | 2015-12-25 | Gate drivers and display panel |
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| CN108717843B (en)* | 2018-02-26 | 2020-04-14 | 友达光电股份有限公司 | Display device and gate driver thereof |
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| TR01 | Transfer of patent right | Effective date of registration:20201209 Address after:5-6 / F, building D, huilongda Industrial Park, Shuitian Private Industrial Park, Shiyan street, Bao'an District, Shenzhen City, Guangdong Province Patentee after:Shenzhen Haiyun Communication Co.,Ltd. Address before:201108 Shanghai city Minhang District Huaning Road No. 3388 Patentee before:Shanghai AVIC Optoelectronics Co.,Ltd. Patentee before:Tianma Micro-Electronics Co.,Ltd. Effective date of registration:20201209 Address after:Room a-430, 4 / F, block a, phase II, Guangxi Huike Technology Co., Ltd., No. 336, Beihai Avenue East extension line, Beihai Industrial Park, Guangxi Zhuang Autonomous Region Patentee after:BEIHAI HKC PHOTOELECTRIC TECHNOLOGY Co.,Ltd. Address before:5-6 / F, building D, huilongda Industrial Park, Shuitian Private Industrial Park, Shiyan street, Bao'an District, Shenzhen City, Guangdong Province Patentee before:Shenzhen Haiyun Communication Co.,Ltd. |