技术领域technical field
本发明涉及数字芯片领域，尤其涉及一种共享存储并发访问处理方法及装置。The invention relates to the field of digital chips, in particular to a shared storage concurrent access processing method and device.
背景技术Background technique
目前多数片上系统(SOC，SystemonChip)都存在不止一个处理器和协处理器，而且这些处理器之间的主要数据交互通过共享存储来实现。随着多核SOC的广泛应用，共享存储的访问冲突和带宽不足越来越成为制约系统性能的瓶颈。At present, most systems on a chip (SOC, System on Chip) have more than one processor and coprocessor, and the main data interaction between these processors is realized through shared memory. With the wide application of multi-core SOC, access conflicts and insufficient bandwidth of shared storage have increasingly become the bottleneck restricting system performance.
现有的共享存储接口改善的方法主要解决了减少访问延时、优化跨边界访问、消除非对齐访问开销、简单的访问冲突规避、优化连续地址访问的带宽和延时等，基本都是对特定场景的优化。The existing methods for improving the shared memory interface mainly solve the problems of reducing access delay, optimizing cross-boundary access, eliminating unaligned access overhead, simple access conflict avoidance, and optimizing the bandwidth and delay of continuous address access, etc., which are basically for specific Optimization of the scene.
如图1所示，为一种普通的共享存储并发访问方式。其中，只有一个逻辑上独立的存储器，当4个接口都有存储访问发生时，只有一个访问可以得到响应(如图中实线所示)。如此，即便具有4个独立接口，却只有一个接口的有效带宽。As shown in Figure 1, it is a common shared storage concurrent access method. Among them, there is only one logically independent memory, and when all four interfaces have storage access, only one access can be responded (as shown by the solid line in the figure). Thus, even with 4 independent interfaces, there is only the effective bandwidth of one interface.
如图2所示，为一种具有普通冲突规避的共享存储并发访问方式，有4个逻辑上独立逻辑块(Block)，但是接口上只能取队列头的访问，当4个接口都有存储访问发生时，只有不存在Block冲突的访问能够得到响应(如图中实线所示)。如此，即便具有4个独立接口，但由于Block冲突的概率很大，实际有效带宽只有单个接口的2.7倍。As shown in Figure 2, it is a shared storage concurrent access method with common conflict avoidance. There are 4 logically independent logical blocks (Block), but the interface can only access the head of the queue. When all 4 interfaces have storage access When it happens, only accesses without Block conflicts can be responded (as shown by the solid line in the figure). In this way, even with four independent interfaces, the actual effective bandwidth is only 2.7 times that of a single interface due to the high probability of block conflicts.
如图3所示，为普通的共享存储并发访问接口返回方式，访问从哪个接口接收则数据从哪个接口返回。显然当有多个访问从同一个接口进入时，虽然这些访问都将被接口所接受，但是同一时刻因为每个接口只能返回一个数据，所以只有那些没有接口冲突的访问得到了实际响应。如图3所示，access0和access1从接口0(Interface0)进入，access2和access3从接口1(Interface1)进入，虽然这些访问都将被相应接口所接受，但是同一时刻因为每个接口只能返回一个数据，因此只有access0和access2得到了实际响应(实线表示被接口所接受并得到了实际响应)，access1和access3没有得到实际响应(虚线表示被接口所接受没有但得到实际响应)。如此，即便具有4个独立接口，但是因为接口冲突的概率很大，实际有效带宽只有单个接口的2.7倍。As shown in Figure 3, it is the normal shared storage concurrent access interface return method, which interface the access is received from, and the data is returned from which interface. Obviously, when multiple accesses come in from the same interface, although these accesses will be accepted by the interface, but because each interface can only return one data at the same time, only those accesses without interface conflicts will be actually responded. As shown in Figure 3, access0 and access1 enter through interface 0 (Interface0), and access2 and access3 enter through interface 1 (Interface1). Although these accesses will be accepted by the corresponding interfaces, each interface can only return one at the same time. data, so only access0 and access2 get the actual response (the solid line indicates that they are accepted by the interface and get the actual response), and access1 and access3 do not get the actual response (the dotted line indicates that they are not accepted by the interface but get the actual response). In this way, even if there are four independent interfaces, the actual effective bandwidth is only 2.7 times that of a single interface due to the high probability of interface conflicts.
因此，需要提出一种新的方案，以更加有效的规避访问冲突和充分利用接口带宽，解决共享存储的访问冲突和带宽不足的问题，并保证基本不受访问方式的影响。Therefore, a new solution needs to be proposed to more effectively avoid access conflicts and make full use of interface bandwidth, solve the problems of shared storage access conflicts and insufficient bandwidth, and ensure that it is basically not affected by access methods.
发明内容Contents of the invention
有鉴于此，本发明的主要目的在于提供一种共享存储并发访问处理方法及装置，能更加有效的规避访问冲突和利用接口带宽，解决共享存储的访问冲突和带宽不足问题。In view of this, the main purpose of the present invention is to provide a shared storage concurrent access processing method and device, which can more effectively avoid access conflicts and utilize interface bandwidth, and solve the problems of shared storage access conflicts and insufficient bandwidth.
为达到上述目的，本发明的技术方案是这样实现的：In order to achieve the above object, technical solution of the present invention is achieved in that way:
本发明实施例中提供了一种共享存储并发访问处理方法，包括：An embodiment of the present invention provides a shared storage concurrent access processing method, including:
对于各个访问接口上的访问队列，从任意一个或多个所述访问队列任意选择未完成的存储访问，所选择的存储访问之间不存在堆Bank冲突；For the access queues on each access interface, arbitrarily select unfinished storage accesses from any one or more of the access queues, and there is no heap Bank conflict between the selected storage accesses;
对所选择的存储访问并行译码，并传输给各自对应的Bank。The selected storage accesses are decoded in parallel and transmitted to the corresponding Banks.
上述方案中，所述方法还包括：In the above scheme, the method also includes:
根据所选择的存储访问的ID，随时更新其传输状态；According to the ID of the selected storage access, update its transfer status at any time;
将已处理完成的存储访问的ID告知相应的访问接口，使得访问接口将相应的存储访问从访问队列中移除。The corresponding access interface is notified of the ID of the processed storage access, so that the access interface removes the corresponding storage access from the access queue.
上述方案中，每个所述访问接口对应一个含多个未完成传输的访问队列，所选择的存储访问不大于访问接口总数。In the above solution, each access interface corresponds to an access queue containing multiple unfinished transmissions, and the selected storage access is not greater than the total number of access interfaces.
本发明实施例中还提供了一种共享存储并发访问处理装置，包括：共享总线、多个访问接口、共享存储访问交换管理单元和共享存储器，其中，An embodiment of the present invention also provides a shared storage concurrent access processing device, including: a shared bus, multiple access interfaces, a shared storage access exchange management unit, and a shared memory, wherein,
共享总线，用于为来自访问源的存储访问提供读写通道，支持未完成传输，支持乱序传输；Shared bus, which is used to provide read and write channels for storage access from access sources, supports incomplete transfers, and supports out-of-order transfers;
访问接口，用于接受通过所述共享总线送来的存储访问，并将接受的存储访问放入访问队列；An access interface, configured to accept storage access sent through the shared bus, and put the accepted storage access into an access queue;
共享存储访问交换管理单元包括：访问选择模块和并行译码模块，其中，The shared storage access exchange management unit includes: an access selection module and a parallel decoding module, wherein,
访问选择模块，用于针对各个所述访问接口上的访问队列，从任意一个或多个所述访问队列任意选择未完成的存储访问，所选择的存储访问之间不存在Bank冲突；The access selection module is configured to arbitrarily select unfinished storage accesses from any one or more of the access queues for the access queues on each of the access interfaces, and there is no Bank conflict between the selected storage accesses;
并行译码模块，用于对所述访问选择模块选择的存储访问并行译码，并传输给各自对应的堆Bank；A parallel decoding module, configured to perform parallel decoding on the storage accesses selected by the access selection module, and transmit them to respective corresponding heap Banks;
共享存储器，包括多个逻辑块，所述逻辑块与访问接口没有明显的对应关系，每个逻辑块包括多个Bank，所述逻辑块是指提供连续地址的逻辑存储单元，Bank是用来进行地址行列交织的更小的物理存储单元。Shared memory includes a plurality of logical blocks. The logical blocks have no obvious correspondence with the access interface. Each logical block includes a plurality of Banks. The logical blocks refer to logical storage units that provide continuous addresses. Banks are used to perform A smaller physical storage unit whose address rows and columns are interleaved.
上述方案中，所述共享存储访问交换管理单元还包括传输状态更新模块；In the above solution, the shared storage access exchange management unit further includes a transmission status update module;
所述访问选择模块，还用于在选择存储访问后，将所选择的存储访问的ID发送给所述传输状态更新模块；The access selection module is further configured to send the ID of the selected storage access to the transmission status update module after selecting the storage access;
所述传输状态更新模块，用于根据所述存储访问的ID，随时更新其传输状态；并，将已处理完成的存储访问的ID告知相应的访问接口；The transmission status update module is configured to update the transmission status at any time according to the ID of the storage access; and notify the corresponding access interface of the ID of the storage access that has been processed;
所述访问接口，还用于根据已处理完成的存储访问的ID，将相应的存储访问从访问队列中移除。The access interface is further configured to remove the corresponding storage access from the access queue according to the ID of the processed storage access.
上述方案中，每个所述访问接口对应一个含多个未完成传输的访问队列，所选择的存储访问不大于访问接口总数。In the above solution, each access interface corresponds to an access queue containing multiple unfinished transmissions, and the selected storage access is not greater than the total number of access interfaces.
本发明实施例中还提供了一种共享存储并发访问处理方法，包括：The embodiment of the present invention also provides a shared storage concurrent access processing method, including:
对于每个需要返回的反馈数据，选择任意一个访问接口作为其通过接口；For each feedback data that needs to be returned, select any access interface as its passing interface;
将反馈数据及其伴随信息送给访问接口，所述伴随信息包含访问ID和所述通过接口的标识。The feedback data and its accompanying information are sent to the access interface, and the accompanying information includes the access ID and the identification of the passing interface.
上述方案中，选择任意一个访问接口作为其通过接口，包括：In the above solution, choose any access interface as its passing interface, including:
优先选择所述反馈数据对应的访问接口作为其通过接口；Preferentially selecting the access interface corresponding to the feedback data as its passing interface;
如果所述反馈数据对应的访问接口存在访问冲突，则选择任意一个当前不需要返回数据的访问接口作为其通过接口。If the access interface corresponding to the feedback data has an access conflict, select any access interface that does not currently need to return data as its passing interface.
上述方案中，所述方法还包括：In the above scheme, the method also includes:
访问接口接收所述反馈数据及其伴随信息，并根据所述伴随信息将所述反馈数据通过共享总线返回给访问源。The access interface receives the feedback data and its accompanying information, and returns the feedback data to the access source through the shared bus according to the accompanying information.
本发明实施例中还提供了一种共享存储并发访问处理装置，包括：共享总线、多个访问接口、共享存储访问交换管理单元和共享存储器，其中，An embodiment of the present invention also provides a shared storage concurrent access processing device, including: a shared bus, multiple access interfaces, a shared storage access exchange management unit, and a shared memory, wherein,
共享总线，用于为来自访问源的存储访问提供读写通道，支持未完成传输，支持乱序传输；Shared bus, which is used to provide read and write channels for storage access from access sources, supports incomplete transfers, and supports out-of-order transfers;
访问接口，用于接受通过所述共享总线送来的存储访问，并将接受的存储访问放入访问队列；以及，用于根据反馈数据的伴随信息，将需要返回的反馈数据通过所述共享总线返回给访问源；The access interface is used to accept the storage access sent through the shared bus, and put the accepted storage access into the access queue; and is used to pass the feedback data that needs to be returned through the shared bus according to the accompanying information of the feedback data return to the access source;
共享存储访问交换管理单元包括：接口选择模块，用于针对存储访问的反馈数据，选择任意一个所述访问接口作为其通过接口，并将所述反馈数据及其伴随信息送给访问接口，所述伴随信息包含所述反馈数据所对应存储访问的ID和所述通过接口的标识；The shared storage access exchange management unit includes: an interface selection module, for selecting any one of the access interfaces as the passing interface for the feedback data of storage access, and sending the feedback data and its accompanying information to the access interface, the The accompanying information includes the ID of the storage access corresponding to the feedback data and the identification of the interface;
共享存储器，包括多个逻辑块，每个逻辑块包括多个Bank，所述逻辑块是指提供连续地址的逻辑存储单元，Bank是用来进行地址行列交织的更小的物理存储单元。The shared memory includes a plurality of logical blocks, and each logical block includes a plurality of Banks. The logical block refers to a logical storage unit providing continuous addresses, and the Bank is a smaller physical storage unit for address row and column interleaving.
上述方案中，所述接口选择模块用于针对每个需要返回的反馈数据，选择任意一个访问接口作为其通过接口，包括：In the above solution, the interface selection module is used to select any access interface as its passing interface for each feedback data that needs to be returned, including:
针对每个需要返回的反馈数据，优先选择反馈数据对应的访问接口作为其通过接口；如果所述反馈数据对应的访问接口存在访问冲突，则选择任意一个当前不需要返回数据的访问接口作为其通过接口。For each feedback data that needs to be returned, the access interface corresponding to the feedback data is preferentially selected as its passing interface; if there is an access conflict with the access interface corresponding to the feedback data, any access interface that does not currently need to return data is selected as its passing interface interface.
本发明中，无视顺序的接受存储访问和选择存储访问，返回数据时选择任意一个接口作为通过接口，如此，多个接口共享同一个芯片内的存储器，改善存储访问带宽，能够更加有效的规避访问冲突和充分利用接口带宽，且基本不受访问方式的影响。In the present invention, storage access is accepted and storage access is selected regardless of the order, and any interface is selected as the passing interface when returning data. In this way, multiple interfaces share the memory in the same chip, which improves the storage access bandwidth and can avoid access more effectively. Conflict and make full use of the interface bandwidth, and basically not affected by the access mode.
附图说明Description of drawings
图1为一种普通的共享存储并发访问方式示意图；FIG. 1 is a schematic diagram of a common shared storage concurrent access method;
图2为一种具有普通冲突规避的共享存储并发访问方式示意图；Fig. 2 is a schematic diagram of a shared storage concurrent access method with common conflict avoidance;
图3为一种普通的共享存储并发访问接口返回方式示意图；Fig. 3 is a schematic diagram of a return mode of a common shared storage concurrent access interface;
图4为根据本发明实施例的共享存储并发访问方式示意图；4 is a schematic diagram of a shared storage concurrent access method according to an embodiment of the present invention;
图5为根据本发明实施例的共享存储并发访问接口返回方式示意图；FIG. 5 is a schematic diagram of a return mode of a shared storage concurrent access interface according to an embodiment of the present invention;
图6为根据本发明实施例的共享存储并发访问处理装置的组成结构示意图；6 is a schematic diagram of the composition and structure of a shared storage concurrent access processing device according to an embodiment of the present invention;
图7a-7b为根据本发明实施例的共享存储并发访问处理装置共享存储器地址编码示意图；7a-7b are schematic diagrams of shared memory address encoding of a shared memory concurrent access processing device according to an embodiment of the present invention;
图8为根据本发明实施例的共享存储并发访问处理方法流程图。FIG. 8 is a flowchart of a method for processing concurrent access to a shared storage according to an embodiment of the present invention.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚明白，以下举实施例并参照附图，对本发明进一步详细说明。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail by citing the following embodiments and referring to the accompanying drawings.
本发明实施例提供的共享存储并发访问处理方法及装置，通过多个接口共享同一个芯片内的存储器，来改善存储访问带宽，能够更加有效的规避访问冲突和充分利用接口带宽，且基本不受访问方式的影响。The shared storage concurrent access processing method and device provided by the embodiments of the present invention improve the storage access bandwidth by sharing the memory in the same chip through multiple interfaces, can more effectively avoid access conflicts and make full use of the interface bandwidth, and are basically not affected by impact of access.
下面以4个访问接口、存储器包含4个逻辑块(block)、16个独立的堆(Bank)为例来说明本发明实施例的具体实现过程。需要说明的是，本发明实施例同样适用且不限于8个接口、8个Block、32个Bank等的类似结构，此类似结构的主要特征是具有多个访问接口，Block和Bank两级组织的共享存储。The specific implementation process of the embodiment of the present invention will be described below by taking 4 access interfaces, the memory including 4 logic blocks (blocks), and 16 independent heaps (Banks) as examples. It should be noted that the embodiment of the present invention is also applicable to and not limited to a similar structure of 8 interfaces, 8 Blocks, 32 Banks, etc. The main feature of this similar structure is that it has multiple access interfaces, and the two-level organization of Block and Bank shared storage.
如图4所示，存储器中有4个逻辑上独立的block以及16个独立的Bank，当4个接口都有存储访问发生时，每个访问接口对应一个含多个未完成传输的访问队列，本发明实施例利用乱序功能可从4个从设备的四个访问队列access01～access04、access11～access14、access21～access24、access31～access34中，从任意访问队列任意取存储访问，所选择的存储访问不大于访问接口总数，对所选择的访问存储进行并行处理，只要不存在Bank冲突的访问都将得到响应，不需要按照访问队列的次序或者每个访问队列取一个访问的规则来处理存储访问，这样的话，Bank冲突的概率接近于0，实际有效带宽约为有单个接口的4倍。例如，如图4所示，可以同时取access01、access03、access21、access34进行并行处理。As shown in Figure 4, there are 4 logically independent blocks and 16 independent banks in the memory. When all 4 interfaces have storage access, each access interface corresponds to an access queue with multiple unfinished transfers. In the embodiment of the present invention, the out-of-order function can be used to arbitrarily take storage access from any of the four access queues access01-access04, access11-access14, access21-access24, and access31-access34 of the four slave devices, and the selected storage access It is not greater than the total number of access interfaces. The selected access storage is processed in parallel. As long as there is no Bank conflict, the access will be responded. It is not necessary to process storage access according to the order of the access queue or the rule that each access queue takes one access. In this case, the probability of bank conflict is close to 0, and the actual effective bandwidth is about four times that of a single interface. For example, as shown in FIG. 4, access01, access03, access21, and access34 can be simultaneously processed for parallel processing.
对于并发访问的接口返回，本发明实施例中反馈数据可以通过任何一个访问接口返回，不需要按照“从哪儿来就从哪儿回的规则”返回数据，只要当前接口上没有需要返回的数据，就可以用这个接口返回反馈数据。利用那些没有数据需要返回的接口来解决接口上的访问冲突，任何时刻所有的访问都能得到实际响应，这样的话，实际有效带宽为单个接口的4倍。如图5所示，access0和access1存在访问冲突，返回数据时，对于access1的反馈数据不用原来的接口Interface0，而用了没有数据需要返回的接口Interface1来返回其反馈数据。在access2和access3存在访问冲突时，access2和access3都有数据需要返回，对于access1的反馈数据用接口Interface2返回，对于access3的反馈数据用接口Interface3返回。For the interface return of concurrent access, the feedback data in the embodiment of the present invention can be returned through any access interface, and there is no need to return data according to the "rule of returning from wherever it comes from". As long as there is no data to be returned on the current interface, it can be You can use this interface to return feedback data. Use those interfaces that have no data to return to resolve access conflicts on the interface, and all accesses at any time can get actual responses. In this case, the actual effective bandwidth is 4 times that of a single interface. As shown in Figure 5, there is an access conflict between access0 and access1. When returning data, the original interface Interface0 is not used for the feedback data of access1, but the interface Interface1, which has no data to be returned, is used to return its feedback data. When there is an access conflict between access2 and access3, both access2 and access3 need to return data, the feedback data of access1 is returned by interface Interface2, and the feedback data of access3 is returned by interface Interface3.
如图6所示，4个接口的共享存储并发访问处理装置结构，主要包括：共享总线、4个访问接口Slave0～Slave3、共享存储访问交换管理(Sharedmemoryaccessswitch)单元、共享存储器。As shown in FIG. 6 , the structure of the shared memory concurrent access processing device with four interfaces mainly includes: a shared bus, four access interfaces Slave0-Slave3, a shared memory access switch management (Shared memory access switch) unit, and a shared memory.
共享总线，为来自访问源的存储访问提供读写通道，可以是任意拓扑但是符合以下几个主要特点(如图6是一个读写通道分离的示意，同样支持读写通道合一的总线)：Master到从设备(Slave)按照地址路由；slave到Master按照ID路由；支持未完成传输(outstanding)；支持乱序传输(outoforder)。The shared bus provides read and write channels for storage access from access sources. It can be any topology but meets the following main features (Figure 6 is a schematic diagram of separation of read and write channels, and also supports a bus with integrated read and write channels): Master to slave device (Slave) is routed according to address; slave to master is routed according to ID; outstanding transmission is supported; out-of-order transmission is supported.
四个访问接口Slave0～Slave3统一管理，Slave0～Slave3中每个访问接口的访问队列都有4个位置(WID0&RID0～WID3&RID3)，用于接受通过所述共享总线送来的存储访问，并将接受的存储访问放入访问队列；此外，访问接口还可以用于根据已处理完成的存储访问的ID，将相应的存储访问从访问队列中移除。除此之外，还可以用于根据反馈数据的伴随信息，将需要返回的反馈数据通过所述共享总线返回给访问源。The four access interfaces Slave0～Slave3 are managed in a unified manner, and the access queue of each access interface in Slave0～Slave3 has 4 positions (WID0&RID0～WID3&RID3), which are used to accept the storage access sent through the shared bus, and the received The storage access is put into the access queue; in addition, the access interface can also be used to remove the corresponding storage access from the access queue according to the ID of the processed storage access. In addition, it can also be used to return the feedback data that needs to be returned to the access source through the shared bus according to the accompanying information of the feedback data.
共享存储访问交换管理单元包括访问选择(accessselect)模块、并行译码(paralleldecoding)模块、传输状态更新(transactionstateupdate)模块，访问选择模块，用于针对各个所述访问接口上的访问队列，从任意一个或多个访问队列任意选择未完成的存储访问，所选择的存储访问之间不存在Bank冲突即可；并行译码模块，用于对所述访问选择模块选择的存储访问并行译码，并传输给各自对应的Bank；所述访问选择模块，还用于在选择存储访问后，将所选择的存储访问的ID发送给所述传输状态更新模块；所述传输状态更新模块，用于根据所述存储访问的ID，随时更新其传输状态；并，将已处理完成的存储访问的ID告知相应的访问接口。除此之外，还可以包含接口选择(datefeedback&interfaceselect)模块，用于针对每个反馈数据，选择任意一个所述访问接口作为其通过接口，并将所述反馈数据及其伴随信息送给访问接口，所述伴随信息包含所述反馈数据所对应存储访问的ID和所述通过接口的标识。The shared storage access exchange management unit includes an access selection (accessselect) module, a parallel decoding (paralleldecoding) module, a transmission state update (transactionstateupdate) module, and an access selection module, which is used to select from any one of the access queues on each of the access interfaces. or a plurality of access queues arbitrarily select unfinished storage accesses, as long as there is no Bank conflict between the selected storage accesses; the parallel decoding module is used to parallelly decode the storage accesses selected by the access selection module, and transmit to each corresponding Bank; the access selection module is also used to send the ID of the selected storage access to the transmission status update module after selecting storage access; the transmission status update module is used to The ID of the storage access is updated at any time for its transmission status; and the ID of the storage access that has been processed is notified to the corresponding access interface. In addition, it may also include an interface selection (datefeedback&interfaceselect) module, which is used to select any one of the access interfaces as its passing interface for each feedback data, and send the feedback data and its accompanying information to the access interface, The accompanying information includes the ID of the storage access corresponding to the feedback data and the identifier of the passing interface.
如图6所示，共享存储器包含4个逻辑块Block0～Block3，每个逻辑块都包含四个Bank(Bank0～Bank3)，所述逻辑块是指提供连续地址的逻辑存储单元，Bank是用来进行地址行列交织的更小的物理存储单元。每个Bank负责多个地址，也就是说，多个访问的地址位于同一个Bank，访问到来时，根据访问的地址将访问放到相应的Bank。实际应用中，共享存储器可以采用两级组织，如图7a所示，包含按照连续地址编码的四个逻辑块(Block)，便于根据功能存储数据来避免并发访问之间的冲突；如图7b所示，每个Block包含按照横向地址编码的四个Bank，便于根据统计特性存储数据来避免并发访问之间的冲突。上述装置中，字长为128bit；第一个字在Bank0，第二个字在Bank1，第三个字在Bank2，第四个字在Bank3，以此类推。也就是Block内顺序编址，Bank间横向编址，Bank内地址不连续(公差4的等差数列)，地址在Bank间做行列交织。As shown in Figure 6, the shared memory includes 4 logical blocks Block0～Block3, and each logical block includes four Banks (Bank0～Bank3). The logical blocks refer to logical storage units that provide continuous addresses. A smaller physical storage unit with address row and column interleaving. Each Bank is responsible for multiple addresses, that is, multiple accessed addresses are located in the same Bank. When an access comes, the access is placed in the corresponding Bank according to the accessed address. In practical applications, the shared memory can adopt a two-level organization, as shown in Figure 7a, including four logic blocks (Block) coded according to consecutive addresses, which is convenient for storing data according to functions to avoid conflicts between concurrent accesses; as shown in Figure 7b As shown, each Block contains four Banks coded according to horizontal addresses, which is convenient for storing data according to statistical characteristics to avoid conflicts between concurrent accesses. In the above device, the word length is 128 bits; the first word is in Bank0, the second word is in Bank1, the third word is in Bank2, the fourth word is in Bank3, and so on. That is, sequential addressing within a block, horizontal addressing between banks, discontinuous addresses within a bank (an arithmetic sequence with a tolerance of 4), and interleaving of rows and columns between banks.
其中，所述接口选择模块用于针对每个需要返回的反馈数据，选择任意一个访问接口作为其通过接口，包括：针对每个需要返回的反馈数据，优先选择反馈数据对应的访问接口作为其通过接口；如果所述反馈数据对应的访问接口存在访问冲突，则选择任意一个当前不需要返回数据的访问接口作为其通过接口。Wherein, the interface selection module is used to select any access interface as its passing interface for each feedback data that needs to be returned, including: for each feedback data that needs to be returned, preferentially select the access interface corresponding to the feedback data as its passing interface interface; if the access interface corresponding to the feedback data has an access conflict, select any access interface that currently does not need to return data as its passing interface.
如图8所示，通过图6所示的装置可以实现本发明实施例的共享存储并发访问处理方法，所述方法具体可以包括如下步骤：As shown in FIG. 8, the shared storage concurrent access processing method of the embodiment of the present invention can be realized by the device shown in FIG. 6, and the method may specifically include the following steps:
步骤801：访问源通过共享总线将存储访问送到各个访问接口Slave0～Slave3上，根据Slave0～Slave3内4个访问队列的总深度判断对新来的多个存储访问是否接受，将已接受的存储访问放到访问队列中；Step 801: The access source sends the storage access to each access interface Slave0-Slave3 through the shared bus, judges whether to accept multiple new storage accesses according to the total depth of the 4 access queues in Slave0-Slave3, and stores the accepted ones Access is placed in the access queue;
其中，每个访问接口优先接受各自对应的存储访问。4个访问队列的总空间不足时，可以根据任何策略仲裁即根据应用特点选取接受或不接受新来的存储访问。Wherein, each access interface preferentially accepts its corresponding storage access. When the total space of the four access queues is insufficient, it can choose to accept or not accept new storage access according to any policy arbitration, that is, according to application characteristics.
步骤802：共享存储访问交换管理单元的访问选择模块从分别对应Slave0～Slave3的4个访问队列的32个位置上已接受但是未完成的存储访问中，无视顺序的选择4个没有Bank冲突的存储访问，并将所选择的存储访问的ID送给共享存储访问交换管理模块的传输状态更新模块；Step 802: The access selection module of the shared storage access switching management unit selects 4 storages without Bank conflicts from the 32 positions of the 4 access queues corresponding to Slave0~Slave3 but not yet completed, regardless of the order. access, and send the ID of the selected storage access to the transmission status update module of the shared storage access exchange management module;
其中，选择存储访问时可以根据任何策略仲裁，重点在于从四个访问队列的32个位置上任意选择一个或多个存储访问进行并行处理，但是同时选择出来的存储访问数量不大于共享存储器的逻辑块数量。本发明实施例中，所选出的存储访问数量不超过4个(总的接口数)即可。Among them, when selecting storage access, it can be arbitrated according to any strategy. The key point is to arbitrarily select one or more storage accesses from 32 positions of the four access queues for parallel processing, but the number of storage accesses selected at the same time is not greater than the logic of the shared memory. number of blocks. In the embodiment of the present invention, it is sufficient that the selected number of storage accesses does not exceed 4 (the total number of interfaces).
步骤803：共享存储访问交换管理单元的并行译码模块将所选定的无冲突存储访问并行译码，并送给各自对应的Bank；Step 803: The parallel decoding module of the shared storage access exchange management unit decodes the selected non-conflicting storage accesses in parallel, and sends them to the corresponding Banks;
步骤804：传输状态更新模块基于各个存储访问的ID，更新其传输状态(传输进度)，如果刚好完成传输则通知访问接口将该存储访问从访问队列中移除。Step 804: The transfer status update module updates the transfer status (transfer progress) of each storage access based on the ID, and notifies the access interface to remove the storage access from the access queue if the transfer is just completed.
步骤805：共享存储访问交换管理单元的接口选择模块为每个需要返回的反馈数据选择通过的访问接口。Step 805: The interface selection module of the shared storage access exchange management unit selects an access interface for each feedback data that needs to be returned.
这里，对于每个需要返回的反馈数据，选择任意一个访问接口作为其通过接口。优先选择反馈数据对应的访问接口作为通过接口，对于存在接口冲突的其他反馈数据，可以选择任意一个不需要返回数据的访问接口作为通过接口。接口选择策略可以灵活设置，本发明实施例不做限制。Here, for each feedback data that needs to be returned, any access interface is selected as its passing interface. The access interface corresponding to the feedback data is preferentially selected as the passing interface. For other feedback data with interface conflicts, any access interface that does not need to return data can be selected as the passing interface. The interface selection policy can be set flexibly, which is not limited in this embodiment of the present invention.
步骤806：共享存储访问交换管理单元的接口选择模块将反馈数据及其伴随信息送给访问接口；Step 806: The interface selection module of the shared storage access exchange management unit sends the feedback data and its accompanying information to the access interface;
其中，伴随信息主要包括反馈数据所对应的存储访问的ID、以及反馈数据所要走的访问接口即通过接口的标识。Wherein, the accompanying information mainly includes the storage access ID corresponding to the feedback data, and the access interface through which the feedback data goes, that is, the identifier of the access interface.
步骤807：访问接口接收反馈数据以及其伴随信息，按照伴随信息将反馈数据通过共享总线返回给访问源。Step 807: The access interface receives the feedback data and its accompanying information, and returns the feedback data to the access source through the shared bus according to the accompanying information.
其中，Slave0～Slave3中每个都根据反馈数据的伴随信息，选择是否接受所述反馈数据，如果伴随信息中通过接口的标识与自身标识相同，则接受，并根据伴随信息中存储访问的ID将所述反馈数据通过共享总线返回给对应的访问源；否则不接受反馈数据，也不进行后续的数据返回处理。Wherein, each of Slave0～Slave3 selects whether to accept the feedback data according to the accompanying information of the feedback data, if the identification of the interface through the accompanying information is the same as its own identification, then accept, and according to the ID stored and accessed in the accompanying information, The feedback data is returned to the corresponding access source through the shared bus; otherwise, the feedback data is not accepted, and subsequent data return processing is not performed.
对于不需要返回数据的访问，例如读访问，到步骤804即可结束流程；对需要返回反馈数据的访问，例如写访问，其流程到807结束。For an access that does not need to return data, such as a read access, the process ends at step 804 ; for an access that requires feedback data, such as a write access, the process ends at 807 .
以上步骤中，步骤802以及步骤805是共享存储访问带宽得以改善的主要原因；步骤801以及步骤807是对现有片内数据总线协议的改进创新和灵活应用，是该方法能够有效使用的辅助条件。Among the above steps, step 802 and step 805 are the main reasons for the improvement of the shared memory access bandwidth; step 801 and step 807 are the improvement innovation and flexible application of the existing on-chip data bus protocol, and are auxiliary conditions for the effective use of the method .
与现有的各种共享存储接口带宽的改善方法和装置相比，采用本发明所述的方法和装置，具有如下特点：Compared with the existing methods and devices for improving the bandwidth of various shared storage interfaces, the method and device of the present invention have the following characteristics:
1)在对各个接口的存储访问仲裁时，结合outstanding功能，乱序地调度和响应，最大限度的降低了多端口存储访问时的Bank冲突，提高了静态随机存储器(SRAM，StaticRAM)的入口和出口带宽。1) When arbitrating the memory access of each interface, combined with the outstanding function, the out-of-order scheduling and response minimizes the Bank conflict during multi-port memory access, and improves the access and access of static random access memory (SRAM, StaticRAM). Egress bandwidth.
2)在多个并发访问发生时，各个访问接口不是独立工作，而是统一管理队列资源，消除了有访问到来的访问接口队列满而其他访问接口有空余时不能接受新的访问所带来的带宽损失。2) When multiple concurrent accesses occur, each access interface does not work independently, but manages the queue resources in a unified manner, eliminating the problem that the access interface queue is full and other access interfaces cannot accept new access when there is vacancy loss of bandwidth.
3)在多个数据返回时，放弃原来从哪里来回哪里去的方式，返回数据可以走任何一个接口返回，控制走各个接口的返回时延一致，总线对返回数据是根据ID路由，这样不会有任何不良影响，从而充分利用了接口提供的出口带宽。3) When multiple data are returned, the original way of returning from where to where is abandoned, and the returned data can be returned through any interface, and the return delay of each interface is controlled to be consistent. The bus routes the returned data according to the ID, so that it will not There is no adverse effect, thus making full use of the egress bandwidth provided by the interface.
假设SRAM只有一个Block和一个访问接口，显然，这种方式与访问时的地址patter无关，假设单个接口的总线带宽为1(归一化单位)，则该方案下共享存储的访问带宽刚好为1。Suppose the SRAM has only one block and one access interface. Obviously, this method has nothing to do with the address pattern during access. Assuming that the bus bandwidth of a single interface is 1 (normalized unit), the access bandwidth of shared storage under this scheme is just 1 .
1)四个独立总线接口和四个独立的Block，使用普通方法的话，4个并发的访问源会出现如下几种情况：1) Four independent bus interfaces and four independent Blocks, if using the common method, the four concurrent access sources will appear as follows:
4个并发访问的地址正好落在四个不同的Block，带宽为4*1＝4。The addresses of the 4 concurrent accesses fall exactly in four different blocks, and the bandwidth is 4*1=4.
4个并发访问的地址落在了三个不同的Block，带宽为3*1＝3。The addresses of the 4 concurrent accesses fall into three different blocks, and the bandwidth is 3*1=3.
4个并发访问的地址落在了两个不同的Block，带宽为2*1＝2。The addresses of the 4 concurrent accesses fall into two different blocks, and the bandwidth is 2*1=2.
4个并发访问的地址落在了同一个Block，带宽为1。The addresses of 4 concurrent accesses fall into the same block, and the bandwidth is 1.
假设每个访问源的访问地址相互独立且访问地址平均分布，而总的访问情况的个数为：Assuming that the access addresses of each access source are independent of each other and the access addresses are evenly distributed, the total number of access situations is:
N＝44＝256＝N1+N2+N3+N4N=44 ＝256＝N1 +N2 +N3 +N4
4个并发访问的地址正好落在四个不同的Block的概率为：N4/N＝9.38％。The probability that 4 concurrently accessed addresses fall exactly in four different blocks is: N4/N=9.38%.
4个并发访问的地址落在了三个不同的Block的概率为：N3/N＝56.25％。The probability that 4 concurrently accessed addresses fall into three different blocks is: N3/N=56.25%.
4个并发访问的地址落在了两个不同的Block的概率为：N2/N＝32.81％。The probability that 4 concurrently accessed addresses fall into two different blocks is: N2/N=32.81%.
4个并发访问的地址落在了同一个Block的概率为：N1/N＝1.56％。The probability that 4 concurrently accessed addresses fall into the same block is: N1/N=1.56%.
这样该方案下的平均带宽为：B＝B1*P1+B2*P2+B2*P2+B2*P2＝4*9.38％+3*56.25％+2*32.81％+1*1.56％＝2.73。In this way, the average bandwidth under this scheme is: B=B1*P1+B2*P2+B2*P2+B2*P2=4*9.38%+3*56.25%+2*32.81%+1*1.56%=2.73.
2)使用本发明实施例提供的装置和方法，假设共享总线可以支持最多16个outstanding的无序功能，也就是每个访问源平均支持4个outstanding的无序功能；存储器分为4个逻辑独立的Block，每个Block分为地址交织的4个Bank。这个方案下，从16个ID中所选择的4个并发的访问源会出现如下几种情况：2) Using the device and method provided by the embodiments of the present invention, it is assumed that the shared bus can support up to 16 outstanding out-of-order functions, that is, each access source supports an average of four outstanding out-of-order functions; the memory is divided into four logically independent Each Block is divided into 4 Banks whose addresses are interleaved. Under this scheme, the four concurrent access sources selected from the 16 IDs will have the following situations:
4个并发访问的地址正好落在四个不同的Bank，带宽为4*1G＝4。The addresses of the 4 concurrent accesses just fall into four different banks, and the bandwidth is 4*1G=4.
4个并发访问的地址落在了三个不同的Bank，带宽为3*1＝3。The addresses of the 4 concurrent accesses fall into three different banks, and the bandwidth is 3*1=3.
4个并发访问的地址落在了两个不同的Bank，带宽为2*1＝2。The addresses of the 4 concurrent accesses fall into two different banks, and the bandwidth is 2*1=2.
4个并发访问的地址落在了同一个Bank，带宽为1。The addresses of 4 concurrent accesses fall into the same Bank, and the bandwidth is 1.
假设每个访问源的访问地址相互独立且访问地址平均分布，而总的访问情况的个数为：Assuming that the access addresses of each access source are independent of each other and the access addresses are evenly distributed, the total number of access situations is:
N＝N1+N2+N3+N4＝1616＝18446744073709551616N=N1 +N2 +N3 +N4 ＝1616 ＝18446744073709551616
N4＝N-N1-N2-N3＝18446744049705622576N4 =NN1 -N2 -N3 =18446744049705622576
4个并发访问的地址正好落在四个不同的block的概率为：N4/N＝99.99％。The probability that 4 concurrently accessed addresses fall into exactly 4 different blocks is: N4/N=99.99%.
4个并发访问的地址落在了三个不同的block的概率为：N3/N＝0.001％。The probability that 4 concurrently accessed addresses fall into three different blocks is: N3/N=0.001%.
4个并发访问的地址落在了两个不同的block的概率为：N2/N＝0.00％。The probability that 4 concurrently accessed addresses fall into two different blocks is: N2/N=0.00%.
4个并发访问的地址落在了同一个block的概率为：N1/N＝0.00。The probability that 4 concurrently accessed addresses fall into the same block is: N1/N=0.00.
这样该方案下的平均带宽为：B＝B1*P1+B2*P2+B2*P2+B2*P2＝4*99.99％+3*0.01％+2*0.00％+1*0.00％＝4。In this way, the average bandwidth under this solution is: B=B1*P1+B2*P2+B2*P2+B2*P2=4*99.99%+3*0.01%+2*0.00%+1*0.00%=4.
因此，和普通的四个独立总线接口配合四个独立的Block相对比，本发明实施例方法和装置所带来的收益，相比于普通的方法带宽提升46.5％。Therefore, compared with the common four independent bus interfaces with four independent Blocks, the benefits brought by the method and device of the embodiment of the present invention are 46.5% higher than the common method bandwidth.
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。Obviously, those skilled in the art should understand that each module or each step of the above-mentioned present invention can be realized by a general-purpose computing device, and they can be concentrated on a single computing device, or distributed in a network formed by multiple computing devices Alternatively, they may be implemented in program code executable by a computing device so that they may be stored in a storage device to be executed by a computing device, and in some cases, in an order different from that shown here The steps shown or described are carried out, or they are separately fabricated into individual integrated circuit modules, or multiple modules or steps among them are fabricated into a single integrated circuit module for implementation. As such, the present invention is not limited to any specific combination of hardware and software.
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.
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