Summary of the invention
Based on this, it is necessary to for the prior art limitation DRAM compatibility, be unfavorable for reduce electronic system exploitation atThis problem of, provides a kind of DRAM combination control method.
A kind of DRAM combination control method that purpose provides to realize the present invention, includes the following steps:
The DRAM according to needed for PCB, according to dram controller periphery height DQ group exchange connection circuit to a piece of DRAM intoRow setting, or multi-disc DRAM is combined；
According to the group of the set-up mode or multi-disc DRAM of the specification of one or more pieces DRAM and a piece of DRAMConjunction mode carries out signal source configuration to the first control terminal of the dram controller.
The height DQ group exchange connection circuit of the dram controller periphery includes the in one of the embodiments,One PCB encapsulation and the 2nd PCB encapsulation；
First PCB is encapsulated as double RANK settings, and the 2nd PCB is encapsulated as single RANK setting；
First chip selection signal end of the first PCB encapsulation is connect with the second control terminal of the dram controller；
Second chip selection signal end of the first PCB encapsulation and the chip selection signal end of the 2nd PCB encapsulation, with it is describedFirst control terminal of dram controller connects；
The high-order input terminal of first PCB encapsulation and the low level input terminal of the 2nd PCB encapsulation, with the DRAMFirst output end of controller connects；
The low level input terminal of first PCB encapsulation and the high-order input terminal of the 2nd PCB encapsulation, with the DRAMThe second output terminal of controller connects.
Multiple selector is set inside the dram controller in one of the embodiments,；
The first input end of the multiple selector is connect with the first internal signal sources of the dram controller；It is described moreSecond input terminal of road selector is connect with the second internal signal sources of the dram controller；
The output end of the multiple selector is connect with the first control terminal of the dram controller, passes through control multichannel choosingIt selects device and signal source configuration is carried out to the first control terminal of the dram controller；
The signal source of second control terminal of the dram controller is first internal signal sources.
The specification of the DRAM needed for the PCB in one of the embodiments, are as follows: data bit width A is pressed when capacity is BConnection circuit is exchanged according to the height DQ group, is A by data bit width, a piece of DRAM that capacity B, RANK quantity is 2 is placed onThe first PCB encapsulation；
It controls the multiple selector and configures described second for the signal source of the first control terminal of the dram controllerInternal signal sources.
The specification of the DRAM needed for the PCB in one of the embodiments, are as follows: data bit width A is pressed when capacity is BConnection circuit is exchanged according to the height DQ group, is A by data bit width, a piece of DRAM that capacity B, RANK quantity is 1 is placed onThe first PCB encapsulation；
It controls the multiple selector and configures described first for the signal source of the first control terminal of the dram controllerInternal signal sources or second internal signal sources, or close the first control terminal of the dram controller.
The specification of the DRAM needed for the PCB in one of the embodiments, are as follows: data bit width A is pressed when capacity is BConnection circuit is exchanged according to the height DQ group, is A by data bit width, a piece of DRAM that capacity B, RANK quantity is 1 is placed onThe 2nd PCB encapsulation；
It controls the multiple selector and configures described first for the signal source of the first control terminal of the dram controllerInternal signal sources.
The specification of the DRAM needed for the PCB in one of the embodiments, are as follows: data bit width A is pressed when capacity is BConnection circuit is exchanged according to the height DQ group, is A by data bit width, the two panels DRAM that capacity C, RANK quantity is 1 is put respectivelyIt sets in the first PCB encapsulation and the 2nd PCB encapsulation；
It controls the multiple selector and configures described second for the signal source of the first control terminal of the dram controllerInternal signal sources；
Wherein, the C is equal to the half of the B.
The specification of the DRAM needed for the PCB in one of the embodiments, are as follows: data bit width A is pressed when capacity is BConnection circuit is exchanged according to the height DQ group, is D by data bit width, the two panels DRAM that capacity C, RANK quantity is 1 is put respectivelySet the low level in the first PCB encapsulation and the low level of the 2nd PCB encapsulation；
It controls the multiple selector and configures described first for the signal source of the first control terminal of the dram controllerInternal signal sources；
Wherein, the D is equal to the half of the A；The C is equal to the half of the B.
The value of the A in one of the embodiments, are as follows: 8 bits, 16 bits or 32 bits；The value of the B is256MB, 512MB, 1GB or 2GB.
The DRAM is DDR1, DDR2, DDR3, LPDDR2 or LPDDR3 in one of the embodiments,.
Above-mentioned DRAM combination control method the utility model has the advantages that DRAM combination control method design first dram controller peripheryConnection circuit be height DQ group exchange connection circuit, by DRAM needed for PCB, connected according to the height DQ group exchange of design electricRoad is configured a piece of DRAM, or is combined to multi-disc DRAM.When according to height DQ group exchange connection type to a piece of orAfter multi-disc DRAM is combined, according to the set-up mode of the specification of one or more pieces DRAM of selection and a piece of DRAM or moreThe combination of piece DRAM carries out signal source configuration to the first control terminal of dram controller, so that the DRAM after combination meetsThe specification of required DRAM.Finally realize the purpose that the DRAM of a variety of different sizes can be compatible on same PCB.AndAnd different DRAM can be selected for same PCB according to the market price, it is reduced costs in the selection of DRAM, effectivelyIt solves the compatibility of prior art limitation DRAM, is unfavorable for the problem of reducing the development cost of electronic system.
Specific embodiment
To keep technical solution of the present invention clearer, the present invention is done further in detail below in conjunction with drawings and the specific embodimentsIt describes in detail bright.
Include the following steps: referring to Fig. 1 as the DRAM combination control method of a specific embodiment
Step S100, the DRAM according to needed for PCB, according to the height DQ group exchange connection circuit of dram controller periphery to onePiece DRAM is configured, or is combined to multi-disc DRAM.
Step S200, according to the set-up mode or multi-disc DRAM of the specification of one or more pieces DRAM and a piece of DRAMCombination carries out signal source configuration to the first control terminal of dram controller.
Its connection circuit for passing through design dram controller periphery first is height DQ group exchange connection circuit, realizes basisDRAM needed for PCB is combined one or more pieces DRAM according to the height DQ group exchange connection circuit of design.
After being combined according to height DQ group exchange connection type to one or more pieces DRAM, according to one or more piecesThe combination of the specification of DRAM and one or more pieces DRAM carries out signal source to the first control terminal of dram controller and matchesIt sets.So that combination after DRAM meet needed for DRAM specification, finally realize can be compatible on same PCB it is a variety of notThe DRAM of same specification.Achieve the purpose that select different DRAM for same PCB according to the market price.Its selection in DRAMOn reduce costs, efficiently solve the compatibility of prior art limitation DRAM, be unfavorable for reducing the cost of electronic systemProblem.
It should be noted that the first control terminal of dram controller include three control ports, respectively CS1,ODT1 and CKE1.Wherein, CS1 is piece choosing, and it is enabled that ODT1 is that on piece is cut off, and CKE1 is enabled for clock.The first of dram controllerControl terminal is denoted as CS1/CKE1/ODT1.
Referring to fig. 2, as an embodiment, the height DQ group exchange connection circuit of dram controller periphery includes theOne PCB encapsulates U1 and the 2nd PCB and encapsulates U2.
It should be noted that the RANK quantity of the first PCB encapsulation U1 is 2, i.e. it is double RANK settings that the first PCB, which encapsulates U1,.The RANK quantity that 2nd PCB encapsulates U2 is 1, i.e. the 2nd PCB encapsulates U2 as list RANK setting.
Since the first PCB encapsulation U1 is double RANK settings, the first PCB encapsulates chip selection signal end there are two U1 settings,Respectively the first chip selection signal end CS0 and the second chip selection signal end CS1.And the 2nd PCB encapsulation U2 is list RANK setting, therefore theA chip selection signal end CS0 is only arranged in two PCB encapsulation U2.
Wherein, the first PCB encapsulates the first chip selection signal end CS0 of U1 and the second control terminal CS0/ of dram controllerCKE0/ODT0 connection.
First PCB encapsulate U1 the second chip selection signal end CS1 and the 2nd PCB encapsulation U2 chip selection signal end CS0, withFirst control terminal CS1/CKE1/ODT1 connection of dram controller.
Meanwhile the first PCB encapsulation U1 high-order input terminal and the 2nd PCB encapsulation U2 low level input terminal, with DRAM controlFirst output end DQH connection of device processed.First PCB encapsulates the low level input terminal of U1 and the high-order input terminal of the 2nd PCB encapsulation U2,It is connect with the second output terminal DQL of dram controller.
First output end DQH of dram controller is as data high position output end, the second output terminal DQL of dram controllerAs data low level output end.Data high position output end by the way that dram controller is arranged encapsulates the height of U1 with the first PCB respectivelyThe low level input terminal connection of position input terminal and the 2nd PCB encapsulation U2, the data low level output end of dram controller is respectively with firstPCB encapsulates the high-order input terminal connection of the low level input terminal and the 2nd PCB encapsulation U2 of U1, forms height DQ group interactive connection sideFormula.
In the present embodiment, it is 16 bits (bit) as the first PCB using data bit width and encapsulates U1 and the 2nd PCB encapsulation U2A high position；It is that 8 bits encapsulate the low level that U1 and the 2nd PCB encapsulates U2 as the first PCB using data bit width.
It should be noted that it is 32 that a high position of the first PCB encapsulation U1 and the 2nd PCB encapsulation U2, which may be alternatively provided as data bit width,Bit, it is 16 bits that the low level of the first PCB encapsulation U1 and the 2nd PCB encapsulation U2, which is set as data bit width,.
Wherein, the first PCB encapsulates a high position of U1 and the 2nd PCB encapsulation U2 and low level and can be configured according to the actual situation,It is not limited to the above-mentioned set-up mode being previously mentioned.
Referring to Fig. 3, after being combined according to height DQ group exchange connection type to one or more pieces DRAM, according to DRAMCombination can be more by controlling when carrying out signal source configuration to the first control terminal CS1/CKE1/ODT1 of dram controllerRoad selector is realized.It is specific:
By the way that multiple selector, the first input end and dram controller of multiple selector are arranged inside dram controllerThe first internal signal sources CS0_i/CKE0_i/ODT0_i connection；Second input terminal of multiple selector and dram controllerSecond internal signal sources CS1_i/CKE1_i/ODT1_i connection.
Meanwhile the first control terminal CS1/CKE1/ODT1 connection of the output end and dram controller of multiple selector.Pass throughUsing the value of programming language (such as: C language) modification dram controller register, the dynamic of modification dram controller register is realizedMake, and then realizes the purpose of control multiple selector.To the first control by control multiple selector to dram controllerCS1/CKE1/ODT1 is held to carry out signal source configuration.
Wherein, the second control terminal CS0/CKE0/ODT0 of dram controller directly believes with the first inside of dram controllerNumber source CS0_i/CKE0_i/ODT0_i connection, thus by the signal source of the second control terminal CS0/CKE0/ODT0 of dram controllerIt is configured to the first internal signal sources CS0_i/CKE0_i/ODT0_i.
Above-mentioned multiple selector is set inside dram controller, by control multiple selector to the of dram controllerOne control terminal CS1/CKE1/ODT1 carries out signal source configuration, thus according to the first control terminal CS1/CKE1/ of dram controllerWhether the signal source of the second control terminal CS0/CKE0/ODT0 of the signal source and dram controller of ODT1 is identical, to determine outsideThe RANK quantity that DRAM is used.
Such as: controllable multi-route selector configures the signal source of the first control terminal CS1/CKE1/ODT1 of dram controllerFor the first internal signal sources CS0_i/CKE0_i/ODT0_i.At this point, due to the second control terminal CSO/CKE0/ of dram controllerThe signal source of ODT0 is similarly the first internal signal sources CS0_i/CKE0_i/ODT0_i, therefore, the first control of dram controllerThe signal source of the signal source and the second control terminal CS0/CKE0/ODT0 of holding CS1/CKE1/ODT1 is same configuration.Thus connect respectivelyIt is connected to the DRAM of the first control terminal CS1/CKE1/ODT1 of dram controller and is connected to the second control terminal of dram controllerThe signal that the DRAM of CS0/CKE0/ODT0 is received is just the same, then is single RANK application, i.e., the RANK number that external DRAM is usedAmount is 1.
When control multiple selector configures for the signal source of the first control terminal CS1/CKE1/ODT1 of dram controllerTwo internal signal sources CS1_i/CKE1_i/ODT1_i, and the signal source of the second control terminal CS0/CKE0/ODT0 of dram controllerIt is then the first internal signal sources CS0_i/CKE0_i/ODT0_i.Therefore, the first control terminal CS1/CKE1/ of dram controllerThe signal source of ODT1 and the signal source of the second control terminal CS0/CKE0/ODT0 are different configurations.Thus it is connected respectively to DRAM controlThe DRAM of first control terminal CS1/CKE1/ODT1 of device processed and the second control terminal CS0/CKE0/ for being connected to dram controllerThe signal that the DRAM of ODT0 is received is unlike signal, then is double RANK application, i.e., the RANK quantity that external DRAM is used is 2.
It should be noted that DRAM can be DDR1, DDR2, DDR3, LPDDR2 (Low Power Double Date) and LPDDR3 (Low Power Double Date Rate3) etc. Rate2.Wherein:
The type of DRAM mentioned herein is DDR1, DDR2, DDR3, LPDDR2 or LPDDR3 etc. only as of the inventionSome preferred embodiments, but be not restricted to that above-mentioned five seed types being previously mentioned.Its other types for being equally applicable to DRAM.
Also, the specification of DRAM includes the RANK quantity of the data bit width of DRAM, the capacity of DRAM and DRAM.Wherein:
The value of the data bit width A of DRAM can be 8 bits, 16 bits or 32 bits.Equally, the data bit width of DRAM is also simultaneouslyIt is not limited to three kinds of data bit widths noted earlier.
The capacity B of DRAM can be 256MB, 512MB, 1GB or 2GB.Similarly, the capacity B of DRAM be 256MB, 512MB,1GB or 2GB is not limited to these examples also only as some preferred embodiments of the invention.
The RANK quantity of DRAM can be 1 or 2.
A piece of DRAM is configured when the height DQ group exchange according to dram controller periphery connects circuit, or to multi-discAfter DRAM is combined, according to the group of the set-up mode or multi-disc DRAM of the specification of one or more pieces DRAM and a piece of DRAMConjunction mode, when carrying out signal source configuration to the first control terminal CS1/CKE1/ODT1 of dram controller, detailed process are as follows:
The specification of the DRAM needed for PCB operation is that data bit width is A, set according to the present invention when capacity is the DRAM of BThe height DQ group exchange connection circuit and dram controller built-in function principle of the dram controller periphery of meter, on same PCBFace can be compatible with following several application schemes simultaneously:
One, a piece of double RANK data bit widths are the DRAM that A (XA) capacity is B.
Two, a piece of list RANK data bit width is the DRAM that A (XA) capacity is B.
Three, two panels list RANK data bit width is the DRAM that A (XA) capacity is C.
Four, two panels list RANK data bit width is the DRAM that D (XD) capacity is C.
Wherein, D is equal to the half of A；C is equal to the half of B.
When selecting the first application scheme, connection circuit is exchanged according to height DQ group, is A by data bit width, capacity isThe a piece of DRAM that B, RANK quantity are 2 is placed on the first PCB encapsulation.
Meanwhile it controlling multiple selector and configuring the second internal signal for the signal source of the first control terminal of dram controllerSource.
When selecting second of application scheme, two kinds of settings can be carried out: a kind of are as follows: exchange connection electricity according to height DQ groupRoad, is A by data bit width, and a piece of DRAM that capacity B, RANK quantity is 1 is placed on the first PCB encapsulation.
Meanwhile it controlling multiple selector and configuring the first internal signal for the signal source of the first control terminal of dram controllerSource or the second internal signal sources, or close the first control terminal of dram controller.
It is another are as follows: to exchange connection circuit according to height DQ group, be A by data bit width, capacity B, RANK quantity is 1A piece of DRAM is placed on the 2nd PCB encapsulation.
Meanwhile it controlling multiple selector and configuring the first internal signal for the signal source of the first control terminal of dram controllerSource.
When selecting the third application scheme, connection circuit is exchanged according to height DQ group, is A by data bit width, capacity isThe two panels DRAM that C, RANK quantity are 1 is individually positioned in the first PCB encapsulation and the 2nd PCB encapsulation.
Meanwhile it controlling multiple selector and configuring the second internal signal for the signal source of the first control terminal of dram controllerSource.
When selecting the 4th kind of application scheme, connection circuit is exchanged according to height DQ group, is D by data bit width, capacity isThe two panels DRAM that C, RANK quantity are 1 is individually positioned in the low level of the first PCB encapsulation and the low level of the 2nd PCB encapsulation.
Meanwhile it controlling multiple selector and configuring the first internal signal for the signal source of the first control terminal of dram controllerSource
Specifically, take data bit width as 16 bits of the specification of DRAM needed for PCB operation, for capacity is the DDR3 of 1GB,Further detailed description is done to DRAM combination control method.
The specification of the DRAM needed for PCB operation is that data bit width is 16 bits, when capacity is the DDR3 of 1GB, according to thisThe height DQ group exchange connection circuit and dram controller built-in function principle of the designed dram controller periphery of invention, sameAbove one PCB, it can be compatible with following several application schemes simultaneously:
One, a piece of double RANK data bit widths are the DDR3 that 16 bits (X16) capacity is 1GB.
Two, a piece of list RANK data bit width is the DDR3 that 16 bits (X16) capacity is 1GB.
Three, two panels list RANK data bit width is the DDR3 that 16 bits (X16) capacity is 512MB.
Four, two panels list RANK data bit width is the DDR3 that 8 bits (X8) capacity is 512MB.
When selecting the first application scheme, that is, select data bit width for 16 bits, capacity 1GB, RANK quantity is 2When a piece of DDR3, connection circuit is exchanged according to height DQ group, which is placed on the first PCB encapsulation U1.
Meanwhile by controlling multiple selector for the signal source of the first control terminal CS1/CKE1/ODT1 of dram controllerIt is configured to the second internal signal sources CS1_i/CKE1_i/ODT1_i.Pass through the first control terminal CS1/CKE1/ of dram controllerODT1 configures the second internal signal sources CS1_i/CKE1_i/ODT1_i, the second control terminal CS0/CKE0/ODT0 of dram controllerSignal source be the first internal signal sources CS0_i/CKE0_i/ODT0_i, realize that two groups of signals control the height of the DDR3 respectivelyRANK and low RANK, to realize the transmission of data.
When selecting second of application scheme, that is, select data bit width for 16 bits, capacity 1GB, RANK quantity is 1When a piece of DDR3, connection circuit is exchanged according to height DQ group, which is placed on the first PCB encapsulation U1 or the 2nd PCB and is encapsulatedU2.
When the DDR3 is placed on the first PCB encapsulation U1, since the RANK quantity of the first PCB encapsulation U1 is 2,It controls multiple selector and configures the first internal signal for the signal source of the first control terminal CS1/CKE1/ODT1 of dram controllerSource CS0_i/CKE0_i/ODT0_i or the second internal signal sources CS1_i/CKE1_i/ODT1_i, or directly close DRAMFirst control terminal CS1/CKE1/ODT1 of controller.
When the DDR3 is placed on the 2nd PCB encapsulation U2, since the RANK quantity of the 2nd PCB encapsulation U2 is 1.Therefore,With the signal of the first control terminal CS1/CKE1/ODT1 of the chip selection signal end CS0 of the 2nd PCB encapsulation U2 dram controller connectingSource should be configured to the first internal signal sources CS0_i/CKE0_i/ODT0_i, and the 2nd PCB encapsulation U2 could be made effective.To makeObtain the specification of DRAM needed for can satisfy PCB operation when DDR3 is placed on a high position of the 2nd PCB encapsulation U2.Therefore, pass throughSoftware programming, control multiple selector configure for the signal source of the first control terminal CS1/CKE1/ODT1 of dram controllerOne internal signal sources CS0_i/CKE0_i/ODT0_i.
When since the DDR3 being placed on the 2nd PCB encapsulation U2, it is necessary to be to the first control terminal of dram controllerThe signal source of CS1/CKE1/ODT1 configured, and when the DDR3 is placed on the first PCB encapsulation U1, then dram controllerFirst control terminal CS1/CKE1/ODT1 can be without any processing, therefore the DDR3 is preferably placed on the first PCB encapsulation U1,It is 16 bits by data bit width, a piece of DRAM that capacity 1GB, RANK quantity is 1 is placed on the first PCB encapsulation.
When selecting the third application scheme, that is, select data bit width for 16 bits, capacity 512MB, RANK quantity is 1Two panels DDR3 when, respectively by two panels DDR3 be placed on the first PCB encapsulation U1 and the 2nd PCB encapsulation U2 on.Due in the program,First PCB encapsulation U1 and the 2nd PCB encapsulation U2 high-low-position all can use arrive, and the first PCB encapsulation U1 and the 2nd PCB encapsulation U2High-low-position there is the phenomenon that being connected to identical one group of signal, that is, being connected to the same output end of dram controller.
Such as: a high position of the first PCB encapsulation U1 and the low level of the 2nd PCB encapsulation U2 are connected to the first defeated of dram controllerOn outlet DQH.If the first PCB encapsulates U1 and the 2nd PCB encapsulation, U2 is effective simultaneously, inherently generates data collision.Therefore,It needs through the first internal signal sources CS0_i/CKE0_i/ODT0_i and the second internal signal sources CS1_i/CKE1_i/ODT1_iTwo groups of signals, the first PCB of timesharing independent control encapsulate U1 and the 2nd PCB and encapsulate U2.
Again since the signal source of the second control terminal CS0/CKE0/ODT0 of dram controller is configured to the first internal signal sourcesCS0_i/CKE0_i/ODT0_i, therefore, by controlling multiple selector for the first control terminal CS1/CKE1/ of dram controllerThe signal source of ODT1 is configured to the second internal signal sources CS1_i/CKE1_i/ODT1_i, to realize the first of dram controllerThe 2nd PCB of the second control terminal CS0/CKE0/ODT0 timesharing independent control of control terminal CS1/CKE1/ODT1 and dram controller envelopeIt fills U2 and the first PCB and encapsulates U1.
When selecting the 4th kind of application scheme, that is, select data bit width for 8 bits, capacity 512MB, RANK quantity is 1Two panels DDR3 when, respectively by two panels DDR3 be placed on the first PCB encapsulation U1 low level and the 2nd PCB encapsulation U2 low level.TogetherWhen, control multiple selector configures the signal source of the first control terminal CS1/CKE1/ODT1 of dram controller to inside firstSignal source CS0_i/CKE0_i/ODT0_i.
By configuring the first internal signal sources for the signal source of the first control terminal CS1/CKE1/ODT1 of dram controllerCS0_i/CKE0_i/ODT0_i, controlling the 2nd PCB encapsulation U2 by the first control terminal CS1/CKE1/ODT1 of dram controller hasEffect.Meanwhile it is effective simultaneously by the second control terminal CS0/CKE0/ODT0 of dram controller control the first PCB encapsulation U1.And then it is realShow the first output end DQH and second output terminal DQL of dram controller while being encapsulated at the low level of U2 to the 2nd PCB is placed onThe DDR3 and DDR3 being placed at the low level of the first PCB encapsulation U1 carries out the transmission of data, and data bit width needed for meeting PCB is16 bits, capacity are the requirement of the DRAM of 1GB.
In conclusion the DRAM combination control method as a specific embodiment, passes through design dram controller peripheryConnect circuit be height DQ group connect circuit, simultaneously for dram controller inside setting multiple selector, realize forThe specification of DRAM needed for same PCB can be combined by the DRAM of a variety of different sizes, to meet the requirement of PCB.It reachesAny hardware modifications, the purpose of compatible a variety of different DRAM combinations can not be done on same PCB by having arrived.Most final declineThe low development cost of electronic system.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneouslyLimitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the artFor, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the inventionProtect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.