A kind of communication data deinterleaving apparatus and de-interlacing methodTechnical field
The present invention relates to a kind of Data Handling Equipment And Method, particularly a kind of deinterleaving apparatus of data and method thereof.
Background technology
Communication data can be carried out interlace operation in the modulation process of transmitting of communication data, data interlacing can ensure the maximization of data restorability while ensureing the possibility reduction that transfer of data is made mistakes.Data interlacing is exactly data arrangement become different orders to transmit, and data being deinterleaved after the other side receives data reverts to original order.
Existing data de-interlacing method is with two the same memories, reads the data in first memory successively and it is put on a position of second memory, will take the identical internal memory of two capacity like this, occupy more resource.
Summary of the invention
Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides and a kind ofly take less resource and just can realize the apparatus and method that communication data deinterleaves.
Technical scheme: for achieving the above object, a kind of communication data deinterleaving apparatus of the present invention comprises CPU, register and two memories, the data capacity of described two memories is identical, wherein first memory is used for storing communication data, second memory is used for storage state flags position, the Status Flag bit flag in described second memory be the reading state of data that in first memory, correspondence position stores.
Described state flag bit is 1 bit character, and namely comprise 0 and 1 two states, wherein 0 mark is not read state, and 1 mark is read state.
Based on a de-interlacing method for above-mentioned communication data deinterleaving apparatus, the concrete steps deinterleaved are:
Step 1: described CPU reads the data in described second memory successively, finds out the position that first is the data of 0, and the data of the correspondence position in described first memory is saved in register, and change this state flag bit into 1 simultaneously;
Step 2: according to the algorithm that deinterleaves, described CPU judges that in now memory, data should write the position in first memory, and data in position in the first memory that should write and the data displacement position in now register, and the state flag bit in second memory corresponding to position in the first memory that should write changes 1 into;
Step 3: the like, repeat the processing method of step 2, until data all in second memory all become 1, then the data in first memory become the order after deinterleaving from the order before deinterleaving.
Beneficial effect: the present invention adopts the reading state of the communication data of each data bit in Data Labels bit flag first memory to achieve and adopts small one and large one two memories to realize communication data and deinterleave, economize on resources, reduce costs, and efficiency is also higher.
Accompanying drawing explanation
Accompanying drawing 1 is the schematic diagram of communication data deinterleaving apparatus.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Communication data deinterleaving apparatus as shown in Figure 1 comprises CPU, register and two memories, the data capacity of described two memories is identical, wherein first memory is used for storing communication data, second memory is used for storage state flags position, the Status Flag bit flag in described second memory be the reading state of data that in first memory, correspondence position stores.
Described state flag bit is 1 bit character, and namely comprise 0 and 1 two states, wherein 0 mark is not read state, and 1 mark is read state.
Based on a de-interlacing method for above-mentioned communication data deinterleaving apparatus, the concrete steps deinterleaved are:
Step 1: described CPU reads the data in described second memory successively, finds out the position that first is the data of 0, and the data of the correspondence position in described first memory is saved in register, and change this state flag bit into 1 simultaneously;
Step 2: according to the algorithm that deinterleaves, described CPU judges that in now memory, data should write the position in first memory, and data in position in the first memory that should write and the data displacement position in now register, and the state flag bit in second memory corresponding to position in the first memory that should write changes 1 into;
Step 3: the like, repeat the processing method of step 2, until data all in second memory all become 1, then the data in first memory become the order after deinterleaving from the order before deinterleaving.
As in accompanying drawing 1, data ABCDEF ... N becomes ECABFD after interweaving ... N, it is 0 that CPU reads S1 data bits certificate in second memory, then the data E of K1 data bit in first memory is extracted register, judge that it should in K5 data bit, then the data F in K5 data bit and the data E in register is exchanged, change the data of the state flag bit S5 data bit in the second corresponding for K5 data bit register into 1 simultaneously; Judge the data bit that now data F should be residing again, the like exchange, until until data all in second memory all become 1, then the data in first memory become the order after deinterleaving from the order before deinterleaving.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.