技术领域technical field
本发明涉及液晶显示领域，特别是涉及一种氧化物薄膜晶体管及其制作方法。The invention relates to the field of liquid crystal display, in particular to an oxide thin film transistor and a manufacturing method thereof.
背景技术Background technique
伴随着液晶LCD以及有机发光二极管OLED为代表的平板显示器向着大尺寸、高分辨率的方向发展，薄膜晶体管TFT作为平板显示行业的核心部件，也得到广泛的关注。现有技术中常用的薄膜晶体管包括非晶硅薄膜晶体管以及氧化物薄膜晶体管，由于氧化物薄膜晶体管具有载流子迁移率高的优势，在导入时无需大幅改变现有的液晶面板生产线等优势，而得到了广泛应用。With the development of flat panel displays represented by liquid crystal LCDs and organic light emitting diodes (OLEDs) toward large size and high resolution, thin-film transistors (TFTs), as the core components of the flat panel display industry, have also received widespread attention. Commonly used thin film transistors in the prior art include amorphous silicon thin film transistors and oxide thin film transistors. Oxide thin film transistors have the advantages of high carrier mobility, and there is no need to greatly change the existing liquid crystal panel production lines when they are introduced. And has been widely used.
现有技术在制作TFT的过程中时，尤其是在制作底栅极和顶接触结构的TFT时，一般是在玻璃基板上形成栅极以后，再在栅极上覆盖栅极绝缘层，由于栅极的存在，相应的在覆盖栅极绝缘层时就会在栅极的位置出现起伏状，再在形成有缘层时，该起伏位置将依然存在。由于源级和漏极是设置在有缘层的上方，因此，在为源级和漏极走线时，就会出现走线爬坡的问题，如图1所示，其中，要爬坡的高度为栅极金属层的厚度102以及有缘层104的厚度之和。由于在TFT实际制作过程中，由于解析度、开口率以及阻容延时等因素的影响，通常根据需要都会将漏极和源级漏极做的很窄，并且TFT本身的厚度也很薄，在爬坡过程中，由于台阶覆盖率以及湿刻等问题，常常会造成短路，极大的影响了TFT在生产过程中的良率以及质量。In the prior art, in the process of making TFTs, especially when making TFTs with a bottom gate and a top contact structure, generally after forming a gate on a glass substrate, a gate insulating layer is covered on the gate. Correspondingly, when the gate insulating layer is covered, undulations will appear at the position of the gate, and when the insulating layer is formed, the undulations will still exist. Since the source and drain are arranged above the active layer, when wiring the source and drain, there will be a problem of climbing the line, as shown in Figure 1, where the height to be climbed is the sum of the thickness 102 of the gate metal layer and the thickness of the active layer 104 . In the actual production process of TFT, due to the influence of factors such as resolution, aperture ratio and resistance-capacitance delay, the drain and source-drain are usually made very narrow according to needs, and the thickness of the TFT itself is also very thin. During the climbing process, due to problems such as step coverage and wet etching, short circuits are often caused, which greatly affects the yield and quality of TFT in the production process.
现有技术中，为了克服上述问题，一般是采用增加源级和漏极线的宽度，且数据线通过两条路径与源级和漏极连接，但是这种情况下，阻容延时以及其他参数都会相应的增大，不仅限制了分辨率的提高，也降低了开口率。In the prior art, in order to overcome the above problems, it is generally used to increase the width of the source and drain lines, and the data lines are connected to the source and drain through two paths, but in this case, the RC delay and other The parameters will increase accordingly, which not only limits the improvement of resolution, but also reduces the aperture ratio.
发明内容Contents of the invention
本发明主要解决的技术问题是提供一种氧化物薄膜晶体管及其制作方法，能够在不降低薄膜晶体管分辨率和开口率前提下，有效消除源级和漏极断线的风险。The technical problem mainly solved by the present invention is to provide an oxide thin film transistor and its manufacturing method, which can effectively eliminate the risk of source and drain disconnection without reducing the resolution and aperture ratio of the thin film transistor.
为解决上述技术问题，本发明采用的一个技术方案是：提供一种氧化物薄膜晶体管的制作方法，In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a method for manufacturing an oxide thin film transistor,
在第一基板上依次形成栅极以及栅极绝缘层；sequentially forming a gate and a gate insulating layer on the first substrate;
对所述栅极绝缘层的凸起部位进行刻蚀，形成一凹陷区域；Etching the raised portion of the gate insulating layer to form a recessed area;
在所述凹陷区域形成有缘层；forming an active layer in the recessed region;
在所述有缘层上形成一漏极和一源级，且所述源级和所述漏极以一沟道分开以暴露部分所述有缘层。A drain and a source are formed on the active layer, and the source and the drain are separated by a channel to expose part of the active layer.
其中，所述有缘层的厚度等于所述凹陷区域的深度。Wherein, the thickness of the active layer is equal to the depth of the recessed region.
其中，所述在所述凹陷区域形成有缘层的步骤具体包括：Wherein, the step of forming an edged layer in the recessed region specifically includes:
在所述凹陷区域通过化学沉积非晶硅形成所述有缘层。The active layer is formed by chemically depositing amorphous silicon in the recessed area.
其中，所述氧化物薄膜晶体管为低栅极和顶接触结构。Wherein, the oxide thin film transistor has a low gate and top contact structure.
其中，所述在所述有缘层上形成一漏极和一源级，且所述源级和所述漏极以一沟道分开以暴露部分所述有缘层的步骤之后还包括：Wherein, after the step of forming a drain and a source on the active layer, and the source and the drain are separated by a channel to expose a part of the active layer, it further includes:
在所述氧化物薄膜晶体管的表面沉积钝化层；Depositing a passivation layer on the surface of the oxide thin film transistor;
在所述绝缘钝化层上刻蚀形成接触通孔；并刻蚀所述接触通孔形成接触电极。etching on the insulating passivation layer to form a contact hole; and etching the contact hole to form a contact electrode.
其中，所述在第一基板上依次形成栅极以及栅极绝缘层步骤具体包括：Wherein, the step of sequentially forming the gate and the gate insulating layer on the first substrate specifically includes:
在所述第一基板上沉积金属膜层，经过曝光，刻蚀形成所述栅极；Depositing a metal film layer on the first substrate, exposing and etching to form the gate;
在所述栅极以及所述第一基板上沉积所述栅极绝缘层。The gate insulating layer is deposited on the gate and the first substrate.
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种氧化物薄膜晶体管，包括第一基板，设置在所述第一基板上的栅极、设置在所述栅极上的栅极绝缘层凹陷区域内的有缘层；还包括位于所述有缘层上方，以一沟道分隔开并暴露部分所述有缘层的源极和漏极；所述凹陷区域为蚀刻所述栅极绝缘凸起部位形成的区域。In order to solve the above technical problems, another technical solution adopted by the present invention is to provide an oxide thin film transistor, comprising a first substrate, a gate disposed on the first substrate, a gate disposed on the gate The active layer in the recessed region of the insulating layer; also includes a source and drain located above the active layer, separated by a channel and exposing part of the active layer; the recessed region is used to etch the gate The area where the insulating bumps are formed.
其中，所述有缘层的厚度等于所述凹陷区域的深度。Wherein, the thickness of the active layer is equal to the depth of the recessed region.
其中，所述有缘层是在所述凹陷区域通过化学沉积非晶硅形成的。Wherein, the active layer is formed by chemically depositing amorphous silicon in the recessed area.
其中，所述氧化物薄膜晶体管还包括覆盖在所述氧化物薄膜晶体管的表面沉积钝化层。Wherein, the oxide thin film transistor further includes depositing a passivation layer covering the surface of the oxide thin film transistor.
本发明的有益效果是：区别于现有技术的情况，本实施方式的氧化物薄膜晶体管的制作方法在第一基板上形成栅极以及栅极绝缘层以后，对栅极绝缘层凸起部位进行刻蚀，即在栅极绝缘层的表面形成一凹陷区域，能够有效消除栅极绝缘层表面的凸起部位，即消除栅极表面的阶梯爬坡；再在该凹陷区域形成有缘层，最后在有缘层上形成以一沟道分隔开且暴露部分有缘层的漏极和源级，能够使源级和漏极接近平滑的平铺在有缘层上，完全消除由于爬坡而导致的源级和漏极断线的风险。进一步提高氧化物薄膜晶体管的良率以及开口率，改善液晶显示产品的品质。The beneficial effects of the present invention are: different from the situation in the prior art, in the manufacturing method of the oxide thin film transistor of this embodiment, after the gate and the gate insulating layer are formed on the first substrate, the protruding part of the gate insulating layer is Etching, that is, forming a recessed area on the surface of the gate insulating layer, can effectively eliminate the raised parts on the surface of the gate insulating layer, that is, eliminate the step climbing on the surface of the gate; then form an insulating layer in the recessed area, and finally The drain and source are formed on the active layer separated by a trench and part of the active layer is exposed, so that the source and drain can be flattened on the active layer almost smoothly, completely eliminating the source level caused by the slope. and the risk of drain disconnection. Further improve the yield rate and aperture ratio of oxide thin film transistors, and improve the quality of liquid crystal display products.
附图说明Description of drawings
图1是现有技术氧化物薄膜晶体管一结构示意图；FIG. 1 is a schematic diagram of a structure of an oxide thin film transistor in the prior art;
图2是本发明氧化物薄膜晶体管制作方法一实施方式的流程示意；2 is a schematic flow chart of an embodiment of the method for manufacturing an oxide thin film transistor of the present invention;
图3是图2氧化物薄膜晶体管一具体实施方式的剖面结构示意图；3 is a schematic cross-sectional structure diagram of a specific embodiment of the oxide thin film transistor in FIG. 2;
图4是图2氧化物薄膜晶体管另一具体实施方式的剖面示意图；4 is a schematic cross-sectional view of another embodiment of the oxide thin film transistor in FIG. 2;
图5是图2氧化物薄膜晶体管再一实施方式的剖面示意图；5 is a schematic cross-sectional view of another embodiment of the oxide thin film transistor in FIG. 2;
图6是本发明氧化物薄膜晶体管制作方法另一实施方式的流程示意图；6 is a schematic flow diagram of another embodiment of the method for manufacturing an oxide thin film transistor of the present invention;
图7是本发明氧化物薄膜晶体管制作方法再一实施方式的流程示意图。FIG. 7 is a schematic flowchart of still another embodiment of the method for fabricating an oxide thin film transistor according to the present invention.
图8是本发明氧化物薄膜晶体管一实施方式的结构示意图；8 is a schematic structural view of an embodiment of an oxide thin film transistor of the present invention;
图9是本发明氧化物薄膜晶体管另一实施方式的结构示意图。FIG. 9 is a schematic structural diagram of another embodiment of the oxide thin film transistor of the present invention.
具体实施方式detailed description
参阅图2，图2是本发明氧化物薄膜晶体管的制作方法一实施方式的流程示意图。其中，本实施方式的薄膜晶体管为低栅极和顶接触结构形式的薄膜晶体管。具体地，本实施方式的制作方法包括以下步骤：Referring to FIG. 2 , FIG. 2 is a schematic flowchart of an embodiment of a method for fabricating an oxide thin film transistor according to the present invention. Wherein, the thin film transistor in this embodiment is a thin film transistor with a low gate and top contact structure. Specifically, the manufacturing method of this embodiment includes the following steps:
201：在第一基板上依次形成栅极以及栅极绝缘层。201: Form a gate and a gate insulating layer in sequence on a first substrate.
具体地，先在第一基板上通过沉积的方式形成金属膜层，经过一道光罩对金属膜层进行曝光，将金属膜层刻蚀成栅极。其中，第一道光罩为只能刻蚀一层的普通光罩。Specifically, firstly, a metal film layer is formed on the first substrate by way of deposition, and the metal film layer is exposed through a photomask, and the metal film layer is etched to form a gate. Among them, the first photomask is an ordinary photomask that can only etch one layer.
其中，第一基板包括玻璃基板以及石英基板，在其他实施方式中还可以为其他基板，在此不做限定。Wherein, the first substrate includes a glass substrate and a quartz substrate, and may also be other substrates in other implementation manners, which is not limited here.
金属膜层包括铝Al、钼Mo、铜Cu以及银Ag中的至少一种，在其他实施方式中也可以为其他金属，在此也不做限定。The metal film layer includes at least one of aluminum Al, molybdenum Mo, copper Cu, and silver Ag, and may be other metals in other embodiments, which is not limited here.
沉积工艺一般是指外来物质淀积于基底表面形成薄膜，又称为气相沉积。本实施方式是通过金属物质在第一基板的表面形成金属膜层。在其他实施方式中，也可以通过其他沉积方式来实现金属膜层，在此不作限定。The deposition process generally refers to the deposition of foreign substances on the surface of the substrate to form a thin film, also known as vapor deposition. In this embodiment, a metal film layer is formed on the surface of the first substrate by using a metal substance. In other implementation manners, the metal film layer can also be realized by other deposition methods, which is not limited here.
刻蚀工艺一般是指把薄膜上未被抗蚀剂掩蔽的部分薄膜层除去，从而在薄膜层上形成与抗蚀剂膜完全相同图形的工艺。刻蚀工艺一般包括干法刻蚀和湿法刻蚀，本实施方式中不作限定，只要能够在金属膜层上刻蚀出栅极即可。The etching process generally refers to the process of removing the part of the film layer that is not masked by the resist, so as to form the same pattern on the film layer as the resist film. The etching process generally includes dry etching and wet etching, which are not limited in this embodiment, as long as the gate can be etched on the metal film layer.
在栅极形成后，在栅极的表面沉积栅极绝缘层。After the gate is formed, a gate insulating layer is deposited on the surface of the gate.
其中，所述栅极绝缘层包括氮化硅SiNx，非晶氧化硅SiOx中的至少一种，在其他实施方式中，也可以为其他绝缘物质，在此不做限定。Wherein, the gate insulating layer includes at least one of silicon nitride SiNx and amorphous silicon oxide SiOx, and in other implementation manners, it may also be other insulating materials, which are not limited here.
202：对所述栅极绝缘层的凸起部位进行刻蚀，形成一凹陷区域。202: Etching the raised portion of the gate insulating layer to form a recessed region.
由于栅极的存在，在栅极和第一基板的表面的各个位置都形成相同厚度的栅极绝缘层时，绝缘层在栅极的表面也会形成一凸起，为了防止由于该凸起引起的漏极和源级的断线，本实施方式中，采用第二道光罩对该凸起部位进行刻蚀，在栅极绝缘层上形成一凹陷区域，如图3所示的3031，其中，301为第一基板、302为栅极、303为栅极绝缘层。Due to the existence of the gate, when a gate insulating layer of the same thickness is formed at various positions on the surface of the gate and the first substrate, the insulating layer will also form a protrusion on the surface of the gate. The disconnection of the drain electrode and the source level, in this embodiment, the second photomask is used to etch the raised part, and a recessed area is formed on the gate insulating layer, such as 3031 shown in Figure 3, wherein, 301 is a first substrate, 302 is a gate, and 303 is a gate insulating layer.
203：在所述凹陷区域形成有缘层。203: Form an edge layer in the recessed region.
具体地，结合图3和图4，再通过第三道光罩在该凹陷区域303是通过化学沉积非晶硅，并进行图案化，形成有缘层404。Specifically, referring to FIG. 3 and FIG. 4 , the third photomask is used to chemically deposit amorphous silicon in the recessed region 303 and pattern it to form an active layer 404 .
在优选的实施方式中，有缘层的厚度与该凹陷区域的深度相同，即通过有缘层404填平该凹陷区。这样，有缘层404与栅极绝缘层之间不再呈现阶梯形状。In a preferred embodiment, the thickness of the active layer is the same as the depth of the recessed area, that is, the recessed area is filled up by the active layer 404 . In this way, there is no stepped shape between the active layer 404 and the gate insulating layer.
204：在所述有缘层上形成一漏极和一源级，且所述源级和所述漏极以一沟道分开以暴露部分所述有缘层。204: Form a drain and a source on the active layer, and the source and the drain are separated by a trench to expose part of the active layer.
具体地，如图5所示，通过第四道光罩对该有缘层进行刻蚀，形成一沟道5041以及被上述沟道5041分隔开的漏极505和源极506的有源区的图形化，其中漏极505和源极506被沟道隔开分别位于栅极的两侧。Specifically, as shown in FIG. 5, the active layer is etched through a fourth photomask to form a pattern of a channel 5041 and the active regions of the drain 505 and the source 506 separated by the channel 5041. 2, wherein the drain 505 and the source 506 are separated by a channel and located on both sides of the gate respectively.
再形成漏极505和源级506之后，由图5可以看出，源级505和漏极506平滑的覆盖在有缘层的上方，能够完全消除由于栅极绝缘层和有缘层共同厚度带来的源级和漏极的爬坡现象，因此，上述方式能够完全消除了由于台阶的存在而导致的容易断线的风险。After the drain 505 and the source 506 are formed, it can be seen from FIG. 5 that the source 505 and the drain 506 cover the active layer smoothly, which can completely eliminate the problem caused by the common thickness of the gate insulating layer and the active layer. The climbing phenomenon of the source and drain, therefore, the above method can completely eliminate the risk of easy disconnection caused by the existence of steps.
其中，上述光罩均包括半色调掩膜工艺，或灰色调掩模工艺，或单狭缝掩膜工艺中的一种，在其他实施方式中也可以为其他工艺，只要能够通过一次光罩能够实现漏极和源极的有源区的图形化的工艺都属于本发明保护的范围，在此不做限定。Wherein, the above-mentioned photomasks all include a half-tone mask process, or a gray-tone mask process, or one of a single-slit mask process. The process of realizing the patterning of the active regions of the drain and the source all belongs to the protection scope of the present invention, which is not limited here.
在另一个实施方式中，如图6所示，图6为本发明氧化物薄膜晶体管制作方法的流程示意图，本实施方式的制作方法与图2所示的制作方法的区别在于在在所述有缘层上形成一漏极和一源级，且所述源级和所述漏极以一沟道分开以暴露部分所述有缘层的步骤604之后，还包括In another embodiment, as shown in FIG. 6, FIG. 6 is a schematic flowchart of a method for manufacturing an oxide thin film transistor of the present invention. The difference between the method of this embodiment and the method shown in FIG. After the step 604 of forming a drain and a source on the layer, and the source and the drain are separated by a channel to expose part of the active layer, further comprising
步骤605：在所述氧化物薄膜晶体管的表面沉积钝化层。Step 605: Deposit a passivation layer on the surface of the oxide thin film transistor.
步骤606：在所述绝缘钝化层上刻蚀形成接触通孔；并刻蚀所述接触通孔形成接触电极。Step 606: Etching on the insulating passivation layer to form a contact via hole; and etching the contact via hole to form a contact electrode.
具体地，在氧化层薄膜晶体管的栅极、源极、漏极形成以后，在氧化层薄膜晶体管的表面沉积绝缘钝化层，并在绝缘钝化层上刻蚀形成接触通孔。Specifically, after the gate, source, and drain of the oxide thin film transistor are formed, an insulating passivation layer is deposited on the surface of the oxide thin film transistor, and contact holes are formed by etching on the insulating passivation layer.
并在上述接触通孔中形成接触电极。And a contact electrode is formed in the contact hole.
其中，绝缘钝化层包括氮化硅SiNx，非晶氧化硅SiOx中的至少一种，在其他实施方式中，也可以为其他相同性质的绝缘钝化物质，在此不做限定。接触电极为铟锡氧化物ITO电极，在其他实施方式中，也可以根据需要将ITO电极替换成其他电极，在此不做限定。Wherein, the insulating passivation layer includes at least one of silicon nitride SiNx and amorphous silicon oxide SiOx, and in other implementation manners, it may also be other insulating passivation materials with the same properties, which is not limited here. The contact electrodes are indium tin oxide ITO electrodes. In other embodiments, the ITO electrodes can also be replaced with other electrodes as required, which is not limited here.
区别于现有技术，本实施方式的氧化物薄膜晶体管的制作方法在第一基板上形成栅极以及栅极绝缘层以后，对栅极绝缘层凸起部位进行刻蚀，即在栅极绝缘层的表面形成一凹陷区域，能够有效消除栅极绝缘层表面的凸起部位，即消除栅极表面的阶梯爬坡；再在该凹陷区域形成有缘层，最后在有缘层上形成以一沟道分隔开且暴露部分有缘层的漏极和源级，能够使源级和漏极接近平滑的平铺在有缘层上，能够完全消除由于栅极绝缘层和有缘层共同厚度带来的源级和漏极的爬坡现象，因此，上述方式能够完全消除了由于台阶的存在而导致的容易断线的风险。进一步提高氧化物薄膜晶体管的良率以及开口率，改善液晶显示产品的品质。Different from the prior art, in the manufacturing method of the oxide thin film transistor of this embodiment, after the gate and the gate insulating layer are formed on the first substrate, the raised portion of the gate insulating layer is etched, that is, the gate insulating layer is etched. A recessed area is formed on the surface of the gate insulating layer, which can effectively eliminate the raised parts on the surface of the gate insulating layer, that is, eliminate the step climbing on the gate surface; then form an insulating layer in the recessed area, and finally form a channel on the active layer The drain and source of the separated and exposed part of the active layer can make the source and drain nearly flat on the active layer, and can completely eliminate the source and drain caused by the common thickness of the gate insulating layer and the active layer. Drain climbing phenomenon, therefore, the above method can completely eliminate the risk of easy disconnection caused by the existence of steps. Further improve the yield rate and aperture ratio of oxide thin film transistors, and improve the quality of liquid crystal display products.
在另一个实施方式中，如图7所示，图7为本发明氧化物薄膜晶体管再一实施方式的流程示意图。本实施方式的流程示意图包括如下步骤：In another embodiment, as shown in FIG. 7 , FIG. 7 is a schematic flowchart of another embodiment of the oxide thin film transistor of the present invention. The schematic flow chart of this embodiment includes the following steps:
701：在第一基板上依次形成栅极以及栅极绝缘层。701: Form a gate and a gate insulating layer in sequence on a first substrate.
具体地，先在第一基板上通过沉积的方式形成金属膜层，经过一道光罩对金属膜层进行曝光，将金属膜层刻蚀成栅极。其中，第一道光罩为只能刻蚀一层的普通光罩。Specifically, firstly, a metal film layer is formed on the first substrate by way of deposition, and the metal film layer is exposed through a photomask, and the metal film layer is etched to form a gate. Among them, the first photomask is an ordinary photomask that can only etch one layer.
其中，第一基板包括玻璃基板以及石英基板，在其他实施方式中还可以为其他基板，在此不做限定。Wherein, the first substrate includes a glass substrate and a quartz substrate, and may also be other substrates in other implementation manners, which is not limited here.
金属膜层包括铝Al、钼Mo、铜Cu以及银Ag中的至少一种，在其他实施方式中也可以为其他金属，在此也不做限定。The metal film layer includes at least one of aluminum Al, molybdenum Mo, copper Cu, and silver Ag, and may be other metals in other embodiments, which is not limited here.
702：抹平所述栅极绝缘层的凸起部位，以使该栅极绝缘层的表面为平面。702: Smooth out the raised portion of the gate insulating layer, so that the surface of the gate insulating layer is flat.
由于栅极的存在，在栅极和玻璃基板都形成相同厚度的栅极绝缘层时，绝缘层在栅极的表面也会形成一凸起，为了防止由于该凸起引起的漏极和源级的断线，本实施方中通过第二道光罩将该凸起进行抹平。通过消除该凸起部位，能够消除源级和漏极由于该凸起部位的存在而带来的爬坡现象，从而有效防止源级和漏极的断线。Due to the existence of the gate, when the gate insulating layer with the same thickness is formed on the gate and the glass substrate, the insulating layer will also form a protrusion on the surface of the gate, in order to prevent the drain and source caused by the protrusion. In this embodiment, the protrusion is smoothed by the second photomask. By eliminating the raised portion, the climbing phenomenon of the source and drain due to the existence of the raised portion can be eliminated, thereby effectively preventing disconnection of the source and drain.
703：在所述栅极绝缘层上形成有缘层。703: Form an insulating layer on the gate insulating layer.
具体地，在平面的栅极绝缘层上通过化学沉积非晶硅，在此步骤中，不需要光罩操作。Specifically, amorphous silicon is chemically deposited on the planar gate insulating layer, and no photomask operation is required in this step.
704：在所述有缘层上形成一漏极和一源级，且所述源级和所述漏极以一沟道分开以暴露部分所述有缘层。704: Form a drain and a source on the active layer, and the source and the drain are separated by a trench to expose part of the active layer.
705：在所述氧化物薄膜晶体管的表面沉积钝化层。705: Deposit a passivation layer on the surface of the oxide thin film transistor.
706：在所述绝缘钝化层上刻蚀形成接触通孔；并刻蚀所述接触通孔形成接触电极。706: Form a contact via hole by etching on the insulating passivation layer; and etch the contact via hole to form a contact electrode.
步骤704～步骤706与上述事实方式的步骤604～606相同，再此不再赘述。Steps 704 to 706 are the same as steps 604 to 606 in the above-mentioned de facto mode, and will not be repeated here.
区别于现有技术，本实施方式的氧化物薄膜晶体管的制作方法与上述实施方式的制作方法的区别在于，在形成栅极绝缘层以后，抹平该栅极绝缘层的凸起部位，使其形成一个平面，再在该栅极绝缘层上形成有缘层。通过上述方式消除栅极绝缘层表面的凸起部位，能够消除由于该凸起部位所导致的源级和漏极爬坡现象，减小源级和漏极由于台阶的存在而导致的容易断线的风险。进一步提高氧化物薄膜晶体管的良率以及开口率，改善液晶显示产品的品质。Different from the prior art, the difference between the manufacturing method of the oxide thin film transistor of this embodiment and the manufacturing method of the above-mentioned embodiment is that after forming the gate insulating layer, the protruding part of the gate insulating layer is smoothed to make it A plane is formed, and an insulating layer is formed on the gate insulating layer. By eliminating the raised portion on the surface of the gate insulating layer in the above way, the source and drain climbing phenomenon caused by the raised portion can be eliminated, and the easy disconnection of the source and drain due to the existence of steps can be reduced. risks of. Further improve the yield rate and aperture ratio of oxide thin film transistors, and improve the quality of liquid crystal display products.
参阅图8，图8是本发明薄膜晶体管一实施方式的结构示意图，如图8所示，本实施方式的薄膜晶体管包括第一基板801、设置在第一基板上的栅极802、设置在栅极802上的栅极绝缘层803。Referring to FIG. 8, FIG. 8 is a schematic structural diagram of an embodiment of the thin film transistor of the present invention. As shown in FIG. 8, the thin film transistor of this embodiment includes a first substrate 801, a gate 802 disposed on the first substrate, The gate insulating layer 803 on the electrode 802.
其中，栅极802是在第一基板上通过沉积的方式形成金属膜层，经过对金属膜层进行曝光刻蚀而形成的。其中，刻蚀工艺一般是指把薄膜上未被抗蚀剂掩蔽的部分薄膜层除去，从而在薄膜层上形成与抗蚀剂膜完全相同图形的工艺。刻蚀工艺一般包括干法刻蚀和湿法刻蚀，本实施方式中不作限定，只要能够在金属膜层上刻蚀出栅极即可。Wherein, the gate 802 is formed by depositing a metal film layer on the first substrate, and then exposing and etching the metal film layer. Among them, the etching process generally refers to the process of removing part of the film layer on the film that is not masked by the resist, so as to form the same pattern on the film layer as the resist film. The etching process generally includes dry etching and wet etching, which are not limited in this embodiment, as long as the gate can be etched on the metal film layer.
栅极绝缘层803也是通过沉积工艺而形成的。沉积工艺一般是指外来物质淀积于基底表面形成薄膜，又称为气相沉积。本实施方式是通过金属物质在第一基板的表面形成金属膜层。在其他实施方式中，也可以通过其他沉积方式来实现金属膜层，在此不作限定。The gate insulating layer 803 is also formed by a deposition process. The deposition process generally refers to the deposition of foreign substances on the surface of the substrate to form a thin film, also known as vapor deposition. In this embodiment, a metal film layer is formed on the surface of the first substrate by using a metal substance. In other implementation manners, the metal film layer can also be realized by other deposition methods, which is not limited here.
其中，第一基板包括玻璃基板以及石英基板，在其他实施方式中还可以为其他基板，在此不做限定。金属膜层包括铝Al、钼Mo、铜Cu以及银Ag中的至少一种，在此也不做限定。Wherein, the first substrate includes a glass substrate and a quartz substrate, and may also be other substrates in other implementation manners, which is not limited here. The metal film layer includes at least one of aluminum Al, molybdenum Mo, copper Cu and silver Ag, which is not limited here.
栅极绝缘层包括氮化硅SiNx，非晶氧化硅SiOx中的至少一种，在其他实施方式中，也可以为其他绝缘物质，在此不做限定。The gate insulating layer includes at least one of silicon nitride SiNx and amorphous silicon oxide SiOx. In other implementation manners, it may also be other insulating materials, which are not limited here.
进一步地如图8所示，该氧化物薄膜晶体管还包括有缘层804，其中，该有缘层设置在栅极绝缘层的凹陷区域8031中。其中，该凹陷区域8031是为刻蚀该栅极绝缘层803的凸起部位后形成的区域。As further shown in FIG. 8 , the oxide thin film transistor further includes an active layer 804 , wherein the active layer is disposed in the recessed region 8031 of the gate insulating layer. Wherein, the recessed region 8031 is a region formed after etching the raised portion of the gate insulating layer 803 .
具体地，由于栅极的存在，在栅极和第一基板的表面的各个位置都形成相同厚度的栅极绝缘层时，绝缘层在栅极的表面也会形成一凸起，为了防止由于该凸起引起的漏极和源级的断线，本实施方式的栅极绝缘层803表面的凸起部位已经通过第二道光罩对该凸起部位进行刻蚀掉，并在栅极绝缘层上形成一凹陷区域8031，以减小由于该凸起部位带来的源级和漏极的爬坡现象。Specifically, due to the existence of the gate, when a gate insulating layer of the same thickness is formed at various positions on the surface of the gate and the first substrate, the insulating layer will also form a protrusion on the surface of the gate. The disconnection of the drain and the source level caused by the protrusion, the raised part on the surface of the gate insulating layer 803 in this embodiment has been etched away by the second photomask, and on the gate insulating layer A recessed region 8031 is formed to reduce the ramping of the source and drain due to the raised portion.
本实施方式的有缘层804形成在该凹陷区域8031内。具体地，该有缘层804是通过化学沉积非晶硅，并进行图案化后形成的。The active layer 804 of this embodiment is formed in the recessed region 8031 . Specifically, the active layer 804 is formed by chemically depositing amorphous silicon and patterning it.
在一个优选的实施方式中，有缘层的厚度与该凹陷区域的深度相同，即通过有缘层404填平该凹陷区。这样，有缘层404与栅极绝缘层之间不再呈现阶梯形状。能够避免由于有缘层804突出而带来的栅极和源级爬坡的现象。In a preferred embodiment, the thickness of the active layer is the same as the depth of the recessed area, that is, the recessed area is filled up by the active layer 404 . In this way, there is no stepped shape between the active layer 404 and the gate insulating layer. It is possible to avoid the phenomenon of ramping up of the gate and source due to the protrusion of the active layer 804 .
进一地，本实施方式的氧化物薄膜晶体管还包括设置在有缘层804表面以一沟道分隔开并暴露部分该有缘层804的源极805和漏极806。具体地，以一沟道分隔开的源极805和漏极806是通过一道光罩对该有缘层804进行刻蚀，形成沟道以及被上述沟道分隔开的漏极805和源极806的有源区的图形化后得到的，其中漏极805和源极806被沟道隔开分别位于栅极的两侧。Furthermore, the oxide thin film transistor of this embodiment further includes a source 805 and a drain 806 disposed on the surface of the active layer 804 separated by a channel and exposing part of the active layer 804 . Specifically, the source 805 and the drain 806 separated by a channel are etched on the active layer 804 through a photomask to form the channel and the drain 805 and the source separated by the channel 806 is obtained after patterning the active region, wherein the drain 805 and the source 806 are separated by a channel and located on both sides of the gate respectively.
上述光罩包括半色调掩膜工艺，或灰色调掩模工艺，或单狭缝掩膜工艺中的一种，在其他实施方式中也可以为其他工艺，只要能够通过一次光罩能够实现漏极208和源极207的有源区的图形化的工艺都属于本发明保护的范围，在此不做限定。The above-mentioned photomask includes one of the half-tone masking process, or the gray-tone masking process, or the single-slit masking process. The patterning process of the active regions of the 208 and the source 207 all belong to the protection scope of the present invention, which is not limited here.
另外，氧化物薄膜晶体管的表面还覆盖有绝缘钝化层807，且，绝缘钝化层807上设置有接触通孔808，接触通孔808中设置有接触电极809。In addition, the surface of the oxide thin film transistor is also covered with an insulating passivation layer 807 , and the insulating passivation layer 807 is provided with a contact via 808 , and a contact electrode 809 is provided in the contact via 808 .
其中，接触通孔809是通过在绝缘钝化层809上刻蚀而形成的，接触电极809是通过在接触通孔808中形成的。Wherein, the contact hole 809 is formed by etching on the insulating passivation layer 809 , and the contact electrode 809 is formed in the contact hole 808 .
其中，绝缘钝化层807包括氮化硅SiNx，非晶氧化硅SiOx中的至少一种，在其他实施方式中，也可以为其他相同性质的绝缘钝化物质，在此不做限定。触控电极809为铟锡氧化物ITO电极，在其他实施方式中，也可以根据需要将ITO电极替换成其他电极，在此不做限定。Wherein, the insulating passivation layer 807 includes at least one of silicon nitride SiNx and amorphous silicon oxide SiOx. In other implementation manners, it can also be other insulating passivation materials with the same properties, which is not limited here. The touch electrodes 809 are indium tin oxide (ITO) electrodes. In other implementation manners, the ITO electrodes can also be replaced with other electrodes as required, which is not limited here.
区别于现有技术，本实施方式的氧化物薄膜晶体管包括第一基板，设置在所述第一基板上的栅极、设置在所述栅极上的栅极绝缘层凹陷区域内的有缘层；还包括位于所述有缘层上方，以一沟道分隔开并暴露部分所述有缘层的源极和漏极；所述凹陷区域为蚀刻所述栅极绝缘凸起部位形成的区域。能够消除栅极绝缘层表面的凸起部位，使源级和漏极接近平滑的平铺在有缘层上，完全消除由于爬坡而导致的源级和漏极断线的风险。进一步提高氧化物薄膜晶体管的良率以及开口率，改善液晶显示产品的品质。Different from the prior art, the oxide thin film transistor of this embodiment includes a first substrate, a gate disposed on the first substrate, and an active layer disposed in the recessed region of the gate insulating layer on the gate; It also includes a source electrode and a drain electrode located above the active layer, separated by a trench and exposing a part of the active layer; the recessed area is an area formed by etching the gate insulation protrusion. It can eliminate the protruding part on the surface of the gate insulating layer, make the source and drain nearly flat on the active layer, and completely eliminate the risk of source and drain disconnection caused by climbing. Further improve the yield rate and aperture ratio of oxide thin film transistors, and improve the quality of liquid crystal display products.
参阅图9，图9是本发明薄膜晶体管另一实施方式的结构示意图。本实施方式的薄膜晶体管与上一个实施方式的薄膜晶体管的区别在于，本实施方式的有缘层904形成在栅极绝缘层903的表面，其中，该栅极绝缘层903为弄平其凸起部位后的平面状，而并不具有上述实施方式的凹陷区域，通过该特征，能够消除由于该凸起部位所导致的源级和漏极爬坡现象，减小源级和漏极由于台阶的存在而导致的容易断线的风险。进一步提高氧化物薄膜晶体管的良率以及开口率，改善液晶显示产品的品质。Referring to FIG. 9 , FIG. 9 is a schematic structural diagram of another embodiment of the thin film transistor of the present invention. The difference between the thin film transistor of this embodiment and the thin film transistor of the previous embodiment is that the active layer 904 of this embodiment is formed on the surface of the gate insulating layer 903, wherein the gate insulating layer 903 is used to flatten its raised portion After the planar shape, and does not have the recessed region of the above-mentioned embodiment, through this feature, the source and drain climbing phenomenon caused by the raised part can be eliminated, and the source and drain due to the existence of steps can be reduced. resulting in the risk of easy disconnection. Further improve the yield rate and aperture ratio of oxide thin film transistors, and improve the quality of liquid crystal display products.
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。The above is only the embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process conversion made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technologies fields, all of which are equally included in the scope of patent protection of the present invention.
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| CN201510955581.9ACN105355664A (en) | 2015-12-17 | 2015-12-17 | Oxide thin-film transistor and manufacturing method thereof |
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| CN201510955581.9ACN105355664A (en) | 2015-12-17 | 2015-12-17 | Oxide thin-film transistor and manufacturing method thereof |
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| CN201510955581.9APendingCN105355664A (en) | 2015-12-17 | 2015-12-17 | Oxide thin-film transistor and manufacturing method thereof |
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