Disclosure of Invention
The invention provides a method for forming a semiconductor device, which solves the problem of deformation of a formed metal gate so as to improve the performance of a transistor.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including:
providing a semiconductor substrate;
forming a pseudo gate material layer on the semiconductor substrate, wherein the pseudo gate material layer is of a multilayer structure;
and etching the pseudo gate material layer to enable the etching rate of each layer in the multilayer structure to be gradually decreased from bottom to top so as to form the pseudo gate structure with the width gradually increased from bottom to top.
Optionally, the multilayer structure is a double-layer structure, and the step of forming a dummy gate material layer on the semiconductor substrate includes:
forming a dummy gate material on the semiconductor substrate;
then, injecting first ions into the surface area of the pseudo gate material to form a first pseudo gate layer, wherein the part of the pseudo gate material which is positioned below the first pseudo gate layer and is not injected with the ions is a second pseudo gate layer;
or,
forming a dummy gate material on the semiconductor substrate;
and then, injecting second ions into the bottom area of the pseudo gate material to form a second pseudo gate layer, wherein the part of the pseudo gate material which is positioned above the second pseudo gate layer and is not injected with the ions is the first pseudo gate layer.
Optionally, the step of forming the dummy gate material layer includes making a thickness ratio of the first dummy gate layer to the second dummy gate layer to be 0.1 to 10.
Optionally, the process parameters for implanting the first ions into the dummy gate material include:
the ion implantation dose is 1.0 × 1013To 1.0 × 1017/cm2The energy is 1.0 to 20 eV.
Optionally, the process parameters for implanting the second ions into the dummy gate material include:
ion implantationThe dosage is 1.0 × 1013To 1.0 × 1017/cm2The energy is 1.0 to 20 eV.
Optionally, the first ion is a nitrogen ion or a carbon ion.
Optionally, the second ion is a phosphorous ion.
Optionally, the multilayer structure is a double-layer structure; the step of forming a dummy gate material layer on the semiconductor substrate includes:
forming a second dummy gate layer on the semiconductor substrate based on a silicon source gas;
forming a first dummy gate layer on the second dummy gate layer based on a silicon source gas and a carbon source or nitrogen source gas.
Optionally, the multilayer structure is a double-layer structure; the step of forming a dummy gate material layer on the semiconductor substrate includes:
forming a first dummy gate layer on the semiconductor substrate based on a silicon source gas and a phosphorus source gas;
a second dummy gate layer is formed on the first dummy gate layer based on a silicon source gas.
Optionally, the step of etching the dummy gate material layer to form a dummy gate structure includes:
and etching the pseudo gate material layer to enable an included angle between the formed pseudo gate structure side wall and the semiconductor substrate to be 45-85 degrees.
Optionally, the step of etching the dummy gate material layer to form a dummy gate structure includes: etching the pseudo gate material layer by adopting a dry etching process; the dry etching process comprises the following steps:
to contain CF4And O2The gas is etching gas, the gas pressure is 1-500 mtorr, the radio frequency power is 50-500W, and the bias power is 0-500W.
Optionally, the step of etching the dummy gate material layer to form a dummy gate structure includes:
forming a hard mask on the pseudo gate material layer, wherein the hard mask is doped with carbon ions or phosphorus atoms;
etching the pseudo gate material layer by taking the hard mask as a mask to form the pseudo gate structure;
the method for forming the semiconductor device further comprises the following steps:
and after the pseudo gate structure is formed, injecting ions into the semiconductor substrate by taking the hard mask as a mask to form a source drain region.
Optionally, the hard mask is a silicon nitride layer doped with carbon ions, and the process of forming the hard mask includes:
forming a silicon nitride material layer on the semiconductor substrate, and injecting carbon ions into the silicon nitride material layer to form a carbon ion-doped silicon nitride layer;
etching the silicon nitride layer to form the hard mask;
or the light source is used for emitting light,
the hard mask is a silicon nitride layer doped with phosphorus ions, and the process for forming the hard mask comprises the following steps:
forming a silicon nitride material layer on the semiconductor substrate, and injecting phosphorus ions into the silicon nitride material layer to form a phosphorus ion-doped silicon nitride layer;
and etching the silicon nitride layer to form the hard mask.
Optionally, the hard mask comprises a silicon nitride layer doped with carbon ions, and the process of forming the hard mask comprises:
forming a carbon ion-doped silicon nitride layer on the semiconductor substrate based on ammonia gas, a silicon source gas and a carbon source gas;
etching the silicon nitride layer to form the hard mask;
or the light source is used for emitting light,
the hard mask includes a silicon nitride layer doped with phosphorous ions, and the process of forming the hard mask includes:
forming a phosphorus ion-doped silicon nitride layer on the semiconductor substrate based on ammonia gas, silicon source gas and phosphorus source gas;
and etching the silicon nitride layer to form the hard mask.
Optionally, the dummy gate structure is an NMOS dummy gate structure.
Optionally, the forming method further comprises: after the NMOS pseudo gate structure is formed, a dielectric layer is formed on the semiconductor substrate and covers the NMOS pseudo gate structure;
removing part of the dielectric layer with a planarization process to expose the NMOS pseudo gate structure;
removing the NMOS pseudo gate structure, and forming an NMOS gate opening in the dielectric layer;
and filling a metal material into the NMOS gate opening to form the NMOS metal gate.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the pseudo gate material layer formed on the semiconductor substrate comprises a multilayer structure, the pseudo gate material layer is etched to form a pseudo gate structure, and the etching rate of each layer of the multilayer structure is gradually reduced from bottom to top, so that the formed pseudo gate structure is of a structure with the width gradually increased from bottom to top. When the grid structure is removed to form the grid opening, the size of the grid opening is increased from bottom to top, and after the metal material is filled in the grid opening to form the metal grid, even if the stress of the metal material easily enables the width of the lower end of the metal grid to be larger than the width of the upper end of the metal grid, the difference between the width of the upper end and the width of the lower end of the finally formed metal grid can be reduced based on the structure that the grid opening is increased from bottom to top, so that the stability of the structural form of the metal grid is improved, and the stability of the performance of a.
And further, after the pseudo gate structure is formed by etching the pseudo gate material layer by taking the silicon nitride layer doped with carbon ions or phosphorus ions as a hard mask, injecting ions into the semiconductor substrate by taking the hard mask as a mask to form a source drain region. In the hard mask, carbon ions (or phosphorus ions) and silicon ions are combined to form a Si-C (Si-P) conjunct, so that the density of the hard mask can be improved, the probability that source and drain ions penetrate through the hard mask and enter a channel of a semiconductor substrate in the process of injecting the source and drain ions into the semiconductor substrate to form a source and drain region is effectively reduced, and the defects of short channel effect and the like caused by the source and drain ions are improved.
Detailed Description
As described in the background, the metal gate formed by the gate last of the prior art transistor is easily deformed, resulting in poor transistor stability.
For the reason analyzed with reference to fig. 1 and fig. 2, after the gate opening 12 is filled with the metal material, based on the characteristics of the metal material used for forming the NMOS metal gate and the definition of the gate opening structure, there is a difference in stress release at various portions in the metal material in the metal gate, so that the formed metal material is deformed, and thus the finally formed NMOS metal gate structure is different from the original design structure (i.e., the structure of the gate opening).
Specifically, as shown in fig. 1 and fig. 2, most of the originally designed metal gates are columnar structures (i.e., structures of the gate openings 12) with the widths of the upper ends and the lower ends being close to each other, but after the metal materials are filled into the gate openings 12 in the columnar structures, based on the stress difference of each part of the metal materials, the formed NMOS metal gate 13 has a structure with the width of the upper end being smaller than that of the lower end, and the structural form of the originally set metal gate is destroyed, so that the performance of the NMOS metal gate is reduced.
In order to solve the above problem, the present invention provides a method of forming a semiconductor device, including: forming a dummy gate material layer including a multi-layer structure on a semiconductor substrate; and etching the pseudo gate material layer to enable the etching rate of each layer structure in the multilayer structure to be gradually decreased from bottom to top so as to form a pseudo gate structure with gradually increased width from bottom to top, so that the pseudo gate structure is an inverted trapezoid structure with the width of the upper end larger than that of the lower end. And forming a dielectric layer on the semiconductor substrate, and removing the pseudo gate structure, wherein the gate opening formed in the dielectric layer is of an inverted trapezoid structure with the upper end width larger than the lower end width. After the metal material for forming the metal grid is filled in the grid opening, even if the metal material expands the width of the lower end of the metal material more than the upper end under the action of internal stress, and the ratio of the width of the upper end to the width of the lower end of the metal material is increased, the difference between the width of the upper end and the width of the lower end of the finally formed metal grid caused by the internal stress release difference of the metal material can be effectively relieved based on the structural constraint of the grid opening, the structural form of the formed metal grid is improved, and the performance of the metal grid is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 10 are schematic structural views of a method for forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 3, the method for forming a semiconductor device according to the present embodiment includes:
providing a semiconductor substrate 20, and forming a gate dielectric layer 23 on the semiconductor substrate 20; a dummy gate material 30 is formed on the gate dielectric layer 23.
The semiconductor substrate 20 is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a glass substrate, or a III-V compound substrate, and the material of the semiconductor substrate does not limit the scope of the present invention.
In this embodiment, the semiconductor substrate 20 is a silicon substrate.
In this embodiment, the semiconductor substrate 20 includes an NMOS region 22 and a PMOS region 21, and the NMOS region 22 and the PMOS region 21 are separated by an isolation structure (not shown).
In this embodiment, the isolation structure is a Shallow Trench Isolation (STI) structure.
In this embodiment, the dummy gate material is polysilicon, and the forming process is Chemical Vapor Deposition (CVD), but the dummy gate material and the forming process do not limit the protection scope of the present invention.
In this embodiment, the gate dielectric layer 23 is a silicon oxide layer.
Referring to fig. 4, ions are implanted into the dummy gate material 30, so as to form a dummy gate material layer 35 in a stacked structure in the dummy gate material 30. Specifically, the dummy gate material layer 35 includes a second dummy gate layer 31 on the gate dielectric layer 23, and a first dummy gate layer 32 on the second dummy gate layer 31; in this embodiment, when the dummy gate material layer 35 is subsequently etched to form a dummy gate structure, the etching rate of the second dummy gate layer 31 is greater than the etching rate of the first dummy gate layer 32.
In this embodiment, the thickness ratio of the second dummy gate layer 31 to the first dummy gate layer 32 is 0.1 to 10, and specific values are set according to specific requirements.
In this embodiment, the forming process of the dummy gate material layer 35 includes:
first ions are injected into the surface area of the dummy gate material 30 to form a first dummy gate layer 32 on the surface layer, and the portion of the dummy gate material not doped with ions is located below the first dummy gate layer 32 to form a second dummy gate layer 31.
In this embodiment, the first ion is a nitrogen ion (N) or a carbon ion (C).
In the process of implanting nitrogen ions (or carbon ions) into the surface region of the dummy gate material 30, the ion implantation dosage is controlled to be 1.0 × 1013To 1.0 × 1017/cm2The energy is 1.0 to 20 eV.
In this embodiment, the process of implanting nitrogen ions (or carbon ions) into the dummy gate material 30 is specifically an ion implanter implantation process, which includes: introducing a carbon source gas (or a nitrogen source gas) into the ion implanter, and controlling the parameters of the ion implanter as follows: the gas pressure is 10-100 mtorr, the extraction voltage (extraction voltage) is 10-100 KV, the extraction current (extraction current) is 0.1-5.0 mA, the arc voltage (ArcVoltage) is 500-2500V, the arc current (ArcCurrent) is 10-100 mA, the filament current (FilamentCurrent) is 50-500A, the filament voltage (FilamentVoltage) is 10-50V, and the solenoid current (SolenodCurrent) is 1.0-10.0A.
In this embodiment, in the subsequent dry etching process, the etching rate of the polysilicon layer (i.e., the second dummy gate layer 31) that is not doped with nitrogen ions (or carbon ions) is greater than the etching rate of the polysilicon layer (i.e., the first dummy gate layer 32) that is doped with nitrogen ions (or carbon ions).
In addition, in the present embodiment, the dummy gate material layer 35 with a double-layer structure is formed by ion implantation. However, the invention is not limited thereto, and in other embodiments, the dummy gate material layer 35 may be formed directly by using a CVD process, which specifically includes:
introducing silicon source gas into the reaction chamber, and forming a polysilicon layer on the semiconductor substrate 20 to form the second dummy gate layer 31; thereafter, while continuing to supply the silicon source gas, a carbon source gas (or a nitrogen source gas) is supplied to form a first dummy gate layer 32 on the second dummy gate layer 31.
In this embodiment, the nitrogen source gas is nitrogen (N)2) The carbon source gas is carbon monoxide (CO) or carbon dioxide (CO)2)。
Referring to fig. 4 to 6 in combination, the dummy gate material layer 35 is etched to form a PMOS dummy gate 61 and an NMOS dummy gate 62 on the semiconductor substrate 20. The specific process comprises the following steps:
referring to fig. 4 and 5 in combination, after the dummy gate material layer 35 is formed on the semiconductor substrate 20, the dummy gate material layer 35 is formed from bottom to top: a silicon nitride layer 51 doped with C ions or P ions, a silicon oxide layer 52, an amorphous carbon layer 53 and a dielectric anti-reflective coating (DARC) 54, an organic bottom-resist layer (ODL) 55 and a Si-based anti-reflective layer (Si-ARC) 56; after a photoresist mask 57 is formed on the Si-ARC layer 56, a hard mask 50 is formed on the PMOS region 21 and the NMOS region 22 after the Si-ARC layer 56, the ODL layer 55, the DARC layer 54, the amorphous carbon layer 53, the silicon oxide layer 52, and the silicon nitride layer 51 are sequentially etched using the photoresist mask 57 as a mask.
In this embodiment, the process for forming the silicon nitride layer 51 doped with C ions or P ions includes:
a silicon nitride material layer is formed on the dummy gate material layer 35 by using a Chemical Vapor Deposition (CVD) process, and then C ions or P ions are implanted into the silicon nitride material layer to form a C ion-doped or P ion-doped silicon nitride layer.
In another embodiment, the C ion or P ion doped silicon nitride layer 51 may be formed directly by a CVD process, which includes: and introducing ammonia gas and silicon source gas into the reaction cavity to form a silicon nitride layer, and introducing carbon source gas or phosphorus source gas into the reaction cavity to form a silicon nitride layer doped with carbon (C) ions or phosphorus (P) ions.
The carbon source gas is carbon monoxide (CO) or carbon dioxide (CO)2) The phosphorus source gas is Phosphine (PH)3) Or phosphorus oxychloride (POCl)3)。
The formation process of the silicon oxide layer 52 and the amorphous carbon layer 53 is a CVD process, and the formation process of the DARC layer 54 is a spin-on process, which are well-established processes in the art and are not described herein again.
It should be noted that the hard mask 50 with the silicon nitride layer 51, the silicon oxide layer 52, the amorphous carbon layer 53, the DARC layer 54, the ODL layer 55 and the Si-ARC layer 56 as a whole can improve the precision of the pattern in the hard mask 50, and further improve the precision of the dummy gate structure formed after the dummy gate material layer is etched, but the implementation of the object of the present invention is not affected if only the silicon nitride layer 51 is used as a mask.
Referring to fig. 6, the hard mask 50 is used as a mask to etch the dummy gate material layer 35, so as to form an NMOS dummy gate 62 in the NMOS region 22 and a PMOS dummy gate 61 in the PMOS region 21.
In this embodiment, the process of etching the dummy gate material layer 35 is a dry etching process, which specifically includes:
with CF4And O2The etching gas is an etching gas, the gas pressure is 1-500 mtorr, the radio frequency power is 50-500W, and the bias power is 0-500W, wherein the CF4The flow rate of (A) is 10 to 500sccm, O2The flow rate of (2) is 5 to 500 sccm.
In an alternative arrangement,the etching gas also comprises an auxiliary gas, and the auxiliary gas comprises N2And SF6One or more of (a). Wherein N is2The flow rate of (1) is 0 to 500sccm, SF6The flow rate of (2) is 0 to 100 sccm.
In this embodiment, the thicknesses of the PMOS dummy gate 61 and the NMOS dummy gate 62 are smaller than
In this embodiment, the second dummy gate layer 31 is a polysilicon layer, and the first dummy gate layer 32 is a polysilicon layer doped with N ions or C ions. The etching rate of the second dummy gate layer 31 is greater than that of the first dummy gate layer 32, so that the PMOS dummy gate 61 and the NMOS dummy gate 62 formed after the etching process have an inverted trapezoid structure with an upper end width greater than a lower end width, and in this embodiment, the sidewalls of the PMOS dummy gate 61 and the NMOS dummy gate 62 are inclined.
In this embodiment, if the thickness ratio of the second dummy gate layer 31 to the first dummy gate layer 32 is too large or too small, the subsequent formation of the gate opening and the formation of the metal gate structure in the gate opening are affected, and the thickness ratio of the second dummy gate layer 31 to the first dummy gate layer 32 also affects the flatness of the sidewall of the formed gate structure.
The thickness ratio of the second dummy gate layer 31 to the first dummy gate layer 32 is 0.1-10, and the specific value is set according to actual needs.
In addition, the inclination angles of the sidewalls of the PMOS dummy gate 61 and the NMOS dummy gate 62 directly affect the structure of the metal gate formed subsequently, thereby affecting the performance of the metal gate.
In this embodiment, an included angle α between the PMOS dummy gate 61 and the NMOS dummy gate 62 and the semiconductor substrate 20 is 45 to 85 °, and the specific value is determined according to a metal material corresponding to the NMOS metal gate and a process for forming the NMOS metal gate.
Next, referring to fig. 7, with the hard mask 50 as a mask, N-type ions and P-type ions are implanted into the semiconductor substrate, so as to form a PMOS source drain region 81 in the PMOS region 21 and an NMOS source drain region 82 in the NMOS region 22.
It is noted that the PMOS source drain region 81 is doped with P-type ions, and the NMOS source drain region 82 is doped with N-type ions. When P-type ions are doped into the PMOS region 81, a photoresist layer is covered on the NMOS region 82; while doping N-type ions into the NMOS region 82, a photoresist layer is covered on the PMOS region 81, which is a mature process in the art and is not described herein again.
As the feature size of the integrated circuit is continuously reduced, the thickness of the dummy gate material layer is also continuously reduced in the gate last process, and as in this embodiment, the thickness of the PMOS dummy gate 61 and the NMOS dummy gate 62 is smaller than that of the PMOS dummy gate 61 and the NMOS dummy gate 62In the existing ion implantation process, the photoresist layer is mostly used as a mask, and in the ion implantation process, the photoresist layer is consumed and the thickness is reduced; therefore, when PMOS and NMOS source/drain regions are formed, partial ions easily penetrate through the photoresist layer and the dummy gate material layer and enter NMOS and PMOS channels in the semiconductor substrate, and therefore the defects of short channel effect and the like are caused.
In this embodiment, silicon (Si) ions in the C (or P) -ion-doped silicon nitride layer 51 are combined to form a Si-C (or Si-P) link, which can improve the density of the hard mask, so that when ions are implanted into the semiconductor substrate 20 to form a PMOS metal gate and an NMOS metal gate, the probability that the ions penetrate through the dummy gate structure (including the PMOS dummy gate 61 and the NMOS dummy gate 62) and then enter the channel region of the semiconductor substrate is reduced, and thus the defects such as a short channel effect caused by the ions entering the channel region are effectively reduced.
Referring to fig. 8, after forming the PMOS and NMOS source/drain regions, the photoresist mask 57, the Si-ARC layer 56, the ODL layer 55, the DARC layer 54, the amorphous carbon layer 53, and the silicon oxide layer 52 are removed, a dielectric layer 100 covering the PMOS dummy gate 61 and the NMOS dummy gate 62 is formed on the semiconductor substrate 20, and the dielectric layer and the silicon nitride layer 51 are formed in an excess thickness by a planarization process such as a Chemical Mechanical Polishing (CMP) process to expose the PMOS dummy gate 61 and the NMOS dummy gate 62.
Referring to fig. 9, the PMOS dummy gate 61 and the NMOS dummy gate 62 are removed, and a PMOS gate opening 101 and an NMOS gate opening 102 are formed in the dielectric layer 100.
In this embodiment, based on the "inverted trapezoid" structure that the upper end width of the PMOS dummy gate 61 and the lower end width of the NMOS dummy gate 62 are larger than each other, the PMOS gate opening 101 and the NMOS gate opening 102 are "inverted trapezoid" structures that the upper end opening size is larger than the lower end opening size.
Referring to fig. 10, a material for forming a PMOS metal gate is filled into the PMOS gate opening 101 to form a PMOS metal gate 201. Most of the materials used to form PMOS metal gates are metal carbonitrides.
And filling the material for forming the NMOS metal gate into the NMOS gate opening 102 to form an NMOS metal gate 202. The materials used to form the NMOS metal gate are metals, metal carbides, metal carbo-silicides, and metal boride materials.
Based on the stress effect inside the metal material filled in the NMOS gate opening 102, the metal material expands from the center to the two sides, and the amount of expansion at the lower end is greater than the amount of expansion at the upper end, so that the NMOS metal gate 202 formed in the NMOS gate opening 102 deforms more than the original NMOS gate opening 102. However, based on the inverted trapezoid structure of the NMOS gate opening 102 in the present embodiment, the NMOS gate opening 102 effectively alleviates the defect of an excessive ratio between the upper end width and the lower end width of the finally formed NMOS metal gate due to the internal stress release difference of the metal material, so as to improve the structural shape of the formed NMOS metal gate and improve the stability of the NMOS metal gate.
In the above embodiments, the dummy gate material layer includes a first dummy gate layer doped with first ions, and a second dummy gate layer located below the first dummy gate layer and not doped with ions. In another embodiment of the present invention, as shown in fig. 3 and 11 in combination, the dummy gate material layer 36 includes a second dummy gate layer 34 doped with second ions and a first dummy gate layer 33 without implanted ions. The forming process of the dummy gate material layer 36 specifically includes:
forming a dummy gate material 30 on the semiconductor substrate 20 by using a CVD process or the like, and then implanting second ions into a bottom region of the dummy gate material 30, thereby forming a second dummy gate layer 34 on the semiconductor substrate 20 in the dummy gate material 30; and the portion of the dummy gate material which is located above the second dummy gate layer 34 and is not implanted with the second ions forms the first dummy gate layer 33, so that in the subsequent etching process, the etching rate of the second dummy gate layer 34 is greater than that of the first dummy gate layer 33.
In this embodiment, the second ions are phosphorus (P) ions, and in the subsequent dry etching process, the etching rate of the P ion-doped polysilicon layer (i.e., the second dummy gate layer 34) is greater than that of the P ion-undoped polysilicon layer (i.e., the first dummy gate layer 33).
In this embodiment, the thickness ratio of the second dummy gate layer 34 to the first dummy gate layer 33 is 0.1 to 10, which is set according to specific requirements.
In this embodiment, in the process of implanting P ions into the dummy gate material 30, the ion implantation dose is controlled to be 1.0 × 1013To 1.0 × 1017/cm2The energy is 1.0 to 20 eV.
In this embodiment, the process of implanting P ions into the dummy gate material 30 is specifically an ion implanter implantation process, and includes: introducing a phosphorus source gas into an ion implanter, and controlling the parameters of the ion implanter as follows: the air pressure is 10-100 mtorr, the extraction voltage is 10-100 KV, the extraction current is 0.1-5.0 mA, the arc voltage is 500V-2500V, the arc current is 10-100 mA, the filament current is 50-500A, the filament voltage is 10-50V, and the solenoid current is 1.0-10.0A.
In other embodiments, the dummy gate material layer 36 may also be formed directly by using a CVD process, which includes:
introducing a silicon source gas and a P source gas into the reaction chamber, and forming a polysilicon layer doped with P ions, i.e., the second dummy gate layer 34, on the semiconductor substrate 20; thereafter, the P source gas is removed, and only the silicon source gas is continuously supplied to form the first dummy gate layer 33, which is not doped with P ions, on the second dummy gate layer 34.
In this embodiment, the P source gas is Phosphine (PH)3) Or phosphorus oxychloride (POCl)3)。
In the above two embodiments, the dummy gate material layer with the double-layer structure is formed in both the PMOS region 21 and the NMOS region 22 of the semiconductor substrate 20, and in other embodiments of the present invention, the dummy gate material layer with the double-layer structure may be formed only on the NMOS region 22 of the semiconductor substrate 20.
In still another embodiment of the present invention, as shown in fig. 12, after forming the polysilicon layer 39 on the semiconductor substrate 20, C or N ions are implanted into the surface region of the polysilicon layer 39 located on the NMOS region 22, a first dummy gate layer 37 doped with C or N ions is formed on the surface region of the NMOS region 22 of the polysilicon layer 39, and a portion of the polysilicon layer located below the first dummy gate layer 37 in the NMOS region 22 is a second dummy gate layer; referring to fig. 13, after an etching process, an NMOS dummy gate 64 having an inverted trapezoid structure with an upper end width larger than a lower end width is formed on the NMOS region 22, and a PMOS dummy gate 65 on the PMOS region 21 has a cubic structure.
Alternatively, referring to fig. 14, in another embodiment of the present invention, P ions are implanted into a bottom region in the polysilicon layer 39 of the NMOS region 22, a second dummy gate layer 38 doped with P ions is formed on the semiconductor substrate 20 in the polysilicon layer 39, and a portion of the polysilicon layer above the second dummy gate layer 38 is a first dummy gate layer above the NMOS region 22; referring to fig. 15, after an etching process, an NMOS dummy gate 66 having an inverted trapezoid structure with an upper end width larger than a lower end width is formed on the NMOS region 22, and a PMOS dummy gate 65 on the PMOS region 21 has a cubic structure.
Or forming a dummy gate material layer with a double-layer structure on the PMOS region and the NMOS region of the semiconductor substrate at the same time (as shown in fig. 4 and 11), removing the dummy gate material layer on the PMOS region, and forming a dummy gate material layer with a single-layer structure on the PMOS region again; and then forming an NMOS pseudo gate with an inverted trapezoid structure with the upper end width larger than the lower end width in an NMOS region of the semiconductor substrate by an etching process, and forming a PMOS pseudo gate with a cubic structure in a PMOS region. All such simple modifications are within the scope of the present invention.
It is to be noted that, in the above embodiments, the dummy gate structure formed on the NMOS region of the semiconductor substrate is a double-layer structure, in other embodiments of the present invention, the dummy gate structure on the NMOS region may be a structure with 3 layers or more, and the etching rate in the multilayer structure decreases from bottom to top, so that the dummy gate structure formed after etching the dummy gate material layer is a structure with a width increasing from bottom to top. For example, the dummy gate material layer with 3-layer structure is a P-ion doped polysilicon layer, an ion undoped polysilicon layer and an N-or C-ion doped polysilicon layer from bottom to top. All such simple modifications are within the scope of the present invention.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.