技术领域technical field
本发明涉及一种通讯系统，特别是涉及一种双二元(duobinary)电压模式传送器。The invention relates to a communication system, in particular to a duobinary voltage mode transmitter.
背景技术Background technique
有线通讯系统的使用对于人们而言，具有息息相关与密不可分的关系。图1展示了当前现有常见的有线(wireline)通讯系统100的方框图，用以传送及接受数据。串化器(serializer,SER)11将数据转换为串行数据流，借由单一线或一对差动线进行传送。有限脉冲响应(FIR)滤波器12进行传送的等化，再进入驱动器13。数据经由通道14(例如单一线或一对差动线)予以传送，再由等化器(equalizer,EQ)15接收并处理，以降低符间干扰(intersymbol interference,ISI)。数据时脉回复电路(CDR)16接着处理数据流，再由解串化器(deserializer,DES)17将数据流转换为并列数据格式。The use of wired communication systems is closely related and inseparable to people. FIG. 1 shows a block diagram of a current common wireline communication system 100 for transmitting and receiving data. A serializer (serializer, SER) 11 converts data into a serial data stream, which is transmitted via a single line or a pair of differential lines. A finite impulse response (FIR) filter 12 performs the equalization of the transmission before entering the driver 13 . Data is transmitted through a channel 14 (such as a single line or a pair of differential lines), and then received and processed by an equalizer (EQ) 15 to reduce intersymbol interference (ISI). A data clock recovery circuit (CDR) 16 then processes the data stream, and then a deserializer (DES) 17 converts the data stream into a parallel data format.
功率消耗与阻抗匹配是设计有线通讯系统100的传送器的重要考虑因素。蓝哥·史瑞多耶维克(Ranko Sredojevic)等人在电机电子工程师学会(IEEE)国际固态电路会议(ISSCC)2010提出“使用动态驱动器阻抗调变的数字链路预加强(Digital Link Pre-emphasis with Dynamic Driver Impedance Modulation)”，其揭示一种数字推拉式(push-pull)阻抗调变(RM)预加强驱动器，克服电压模式驱动器在等化时的功率消耗，以增进输出级的效能。当数据样式为“11111…”或“00000…”时，将具阻抗的差动路径予以短路。由于没有短路电流，因此功率的消耗几乎为固定的。然而，功率的消耗仍有改善的空间。Power consumption and impedance matching are important considerations in designing the transmitter of the wired communication system 100 . Ranko Sredojevic and others proposed "Digital Link Pre-emphasis Using Dynamic Driver Impedance Modulation (Digital Link Pre- emphasis with Dynamic Driver Impedance Modulation), which discloses a digital push-pull (push-pull) impedance modulation (RM) pre-emphasis driver, which overcomes the power consumption of the voltage mode driver during equalization to improve the performance of the output stage. When the data pattern is "11111..." or "00000...", the differential path with impedance is short-circuited. Since there is no short-circuit current, the power consumption is almost constant. However, there is still room for improvement in power consumption.
蓝哥·史瑞多耶维克(Ranko Sredojevic)等人在电机电子工程师学会(IEEE)固态电路期刊(JSSC)2011提出“使用动态阻抗调变的全数字传送等化器(Fully DigitalTransmit Equalizer with Dynamic Driver Impedance Modulation)”，其揭示一种数字推拉式阻抗调变驱动器。当数据样式为“11111…”或“00000…”时，增加阻抗以降低功率消耗。借此，电压模式功率随输出电压的不同而不同。然而，其阻抗匹配并不理想。Ranko Sredojevic and others proposed "Fully Digital Transmit Equalizer with Dynamic Impedance Modulation (Fully Digital Transmit Equalizer with Dynamic Driver Impedance Modulation), which discloses a digital push-pull impedance modulation driver. When the data pattern is "11111..." or "00000...", increase the impedance to reduce power consumption. By this, the voltage mode power varies with the output voltage. However, its impedance matching is not ideal.
鉴于传统传送器无法有效降低功率消耗且增进阻抗匹配，因此急需提出一种新颖的传送器，以改进传统传送器的缺点。Since the traditional transmitter cannot effectively reduce power consumption and improve impedance matching, it is urgent to propose a novel transmitter to improve the shortcomings of the traditional transmitter.
有鉴于上述现有的传送器存在的缺陷，本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识，积极加以研究创新，以期创设一种新型结构的双二元电压模式传送器，能够改进一般现有的传送器，使其更具有实用性。经过不断的研究、设计,并经反复试作样品及改进后，终于创设出确具实用价值的本发明。In view of the defects of the above-mentioned existing transmitters, the inventor actively researches and innovates on the basis of years of rich practical experience and professional knowledge engaged in the design and manufacture of such products, in order to create a dual-binary voltage mode transmitter with a new structure , can improve the general existing transmitters to make them more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.
发明内容Contents of the invention
本发明的目的在于，克服现有的传送器存在的缺陷，而提供一种新型结构的双二元电压模式传送器，所要解决的技术问题是当双二元信号为中间位准时，使其关闭驱动器可以节省功率消耗并可增进阻抗匹配，从而更加适于实用。The purpose of the present invention is to overcome the existing defects of the existing transmitter and provide a dual binary voltage mode transmitter with a new structure. The technical problem to be solved is to make the dual binary signal close The driver can save power consumption and improve impedance matching, so it is more suitable for practical use.
本发明的目的及解决其技术问题是采用以下的技术方案来实现的。依据本发明提出的一种双二元电压模式传送器，包含：第一分支、第二分支及第一匹配电路。该第一分支包含第一逻辑电路、第一驱动器，第一逻辑电路接受多数个非归零信号，并侦测所述非归零信号的相位变化，第一驱动器受控于该第一逻辑电路的至少一输出，用以产生一双二元信号。该第二分支包含第二逻辑电路、第二驱动器，第二逻辑电路接收多数个互补非归零信号，其互补于该第一逻辑电路所接收的所述非归零信号，并侦测所述互补非归零信号的相位变化，第二驱动器受控于该第二逻辑电路的至少一输出。该第一匹配电路的二端分别耦接至该第一驱动器、该第二驱动器的输出端，其中该第一匹配电路可根据该第一逻辑电路或该第二逻辑电路的输出而切换。当所述非归零信号有相位变化，则该第一匹配电路被切换闭合，使得该第一匹配电路的二端分别电性耦接至该第一驱动器、该第二驱动器的输出端，且该第一驱动器、该第二驱动器关闭。The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A double binary voltage mode transmitter according to the present invention includes: a first branch, a second branch and a first matching circuit. The first branch includes a first logic circuit and a first driver. The first logic circuit receives a plurality of non-return-to-zero signals and detects phase changes of the non-return-to-zero signals. The first driver is controlled by the first logic circuit. At least one output of is used to generate a pair of binary signals. The second branch includes a second logic circuit and a second driver. The second logic circuit receives a plurality of complementary non-return-to-zero signals, which are complementary to the non-return-to-zero signals received by the first logic circuit, and detects the The phase change of the complementary non-return-to-zero signal, the second driver is controlled by at least one output of the second logic circuit. Two terminals of the first matching circuit are respectively coupled to output terminals of the first driver and the second driver, wherein the first matching circuit can be switched according to the output of the first logic circuit or the second logic circuit. When the phase of the non-return-to-zero signal changes, the first matching circuit is switched and closed, so that the two terminals of the first matching circuit are electrically coupled to the output terminals of the first driver and the second driver, respectively, and The first driver and the second driver are turned off.
本发明的目的以及解决其技术问题还可以采用以下的技术措施来进一步实现。前述的双二元电压模式传送器，其中所述的第一逻辑电路或第二逻辑电路所接收的所述非归零信号包含目前非归零信号及至少一先前非归零信号。The object of the present invention and the solution to its technical problems can also be further realized by adopting the following technical measures. In the aforementioned dual binary voltage mode transmitter, the NRZ signal received by the first logic circuit or the second logic circuit includes a current NRZ signal and at least one previous NRZ signal.
前述的双二元电压模式传送器，其中所述的双二元信号具有三个可能位阶—“0”、“1”及“2”，以正电压代表“2”，以负电压或地代表“0”，使用介于中间的电压代表“1”。The aforementioned dual binary voltage mode transmitter, wherein said dual binary signal has three possible levels - "0", "1" and "2", with positive voltage representing "2" and negative voltage or ground Represents "0" and uses an intermediate voltage to represent "1".
前述的双二元电压模式传送器，其中当所述的非归零信号有相位改变，则该第一驱动器及该第二驱动器产生双二元信号“1”；否则，当目前非归零信号为“1”，则该第一驱动器及该第二驱动器产生双二元信号“2”，或者当目前非归零信号为“0”，则该第一驱动器及该第二驱动器产生双二元信号“0”。The aforementioned dual binary voltage mode transmitter, wherein when the phase of the non-return-to-zero signal changes, the first driver and the second driver generate a dual binary signal "1"; otherwise, when the current non-return-to-zero signal is "1", the first driver and the second driver generate a double binary signal "2", or when the current non-return-to-zero signal is "0", the first driver and the second driver generate a double binary Signal "0".
前述的双二元电压模式传送器，其中所述的第一匹配电路包含串接的第一匹配电阻、第二匹配电阻与第一开关。In the aforementioned dual binary voltage mode transmitter, the first matching circuit includes a first matching resistor, a second matching resistor and a first switch connected in series.
前述的双二元电压模式传送器，其中当所述的第一开关闭合时，该第一匹配电阻与该第二匹配电阻的整体电阻匹配于传输通道的阻抗。In the aforementioned dual binary voltage mode transmitter, when the first switch is closed, the overall resistance of the first matching resistor and the second matching resistor matches the impedance of the transmission channel.
前述的双二元电压模式传送器，其中当所述的非归零信号有相位改变，则该第一开关闭合。In the aforementioned dual binary voltage mode transmitter, when the phase of the non-return-to-zero signal changes, the first switch is closed.
前述的双二元电压模式传送器，其中所述的第一驱动器或第二驱动器包含第一晶体管及第二晶体管，串接于电源与地之间。In the aforementioned dual binary voltage mode transmitter, the first driver or the second driver includes a first transistor and a second transistor connected in series between the power supply and the ground.
前述的双二元电压模式传送器，其中所述的第一晶体管的源极电性耦接至该第二晶体管的漏极。In the aforementioned dual binary voltage mode transmitter, the source of the first transistor is electrically coupled to the drain of the second transistor.
前述的双二元电压模式传送器，其中所述的第一逻辑电路接收目前非归零信号与先前非归零信号，据以产生第一输出信号及第二输出信号，用以分别控制该第一晶体管与该第二晶体管的栅极；且该第一逻辑电路根据目前非归零信号与先前非归零信号以产生第三输出信号，用以控制该第一开关。In the aforementioned dual binary voltage mode transmitter, wherein the first logic circuit receives the current non-return-to-zero signal and the previous non-return-to-zero signal, and generates a first output signal and a second output signal accordingly to control the first A transistor and a gate of the second transistor; and the first logic circuit generates a third output signal according to the current non-return-to-zero signal and the previous non-return-to-zero signal for controlling the first switch.
前述的双二元电压模式传送器，更包含：The aforementioned dual binary voltage mode transmitter further includes:
第一延迟元件；a first delay element;
第三驱动器，串接于该第一延迟元件之后，其中串接的该第一延迟元件、该第三驱动器再与该第一驱动器并接；The third driver is connected in series after the first delay element, wherein the first delay element and the third driver connected in series are connected in parallel with the first driver;
第二延迟元件；a second delay element;
第四驱动器，串接于该第二延迟元件之后，其中串接的该第二延迟元件、该第四驱动器再与该第二驱动器并接；及第二匹配电路，并接于该第一匹配电路；The fourth driver is connected in series after the second delay element, wherein the second delay element and the fourth driver connected in series are connected in parallel with the second driver; and a second matching circuit is connected in parallel with the first matching circuit. circuit;
当所述非归零信号有相位变化，则该第二匹配电路被切换闭合，使得该第二匹配电路的二端分别电性耦接至该第三驱动器、该第四驱动器的输出端，且该第三驱动器、该第四驱动器关闭。When the phase of the non-return-to-zero signal changes, the second matching circuit is switched on, so that the two terminals of the second matching circuit are electrically coupled to the output terminals of the third driver and the fourth driver, respectively, and The third driver and the fourth driver are turned off.
前述的双二元电压模式传送器，其中所述的第二匹配电路包含串接的第三匹配电阻、第四匹配电阻与第二开关。In the aforementioned dual binary voltage mode transmitter, the second matching circuit includes a third matching resistor, a fourth matching resistor and a second switch connected in series.
前述的双二元电压模式传送器，其中当所述的第二开关闭合时，该第三匹配电阻与该第四匹配电阻的整体电阻匹配于传输通道的阻抗。In the aforementioned dual binary voltage mode transmitter, when the second switch is closed, the overall resistance of the third matching resistor and the fourth matching resistor matches the impedance of the transmission channel.
前述的双二元电压模式传送器，其中当两个所述的先前非归零信号有相位改变，则该第二开关闭合。In the aforementioned dual binary voltage mode transmitter, the second switch is closed when the two preceding non-return-to-zero signals have a phase change.
前述的双二元电压模式传送器，其中所述的第三驱动器或第四驱动器包含第三晶体管及第四晶体管，串接于电源与地之间。In the aforementioned dual binary voltage mode transmitter, the third driver or the fourth driver includes a third transistor and a fourth transistor connected in series between the power supply and the ground.
前述的双二元电压模式传送器，其中所述的第三晶体管的源极电性耦接至该第四晶体管的漏极。In the aforementioned dual binary voltage mode transmitter, the source of the third transistor is electrically coupled to the drain of the fourth transistor.
前述的双二元电压模式传送器，其中所述的第一逻辑电路接收先前非归零信号与二延迟时间的先前非归零信号，据以产生第四输出信号及第五输出信号，用以分别控制该第三晶体管与该第四晶体管的栅极；且该第一逻辑电路根据先前非归零信号与二延迟时间的先前非归零信号以产生第六输出信号，用以控制该第二开关。In the aforementioned double binary voltage mode transmitter, wherein the first logic circuit receives the previous non-return-to-zero signal and the previous non-return-to-zero signal of two delay times, and generates the fourth output signal and the fifth output signal accordingly, for respectively controlling the gates of the third transistor and the fourth transistor; and the first logic circuit generates a sixth output signal according to the previous non-return-to-zero signal and the previous non-return-to-zero signal of two delay times for controlling the second switch.
本发明与现有技术相比具有明显的优点和有益效果。借由上述技术方案,本发明双二元电压模式传送器可达到相当的技术进步性及实用性，并具有产业上的广泛利用价值，其至少具有下列优点：根据本发明实施例，双二元电压模式传送器包含第一分支、第二分支及第一匹配电路。第一分支包含第一逻辑电路与第一驱动器。其中，第一逻辑电路接收多数个非归零信号，并侦测所述非归零信号的相位变化。第一驱动器受控于第一逻辑电路的至少一输出，用以产生一双二元信号。第二分支包含第二逻辑电路与第二驱动器。其中，第二逻辑电路接收多数个互补非归零信号，其互补于第一逻辑电路所接收之所述非归零信号，并侦测所述互补非归零信号的相位变化。第二驱动器受控于第二逻辑电路的至少一输出。第一匹配电路的二端分别耦接至第一驱动器、第二驱动器的输出端，其中第一匹配电路可根据第一逻辑电路或第二逻辑电路的输出而切换。当所述非归零信号有相位变化，则第一匹配电路被切换闭合，使得第一匹配电路的二端分别电性耦接至第一驱动器、第二驱动器的输出端，且第一驱动器、第二驱动器关闭，达到节省功率并增进阻抗匹配，克服传统传送器无法有效降低功率消耗且增进阻抗匹配的缺陷。Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the dual binary voltage mode transmitter of the present invention can achieve considerable technical progress and practicability, and has wide industrial application value. It has at least the following advantages: According to the embodiment of the present invention, the dual binary The voltage mode transmitter includes a first branch, a second branch and a first matching circuit. The first branch includes a first logic circuit and a first driver. Wherein, the first logic circuit receives a plurality of non-return-to-zero signals, and detects phase changes of the non-return-to-zero signals. The first driver is controlled by at least one output of the first logic circuit to generate a dual binary signal. The second branch includes a second logic circuit and a second driver. Wherein, the second logic circuit receives a plurality of complementary NRZ signals, which are complementary to the NRZ signals received by the first logic circuit, and detects phase changes of the complementary NRZ signals. The second driver is controlled by at least one output of the second logic circuit. The two terminals of the first matching circuit are respectively coupled to the output terminals of the first driver and the second driver, wherein the first matching circuit can be switched according to the output of the first logic circuit or the second logic circuit. When the non-return-to-zero signal has a phase change, the first matching circuit is switched on and closed, so that the two terminals of the first matching circuit are electrically coupled to the output terminals of the first driver and the second driver respectively, and the first driver, the second driver The second driver is turned off to save power and improve impedance matching, which overcomes the defects that traditional transmitters cannot effectively reduce power consumption and improve impedance matching.
综上所述，本发明是有关于一种双二元电压模式传送器，包含第一分支、第二分支及第一匹配电路。该第一分支包含第一逻辑电路与第一驱动器。该第二分支包含第二逻辑电路与第二驱动器。当非归零信号有相位变化时，该第一匹配电路的二端分别电性耦接至该第一驱动器、该第二驱动器的输出端，且该第一驱动器、该第二驱动器关闭，达到节省功率消耗并增进阻抗匹配的目的。To sum up, the present invention relates to a dual binary voltage mode transmitter, which includes a first branch, a second branch and a first matching circuit. The first branch includes a first logic circuit and a first driver. The second branch includes a second logic circuit and a second driver. When the non-return-to-zero signal has a phase change, the two terminals of the first matching circuit are electrically coupled to the output terminals of the first driver and the second driver respectively, and the first driver and the second driver are turned off to achieve The purpose of saving power consumption and improving impedance matching.
上述说明仅是本发明技术方案的概述，为了能更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例,并配合附图，详细说明如下。The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows.
附图说明Description of drawings
图1是有线通讯系统的方框图。Fig. 1 is a block diagram of a wired communication system.
图2是本发明实施例的双二元电压模式传送器的方框图。FIG. 2 is a block diagram of a dual binary voltage mode transmitter according to an embodiment of the present invention.
图3是非归零信号与双二元信号的时序图。FIG. 3 is a timing diagram of a non-return-to-zero signal and a double binary signal.
图4A至图4B是图2的双二元电压模式传送器。4A-4B are dual binary voltage mode transmitters of FIG. 2 .
图5A是图2的传送器的部分电路图。FIG. 5A is a partial circuit diagram of the transmitter of FIG. 2 .
图5B是图2的第一逻辑电路的电路图。FIG. 5B is a circuit diagram of the first logic circuit of FIG. 2 .
图6是本发明另一实施例的具等化的双二元电压模式传送器的方框图。FIG. 6 is a block diagram of an equalized dual binary voltage mode transmitter according to another embodiment of the present invention.
图7A至图7D是图6的双二元电压模式传送器。7A-7D are dual binary voltage mode transmitters of FIG. 6 .
图8A是图6的传送器的部分电路图。FIG. 8A is a partial circuit diagram of the transmitter of FIG. 6 .
图8B是图6的第一逻辑电路的电路图。FIG. 8B is a circuit diagram of the first logic circuit of FIG. 6 .
【符號說明】【Symbol Description】
100：有线通讯系统 11：串化器100: wired communication system 11: serializer
12：有限脉冲响应滤波器 13：驱动器12: Finite impulse response filter 13: Driver
14：通道 15：等化器14: Channel 15: Equalizer
16：数据时脉回复电路 17：解串化器16: Data clock recovery circuit 17: Deserializer
200：传送器 600：传送器200: Teleporter 600: Teleporter
21：第一分支 211：第一非归零产生器21: The first branch 211: The first non-return-to-zero generator
212：第一逻辑电路 213：第一驱动器212: first logic circuit 213: first driver
214：第一延迟元件 215：第三驱动器214: first delay element 215: third driver
22：第二分支 221：第二非归零产生器22: The second branch 221: The second non-return-to-zero generator
222：第二逻辑电路 223：第二驱动器222: second logic circuit 223: second driver
224：第二延迟元件 225：第四驱动器224: second delay element 225: fourth driver
23：第一匹配电路 24：传输通道23: First matching circuit 24: Transmission channel
25：第二匹配电路 31：周期25: Second matching circuit 31: Cycle
32：周期 33：周期32: Cycle 33: Cycle
R1：第一匹配电阻 R2：第二匹配电阻R1: the first matching resistor R2: the second matching resistor
R3：第三匹配电阻 R4：第四匹配电阻R3: The third matching resistor R4: The fourth matching resistor
SW1：第一开关 SW2：第二开关SW1: First switch SW2: Second switch
M1：第一晶体管 M2：第二晶体管M1: first transistor M2: second transistor
M3：第三晶体管 M4：第四晶体管M3: third transistor M4: fourth transistor
X[n]：目前非归零信号 X[n-1]：先前非归零信号X[n]: current non-return-to-zero signal X[n-1]: previous non-return-to-zero signal
X[n-2]：二延迟时间的先前非归零信号 Y[n]：第一输出信号X[n-2]: previous non-return-to-zero signal of two delay times Y[n]: first output signal
Y[n-1]：第四输出信号 Yb[n]：第二输出信号Y[n-1]: Fourth output signal Yb[n]: Second output signal
Yb[n-1]：第五输出信号 G[n]：第三输出信号Yb[n-1]: fifth output signal G[n]: third output signal
G[n-1]：第六输出信号G[n-1]: sixth output signal
具体实施方式detailed description
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的双二元电压模式传送器其具体实施方式、结构、特征及其功效，详细说明如后。In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation, structure and characteristics of the double binary voltage mode transmitter proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. And its effect, detailed description is as follows.
图2显示本发明实施例的双二元(duobinary)电压模式传送器(以下简称为传送器)200的方框图。本实施例的传送器200包含二个分支-第一分支21与第二分支22。在第一分支21，第一非归零(non-return-to-zero,NRZ)产生器211产生非归零信号，符合二阶非归零码的格式，其为一种二元码，以正电压代表位阶“1”，以负电压(或地)代表位阶“0”，两者间没有其他中性或静止状态。类似的情形，在第二分支22，第二非归零产生器221产生非归零信号(符合二阶非归零码的格式)，其互补于第一非归零产生器211所产生的非归零信号。FIG. 2 shows a block diagram of a duobinary voltage mode transmitter (hereinafter simply referred to as a transmitter) 200 according to an embodiment of the present invention. The conveyor 200 of this embodiment includes two branches—a first branch 21 and a second branch 22 . In the first branch 21, a first non-return-to-zero (NRZ) generator 211 generates a non-return-to-zero signal, which conforms to the format of a second-order non-return-to-zero code, which is a binary code, with A positive voltage represents a "1" level, a negative voltage (or ground) represents a "0" level, and there is no other neutral or static state in between. In a similar situation, in the second branch 22, the second NRZ generator 221 generates a NRZ signal (conforming to the format of the second-order NRZ code), which is complementary to the NRZ signal generated by the first NRZ generator 211. Zero signal.
第一分支21包含第一逻辑电路212，其接收第一非归零产生器211所产生的非归零信号，并侦测所述非归零信号之间的相变，产生输出以控制后续的电路。第一逻辑电路212所接收的非归零信号包含目前非归零信号及至少一先前(或延迟)非归零信号。类似的情形，第二分支22包含第二逻辑电路222，其接收第二非归零产生器221所产生的非归零信号，并侦测所述非归零信号之间的相变，产生输出以控制后续的电路。第二逻辑电路222所接收的非归零信号包含目前非归零信号及至少一先前非归零信号。The first branch 21 includes a first logic circuit 212, which receives the non-return-to-zero signal generated by the first non-return-to-zero generator 211, detects the phase change between the non-return-to-zero signals, and generates an output to control the subsequent circuit. The NRZ signal received by the first logic circuit 212 includes a current NRZ signal and at least one previous (or delayed) NRZ signal. In a similar situation, the second branch 22 includes a second logic circuit 222, which receives the non-return-to-zero signal generated by the second non-return-to-zero generator 221, detects the phase change between the non-return-to-zero signals, and generates an output to control subsequent circuits. The NRZ signal received by the second logic circuit 222 includes a current NRZ signal and at least one previous NRZ signal.
请参阅图2，第一分支21还可包含第一驱动器213，接收非归零信号并受控于第一逻辑电路212的输出，因而产生双二元信号，其具有三个可能位阶—“0”、“1”及“2”。例如，以正电压代表“2”，以负电压(或地)代表“0”，使用介于中间的电压代表“1”。详而言之，如果非归零信号的相位改变，例如从“1”至“0”或从“0”至“1”，则第一驱动器213产生双二元信号“1”；否则，当非归零信号为“1”，第一驱动器213产生双二元信号“2”，或者当非归零信号为“0”，第一驱动器213产生双二元信号“0”。图3例示非归零信号与双二元信号的时序图。双二元数据格式的细节可参阅珠立·李(Jri Lee)等人在电机电子工程师学会(IEEE)固态电路期刊(JSSC)2008提出“双二元、脉波振幅调变4及非归零数据的三种20-Gb/s底板收发器的设计与比较(Design and Comparison of Three 20-GB/s Backplane Transceivers forDuobinary,PAM4,and NRZ Data)”。类似的情形，第二分支22还可包含第二驱动器223，接收非归零信号并受控于第二逻辑电路222的输出，因而产生双二元信号。Please refer to FIG. 2, the first branch 21 may also include a first driver 213, which receives a non-return-to-zero signal and is controlled by the output of the first logic circuit 212, thereby generating a double binary signal, which has three possible levels—" 0", "1" and "2". For example, "2" is represented by a positive voltage, "0" is represented by a negative voltage (or ground), and a "1" is represented by an intermediate voltage. In detail, if the phase of the NRZ signal changes, for example from "1" to "0" or from "0" to "1", the first driver 213 generates a double binary signal "1"; otherwise, when When the NRZ signal is “1”, the first driver 213 generates a dual binary signal “2”, or when the NRZ signal is “0”, the first driver 213 generates a dual binary signal “0”. FIG. 3 illustrates a timing diagram of a non-return-to-zero signal and a dual binary signal. The details of the double binary data format can be found in "Double Binary, Pulse Amplitude Modulation 4 and Non-Return-to-Zero Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data (Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data)". In a similar situation, the second branch 22 may further include a second driver 223 for receiving the non-return-to-zero signal and controlled by the output of the second logic circuit 222 to generate a dual binary signal.
第一匹配电路23的二端分别电性耦接在第一驱动器213与第二驱动器223的输出端。第一匹配电路23可表示为串接的第一匹配电阻R1、第二匹配电阻R2与第一开关SW1。当第一开关SW1闭合时，第一匹配电阻R1与第二匹配电阻R2的整体电阻大致相同于传输通道24的阻抗，因而达到阻抗的匹配。Two terminals of the first matching circuit 23 are electrically coupled to the output terminals of the first driver 213 and the second driver 223 respectively. The first matching circuit 23 can be represented as a first matching resistor R1 , a second matching resistor R2 and a first switch SW1 connected in series. When the first switch SW1 is closed, the overall resistance of the first matching resistor R1 and the second matching resistor R2 is substantially the same as the impedance of the transmission channel 24 , thus achieving impedance matching.
根据本实施例的特征之一，当(目前与先前)非归零信号之间的相位有改变，或者说，当目前周期的双二元信号为中间位阶(亦即“1”)，则第一开关SW1闭合，且第一驱动器213与第二驱动器223可关闭(如图3所示的周期31、32及33)，以节省功率消耗。否则，第一开关SW1断开，且第一驱动器213与第二驱动器223为开启。图4A例示图2的双二元电压模式传送器200，由于目前周期未有相位的改变，因此第一开关SW1断开，且第一驱动器213与第二驱动器223为开启。图4B例示图2的双二元电压模式传送器200，由于目前周期有相位的改变，因此第一开关SW1闭合，且第一驱动器213与第二驱动器223为关闭，如虚线所示。According to one of the features of this embodiment, when the phase between the (current and previous) non-return-to-zero signals has changed, or in other words, when the current period of the dual binary signal is at an intermediate level (ie "1"), then The first switch SW1 is closed, and the first driver 213 and the second driver 223 can be turned off (periods 31 , 32 and 33 as shown in FIG. 3 ) to save power consumption. Otherwise, the first switch SW1 is turned off, and the first driver 213 and the second driver 223 are turned on. FIG. 4A illustrates the dual binary voltage mode transmitter 200 in FIG. 2 . Since there is no phase change in the current cycle, the first switch SW1 is turned off, and the first driver 213 and the second driver 223 are turned on. FIG. 4B illustrates the dual binary voltage mode transmitter 200 in FIG. 2 . Since the current cycle has a phase change, the first switch SW1 is closed, and the first driver 213 and the second driver 223 are turned off, as shown by the dotted line.
图5A显示图2的传送器200的部分电路图，且图5B显示图2的第一逻辑电路212的电路图。在本实施例中，第一驱动器213包含第一晶体管M1(例如N型晶体管)及第二晶体管M2(例如N型晶体管)，串接于电源与地之间。第一晶体管M1的源极电性耦接至第二晶体管M2的漏极。第一逻辑电路212(图5B)接收目前非归零信号X[n]与先前非归零信号X[n-1]，据以产生第一输出信号Y[n]及第二输出信号Yb[n]，用以分别控制第一晶体管M1与第二晶体管M2的栅极。第一逻辑电路212还根据目前非归零信号X[n]与先前非归零信号X[n-1]以产生第三输出信号G[n]，用以控制第一开关SW1。FIG. 5A shows a partial circuit diagram of the transmitter 200 of FIG. 2 , and FIG. 5B shows a circuit diagram of the first logic circuit 212 of FIG. 2 . In this embodiment, the first driver 213 includes a first transistor M1 (such as an N-type transistor) and a second transistor M2 (such as an N-type transistor), which are connected in series between the power supply and the ground. The source of the first transistor M1 is electrically coupled to the drain of the second transistor M2. The first logic circuit 212 ( FIG. 5B ) receives the current non-return-to-zero signal X[n] and the previous non-return-to-zero signal X[n-1] to generate the first output signal Y[n] and the second output signal Yb[ n] for controlling the gates of the first transistor M1 and the second transistor M2 respectively. The first logic circuit 212 also generates a third output signal G[n] according to the current NRZ signal X[n] and the previous NRZ signal X[n−1] for controlling the first switch SW1.
图6显示本发明另一实施例的具等化的双二元电压模式传送器(以下简称为传送器)600的方框图。传送器600(图6)的架构类似于传送器200(图2)，因此，相同的元件使用相同的元件符号。传送器600在第一分支21还包含第一延迟元件214，后接第三驱动器215(其与第一延迟元件214串接)。第一延迟元件214具有一个元周期的延迟时间。第三驱动器215相关于等化(equalization,EQ)，因此也可称为等化(EQ)驱动器。串接的第一延迟元件214、第三驱动器215再与第一驱动器213并接。虽然仅例示一个等化驱动器215，然而，也可以使用多个等化驱动器，每1个等化驱动器相关于一个不同延迟时间的延迟元件。FIG. 6 shows a block diagram of an equalized dual binary voltage mode transmitter (hereinafter simply referred to as a transmitter) 600 according to another embodiment of the present invention. The architecture of the transmitter 600 (FIG. 6) is similar to that of the transmitter 200 (FIG. 2), and therefore, the same reference numbers are used for the same components. The transmitter 600 further includes a first delay element 214 in the first branch 21 followed by a third driver 215 (which is connected in series with the first delay element 214 ). The first delay element 214 has a delay time of one meta-cycle. The third driver 215 is related to equalization (EQ), so it can also be called an equalization (EQ) driver. The serially connected first delay element 214 and the third driver 215 are connected in parallel with the first driver 213 . Although only one equalization driver 215 is illustrated, multiple equalization drivers may also be used, and each equalization driver is associated with a delay element of a different delay time.
类似的情形，传送器600在第二分支22还包含第二延迟元件224，后接第四驱动器225(其与第二延迟元件224串接)。第二延迟元件224具有一个元周期的延迟时间。第四驱动器225相关于等化(EQ)，因此也可称为等化(EQ)驱动器。串接的第二延迟元件224、第四驱动器225再与第二驱动器223并接。虽然仅例示一个等化驱动器225，然而，也可以使用多个等化驱动器，每个等化驱动器相关于一个不同延迟时间的延迟元件。In a similar situation, the transmitter 600 further includes a second delay element 224 in the second branch 22 followed by a fourth driver 225 (which is connected in series with the second delay element 224 ). The second delay element 224 has a delay time of one meta-cycle. The fourth driver 225 is related to equalization (EQ), and thus may also be called an equalization (EQ) driver. The second delay element 224 and the fourth driver 225 connected in series are connected in parallel with the second driver 223 . Although only one equalization driver 225 is illustrated, however, multiple equalization drivers may be used, each equalization driver being associated with a delay element of a different delay time.
传送器600更包含第二匹配电路25，类似于第一匹配电路23，其二端分别电性耦接于第驱动器213与第二驱动器223的输出端。第二匹配电路25相关于等化，可表示为串接的第三匹配电阻R3、第四匹配电阻R4与第二开关SW2。虽然仅例示一个第二匹配电路25，然而也可使用多个与等化相关的匹配电路。当第二开关SW2闭合时，第三匹配电阻R3与第四匹配电阻R4的整体电阻相同于传输通道24的阻抗，因而达到阻抗的匹配。The transmitter 600 further includes a second matching circuit 25 , which is similar to the first matching circuit 23 , and its two terminals are electrically coupled to the output terminals of the first driver 213 and the second driver 223 respectively. The second matching circuit 25 is related to the equalization, and can be expressed as a third matching resistor R3 , a fourth matching resistor R4 and a second switch SW2 connected in series. Although only one second matching circuit 25 is exemplified, a plurality of equalization-related matching circuits may be used. When the second switch SW2 is closed, the overall resistance of the third matching resistor R3 and the fourth matching resistor R4 is equal to the impedance of the transmission channel 24 , thus achieving impedance matching.
根据本实施例的特征之一，第二匹配电路25与相应的第三驱动器215、第四驱动器225的操作方式类似于第一匹配电路23与相应的第一驱动器213、第二驱动器223的操作，不同的地方说明如下。当(二个先前)非归零信号之间的相位有改变，或者说，当先前周期的双二元信号为中间位阶(亦即“1”)，则第二开关SW2闭合，且第三驱动器215与第四驱动器225可关闭，可以节省功率消耗。否则，第二开关SW2断开，且第三驱动器215与第四驱动器225为开启。According to one of the characteristics of this embodiment, the operation of the second matching circuit 25 and the corresponding third driver 215 and the fourth driver 225 is similar to the operation of the first matching circuit 23 and the corresponding first driver 213 and the second driver 223 , the different places are described as follows. When there is a change in phase between the (two previous) non-return-to-zero signals, or when the previous cycle of the bi-binary signal is at an intermediate level (i.e. "1"), the second switch SW2 is closed, and the third The driver 215 and the fourth driver 225 can be turned off to save power consumption. Otherwise, the second switch SW2 is turned off, and the third driver 215 and the fourth driver 225 are turned on.
图7A例示图6的双二元电压模式传送器600，由于目前及先前周期未有相位的改变，因此第一开关SW1、第二开关SW2断开，且第一至第四驱动器213、215、223、225为开启。图7B例示图6的传送器600，由于目前周期有相位的改变，因此第一开关SW1闭合，且第一驱动器213、第二驱动器223为关闭；由于先前周期未有相位的改变，因此第二开关SW2断开，且第三驱动器215、第四驱动器225为开启。图7C例示图6的传送器600，由于目前及先前周期有相位的改变，因此第一开关SW1、第二开关SW2闭合，且第一至第四驱动器213、215、223、225为关闭。图7D例示图6的传送器600，由于目前周期未有相位的改变，因此第一开关SW1断开，且第一驱动器213、第二驱动器223为开启；由于先前周期有相位的改变，因此第二开关SW2闭合，且第三驱动器215、第四驱动器225为关闭。FIG. 7A illustrates the dual binary voltage mode transmitter 600 in FIG. 6. Since there is no phase change in the current and previous cycles, the first switch SW1 and the second switch SW2 are turned off, and the first to fourth drivers 213, 215, 223,225 are open. Fig. 7B illustrates the transmitter 600 in Fig. 6, because there is a phase change in the current cycle, the first switch SW1 is closed, and the first driver 213 and the second driver 223 are closed; since there is no phase change in the previous cycle, the second The switch SW2 is turned off, and the third driver 215 and the fourth driver 225 are turned on. FIG. 7C illustrates the transmitter 600 in FIG. 6 . Since the current and previous periods have phase changes, the first switch SW1 and the second switch SW2 are closed, and the first to fourth drivers 213 , 215 , 223 , 225 are closed. FIG. 7D illustrates the transmitter 600 in FIG. 6. Since there is no phase change in the current cycle, the first switch SW1 is turned off, and the first driver 213 and the second driver 223 are turned on; because there is a phase change in the previous cycle, the second The second switch SW2 is closed, and the third driver 215 and the fourth driver 225 are turned off.
图8A显示图6的传送器600的部分电路图，且图8B显示图6的第一逻辑电路212的电路图。在本实施例中，第一驱动器213的电路同于图5A所示。本实施例的第三驱动器215包含第三晶体管M3(例如N型晶体管)及第四晶体管M4(例如N型晶体管)，串接于电源与地之间。第三晶体管M3的源极电性耦接至第四晶体管M4的漏极。第一逻辑电路212(图8B)接收目前非归零信号X[n]与先前非归零信号X[n-1]，据以产生第一输出信号Y[n]及第二输出信号Yb[n]，用以分别控制第一晶体管M1与第二晶体管M2的栅极。此外，第一逻辑电路212(图8B)还接收先前非归零信号X[n-1]与二延迟时间的先前非归零信号X[n-2]，据以产生第四输出信号Y[n-1]及第五输出信号Yb[n-1]，用以分别控制第三晶体管M3与第四晶体管M4的栅极。第一逻辑电路212还根据先前非归零信号X[n-1]与二延迟时间的先前非归零信号X[n-2]以产生第六输出信号G[n-1]，用以控制第二开关SW2。FIG. 8A shows a partial circuit diagram of the transmitter 600 of FIG. 6 , and FIG. 8B shows a circuit diagram of the first logic circuit 212 of FIG. 6 . In this embodiment, the circuit of the first driver 213 is the same as that shown in FIG. 5A . The third driver 215 in this embodiment includes a third transistor M3 (such as an N-type transistor) and a fourth transistor M4 (such as an N-type transistor), which are connected in series between the power supply and the ground. The source of the third transistor M3 is electrically coupled to the drain of the fourth transistor M4. The first logic circuit 212 ( FIG. 8B ) receives the current non-return-to-zero signal X[n] and the previous non-return-to-zero signal X[n-1] to generate the first output signal Y[n] and the second output signal Yb[ n] for controlling the gates of the first transistor M1 and the second transistor M2 respectively. In addition, the first logic circuit 212 ( FIG. 8B ) also receives the previous non-return-to-zero signal X[n-1] and the previous non-return-to-zero signal X[n-2] of two delay times, so as to generate the fourth output signal Y[ n−1] and the fifth output signal Yb[n−1] are used to control the gates of the third transistor M3 and the fourth transistor M4 respectively. The first logic circuit 212 also generates a sixth output signal G[n-1] according to the previous non-return-to-zero signal X[n-1] and the previous non-return-to-zero signal X[n-2] of two delay times for controlling The second switch SW2.
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明,任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence still belong to the scope of the technical solutions of the present invention.
| Application Number | Priority Date | Filing Date | Title |
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| CN201410350132.7ACN105306100B (en) | 2014-07-22 | 2014-07-22 | Dual Binary Voltage Mode Transmitter |
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| CN201410350132.7ACN105306100B (en) | 2014-07-22 | 2014-07-22 | Dual Binary Voltage Mode Transmitter |
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| CN105306100A CN105306100A (en) | 2016-02-03 |
| CN105306100Btrue CN105306100B (en) | 2017-10-20 |
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| CN201410350132.7AActiveCN105306100B (en) | 2014-07-22 | 2014-07-22 | Dual Binary Voltage Mode Transmitter |
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