Carrier-board-level embedded packaging structure with UBM structure and manufacturing method thereofTechnical Field
The present invention relates to a circuit board package structure, and more particularly, to a carrier-level embedded package structure with an UBM (under bump metallization) structure and a method for fabricating the same.
Background
At present, wire bonding technology is commonly applied in the packaging process of semiconductor chips. For example, existing semiconductor IC packages typically employ wire bonding techniques to achieve interconnection between on-chip contact pads and package internal traces. However, these techniques have deficiencies, including:
1. the wire bonding technology is wire bonding connection based on a single chip, and multi-wire bonding aiming at multiple I/Opad (electrode) numbers on the single chip is asynchronous, and the process speed is slow.
2. By adopting the wire bonding technology and the technology of arranging the chip on the carrier plate, the thickness of the finally formed packaging structure is larger.
3. This form of packaging is costly.
In addition, the top electrode (bonding pad) of the semiconductor chip is usually an aluminum-based metal top layer, such as Al, AlSi, AlSiCu, etc., the aluminum-based metal material is easily corroded by acid and alkali solutions, and has poor compatibility with the chip embedded packaging process, but at present, the novel packaging method Flip-chip (Flip chip technology) widely applied to the semiconductor chip replaces WB gold wires used in the traditional packaging with bumps, so that the current transmission efficiency is improved, and the volume of the packaged and molded element is also significantly reduced.
Therefore, it is desirable to provide a novel semiconductor chip package structure and process to solve the above problems.
Disclosure of Invention
The invention aims to provide a carrier-board level embedded packaging structure with a UBM structure, which can effectively improve the compatibility problem of a semiconductor chip with an aluminum-based metal top layer and a carrier-board level semiconductor chip embedded packaging process.
In order to solve the above technical problem, a carrier-level embedded package structure with a UBM structure provided in one technical solution of the present invention includes:
a circuit board;
at least one opening or cavity for accommodating a semiconductor chip, which is arranged in the circuit board;
the electrode surface of the semiconductor chip is at least exposed from the second surface of the circuit board and is positioned on the same plane with the second surface of the circuit board or the lowest surface of the circuit board;
the packaging material is at least used for covering the first surface of the circuit board, the module alignment mark and filling the space which is not occupied by the chip in the opening or the cavity;
and a UBM structure correspondingly disposed over the electrode of the semiconductor chip.
In a preferred embodiment, the first surface of the circuit board is further provided with a module alignment mark, and the module alignment mark surface and the second surface of the circuit board respectively correspond to the highest surface and the lowest surface of the circuit board.
In a preferred embodiment, the circuit board has at least one opening or cavity per unit module area.
Further, at least one semiconductor chip is accommodated in a single opening or cavity in the unit module region.
In a preferred embodiment, the highest surface and the lowest surface of the opening or the cavity in the vertical direction are respectively the highest surface of the circuit board or the module alignment mark surface and the second surface of the circuit board or the lowest surface thereof, and the boundary of the opening or the cavity in the horizontal direction is the sidewall of the opening or the cavity of the circuit board between the first surface and the second surface, and the opening or the cavity includes a first space and a second space, wherein the first space is distributed between the first surface and the second surface of the circuit board, the second space is distributed between the first surface of the circuit board and the module alignment mark surface, and the sidewall of the first space is a continuous cross section of the circuit board between the first surface and the second surface of the circuit board, and the second space has no sidewall.
In a preferred embodiment, the semiconductor chip electrode is a top layer of an aluminum-based metal selected from, but not limited to, aluminum metal, aluminum-silicon alloy metal, aluminum-silicon-copper alloy metal, and other aluminum-containing alloy metals.
In a preferred embodiment, the UBM structure on the aluminum-based metal top layer of the semiconductor chip electrode includes a combination of, but is not limited to, an anti-diffusion metal layer and a conductive metal layer.
Further, the adhesion or diffusion-proof metal layer directly covers the aluminum-based metal top layer of the electrode, and the material of the adhesion or diffusion-proof metal layer can be selected from but not limited to nickel, titanium, nichrome, titanium tungsten alloy and the like; and the conductive metal layer directly covers the adhesion or diffusion-preventing metal layer, and the material of the conductive metal layer can be selected from, but is not limited to, copper, gold and the like.
In a preferred embodiment, the UBM structure on the aluminum-based metal top layer of the semiconductor chip electrode comprises a combination of electroless nickel and gold metal layers. The nickel metal layer is firstly deposited on the aluminum-based metal top layer of the electrode through a nickel melting process, and the gold metal layer is deposited on the nickel metal layer through a gold leaching process.
In a preferred embodiment, a UBM generation process is performed on the electrode of the semiconductor chip to form a UBM structure, and then an accumulation layer is covered on the second surface of the circuit board, the semiconductor chip and the surface of the packaging material coplanar with the second surface of the circuit board, and the accumulation layer above the UBM of the semiconductor chip is removed to form an opening.
Further, the build-up layer material may be selected from, but not limited to, ABF insulation, fiberglass-containing insulation, light-sensitive insulation.
Furthermore, a first circuit layer is arranged on the surface of the accumulation layer and is electrically connected with the UBM surface through the opening of the accumulation layer.
Further, the package structure may further include: and the welding mask is used for covering the accumulation layer and the first circuit layer on the accumulation layer.
Further, the package structure may further include: and the welding spot array is arranged in the welding mask opening covering the accumulation layer and the surface of the first circuit layer on the accumulation layer and is electrically connected with the first circuit layer, and the welding spot array comprises a ball grid array or a contact array.
In another technical solution adopted by the present invention, a carrier-level embedded package structure with a UBM structure includes:
a circuit board;
at least one opening or cavity for accommodating a semiconductor chip, which is arranged in the circuit board;
the electrode surface of the semiconductor chip is at least exposed from the second surface of the circuit board and is positioned on the same plane with the second surface of the circuit board or the lowest surface of the circuit board;
the packaging material is at least used for covering the first surface of the circuit board, the module alignment mark and filling the space which is not occupied by the chip in the opening or the cavity;
and a UBM structure correspondingly disposed over the electrode of the semiconductor chip.
In a preferred embodiment, the first surface of the circuit board is further provided with a module alignment mark, and the module alignment mark surface and the second surface of the circuit board respectively correspond to the highest surface and the lowest surface of the circuit board.
In a preferred embodiment, the circuit board has at least one opening or cavity per unit module area.
Further, at least one semiconductor chip is accommodated in a single opening or cavity in the unit module region.
In a preferred embodiment, the highest surface and the lowest surface of the opening or the cavity in the vertical direction are respectively the highest surface of the circuit board or the module alignment mark surface and the second surface of the circuit board or the lowest surface thereof, and the boundary of the opening or the cavity in the horizontal direction is the sidewall of the opening or the cavity of the circuit board between the first surface and the second surface, and the opening or the cavity includes a first space and a second space, wherein the first space is distributed between the first surface and the second surface of the circuit board, the second space is distributed between the first surface of the circuit board and the module alignment mark surface, and the sidewall of the first space is a continuous cross section of the circuit board between the first surface and the second surface of the circuit board, and the second space has no sidewall.
In a preferred embodiment, the semiconductor chip electrode is a top layer of an aluminum-based metal selected from, but not limited to, aluminum metal, aluminum-silicon alloy metal, aluminum-silicon-copper alloy metal, and other aluminum-containing alloy metals.
In a preferred embodiment, the UBM structure on the aluminum-based metal top layer of the semiconductor chip electrode includes a combination of, but is not limited to, an anti-diffusion metal layer and a conductive metal layer.
Further, the adhesion or diffusion-proof metal layer directly covers the aluminum-based metal top layer of the electrode, and the material of the adhesion or diffusion-proof metal layer can be selected from, but not limited to, nickel, titanium, nickel-chromium alloy, nickel-vanadium alloy, titanium-tungsten alloy and the like; and the conductive metal layer directly covers the adhesion or diffusion-preventing metal layer, and the material of the conductive metal layer can be selected from, but is not limited to, copper, gold and the like.
In a preferred embodiment, the UBM structure on the aluminum-based metal top layer of the semiconductor chip electrode comprises a combination of electroless nickel and gold metal layers. The nickel metal layer is firstly deposited on the aluminum-based metal top layer of the electrode through a nickel melting process, and the gold metal layer is deposited on the nickel metal layer through a gold leaching process.
In a preferred embodiment, the second surface of the circuit board, the semiconductor chip and the surface of the packaging material coplanar with the second surface are covered with at least one accumulation layer, the accumulation layer has an opening in the region above the electrode surface of the semiconductor chip, and the UBM structure is located on the electrode surface of the semiconductor chip and limited in the accumulation layer opening, and the UBM metal layer is in direct electrical contact with the aluminum-based metal top layer of the electrode.
Further, the build-up layer material may be selected from, but is not limited to, ABF insulation, fiberglass-containing insulation, light-sensitive insulation, and the like.
Furthermore, a first circuit layer is arranged on the surface of the accumulation layer and is electrically connected with the UBM surface through the opening of the accumulation layer.
Further, the package structure may further include: and the welding mask is used for covering the accumulation layer and the first circuit layer on the accumulation layer.
Further, the package structure may further include: and the welding spot array is arranged in the welding mask opening covering the accumulation layer and the surface of the first circuit layer on the accumulation layer and is electrically connected with the first circuit layer, and the welding spot array comprises a ball grid array or a contact array.
The invention also provides a method for manufacturing the carrier-board-level embedded packaging structure with the UBM structure, which comprises the following steps:
(1) providing a circuit board, wherein the circuit board is provided with at least one opening or cavity for accommodating a semiconductor chip, and a module alignment mark is arranged on the first surface of the circuit board at the periphery of an independently packaged module area or the periphery of an opening or cavity in an independently packaged sub-module;
(2) attaching an adhesive film on the second surface of the circuit board, placing the chip into the opening or the cavity, and adhering and fixing the surface of the semiconductor chip with the electrode with the adhesive film;
(3) applying an encapsulation material on at least the first surface of the circuit board, the module alignment mark and the opening or the cavity, so that the first surface of the circuit board and the module alignment mark are covered by the encapsulation material, and the opening or the cavity is completely filled by the encapsulation material and the semiconductor chip;
(4) removing the adhesive film and turning over the circuit board;
(5) covering more than one accumulation layer on the second surface of the circuit board, the semiconductor chip and the surface of the packaging material coplanar with the second surface of the circuit board, removing the accumulation layer above the electrode of the semiconductor chip to form an opening,
carrying out UBM generation process in the accumulation layer opening and on the electrode of the semiconductor chip to form a UBM structure;
or,
directly carrying out a UBM generation process on an electrode of the semiconductor chip to form a UBM structure, covering more than one accumulation layer on the second surface of the circuit board, the semiconductor chip, the UBM structure and the surface of the packaging material coplanar with the second surface of the circuit board, and removing the accumulation layer above the UBM of the semiconductor chip to form an opening;
(6) sequentially forming an anti-diffusion TiW metal layer and a copper layer on the accumulation layer on the surface of the UBM structure;
(7) processing and forming a first circuit layer on the accumulation layer;
(8) and arranging a welding mask on the accumulation layer and the first circuit layer on the accumulation layer, arranging a welding spot array in an opening of the welding mask covering the accumulation layer and the surface of the first circuit layer on the accumulation layer, and electrically connecting the welding spot array with the first circuit layer.
Further, the UBM generation process comprises the steps of:
(1) forming a nickel layer with the thickness of 5-15 mu m on the electrode of the semiconductor chip;
(2) and forming an Au layer with the thickness of 0.05-0.2 mu m on the nickel layer.
Compared with the prior art, the invention has at least the following advantages:
(1) the compatibility of the semiconductor chip with an electrode of aluminum-based metal (such as AlSi) and a carrier-grade semiconductor chip embedded packaging process is effectively improved through the UBM structure;
(2) the carrier plate level embedded packaging structure with the UBM structure has high production efficiency, excellent performance and low cost;
(3) the manufacturing process of the carrier plate level embedded packaging structure with the UBM structure is a carrier plate level packaging process with high production speed, and is obviously superior to a low-efficiency production process based on a single-chip bonding connection process.
Drawings
FIGS. 1 a-1 d are schematic diagrams of different types of modules with different openings or cavities on the circuit board and semiconductor chips accommodated therein;
FIG. 2 is a cross-sectional view of a substrate having an opening or cavity and a circuit board in accordance with a preferred embodiment of the present invention;
FIGS. 3 a-3 b are schematic views of a semiconductor chip placed in an opening or cavity with an electrode facing down according to a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of the device of FIG. 3b encapsulated in an encapsulating material;
FIG. 5 is a schematic view of the device of FIG. 4 with the adhesive film removed and inverted;
FIGS. 6 a-6 d are schematic diagrams of a preferred embodiment of disposing a nickel layer, an Au layer and an accumulation layer on the device of FIG. 5 and forming an accumulation layer opening;
FIGS. 7 a-7 b are schematic diagrams of a bond coat, Cu layer of NiCr or TiW disposed on the device of FIG. 6 d;
FIG. 8 is a schematic diagram of a preferred embodiment of forming a first line layer on the UBM structure of the device shown in FIG. 7 b;
FIGS. 9 a-9 b are schematic diagrams of another preferred embodiment of providing an accumulation layer and forming an accumulation layer opening on the device of FIG. 5;
FIGS. 10 a-10 d are schematic diagrams of the placement of a nickel layer, an Au, NiCr or TiW adhesion layer, and a Cu layer within the accumulation layer opening of the device of FIG. 9 b;
FIG. 11 is a schematic diagram of another preferred embodiment of forming a first line layer over the UBM structure of the device shown in FIG. 10 d;
12 a-12 b are schematic diagrams of the placement of a solder mask and an array of solder pads on the device of FIG. 8 or 11;
the parts in the drawings are numbered as follows: 1-circuit board, 11-first surface, 12-second surface, 2-opening or cavity, 21-first space, 22-second space, 3-semiconductor chip, 31-semiconductor chip electrode, 4-module alignment mark, 5-adhesive film, 6-packaging material, 7-accumulation layer, 71-accumulation layer opening, 8-UBM structure, 81-nickel layer, 82-Au layer, 83-adhesive layer of NiCr or TiW, 84-Cu layer, 9-first line layer, 100-welding mask, 101-welding mask opening, 102-welding spot array, L-transverse direction and V-longitudinal direction.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
One aspect of the present invention provides a carrier-board embedded package structure with a UBM structure, comprising:
the circuit board 1, i.e. a carrier for packaging ICs, comprises a first surface 11, a second surface 12;
at least one opening or cavity 2 disposed within the circuit board 1 for receiving a semiconductor chip 3; the circuit board 1 has at least one opening or cavity 2 in a unit module region, where at least one semiconductor chip 3 can be accommodated in one opening or cavity 2 in the unit module region, or more than two openings or cavities 2 in the unit module region can accommodate more than two semiconductor chips 3 respectively, and a surface of an electrode 31 of at least one semiconductor chip 3 is coplanar with the second surface 12 of the circuit board 1, please refer to fig. 1 a-1 d, fig. 12a, and the like;
the module alignment mark 4 is arranged on the first surface 11 of the circuit board 1, and the surface of the module alignment mark 4 and the second surface 12 of the circuit board 1 respectively correspond to the highest surface and the lowest surface of the circuit board 1; the module alignment mark 4 is used for realizing accurate flip chip arrangement and conductive circuit interconnection, and all marks or part of marks simultaneously become connecting circuits and provide a conductive function;
a semiconductor chip 3 disposed in the opening or cavity 2, wherein a surface of an electrode 31 of the chip 3 is exposed from at least the second surface 12 of the circuit board and is coplanar with the second surface 12 or the lowest surface of the circuit board 1; the semiconductor chip electrode 31 is an aluminum-based metal top layer, and the aluminum-based metal comprises aluminum metal, aluminum-silicon alloy metal, aluminum-silicon-copper alloy metal or other aluminum-containing alloy metal;
an encapsulation material 6 at least for covering the first surface 11 of the circuit board 1, the module alignment mark 4 and filling the space inside the opening or cavity 2 not occupied by the chip 3;
and a corresponding UBM structure 8 is provided above the electrode 31 of the semiconductor chip.
Wherein the highest surface and the lowest surface of the opening or cavity 2 in the vertical direction are the highest surface of the circuit board 1 or the module alignment mark 4 surface and the second surface 12 of the circuit board 1 or the lowest surface thereof, respectively, and the boundary of the opening or cavity 2 in the horizontal direction is the sidewall of the opening or cavity 2 of the circuit board 1 between the first surface 11 and the second surface 12, while the opening or cavity 2 includes a first space 21 and a second space 22, wherein the first space 21 is distributed between the first surface 11 and the second surface 12 of the circuit board 1, the second space 22 is distributed between the first surface 11 of the circuit board 1 and the module alignment mark 4 surface, and the sidewall of the first space 21 is a continuous cross section of the circuit board 1 between the first surface 11 and the second surface 12 of the circuit board, whereas said second space 21 has no side walls.
Further, the UBM structure 8 on the aluminum-based metal top layer of the semiconductor chip electrode 31 may be two metal layers of electroless nickel and gold, wherein the nickel metal layer is firstly deposited on the aluminum-based metal top layer of the electrode 31 by a nickel-plating process, and the gold metal layer is deposited on the nickel metal layer by a gold-dipping process.
Alternatively, the UBM structure 8 on the aluminum-based metal top layer of the semiconductor chip electrode 31 may be a two-layer metal structure of an adhesion or diffusion-proof metal layer and a conductive metal layer, but is not limited thereto.
Further, the adhesion or diffusion-proof metal layer is directly covered on the aluminum-based metal top layer of the electrode 31, and the material of the adhesion or diffusion-proof metal layer can be nickel, titanium, nichrome or titanium-tungsten alloy; and the conductive metal layer is directly covered with an adhesive or diffusion-preventing metal layer, which may be copper or gold.
In the carrier-board embedded package structure with the UBM structure, the second surface 12 of the circuit board 1, the semiconductor chip 3 and the surface of the packaging material 6 coplanar with the second surface 12 are covered with an accumulation layer 7, the accumulation layer 7 has an opening 71 in the region above the surface of the electrode 31 of the semiconductor chip 3, and the UBM structure 8 is located on the surface of the electrode 31 of the semiconductor chip 3 and is limited to be directly contacted with the accumulation layer opening 71, the UBM metal layer and the aluminum-based metal top layer of the electrode 31, so that the electrical intercommunication is realized. The material of the accumulation layer 7 is ABF insulating material, epoxy resin insulating material containing glass fiber, or light sensitive insulating material. A first line layer 9 is further disposed on the surface of the accumulation layer 7, and the first line layer 9 is electrically connected to the UBM surface through the opening 71 of the accumulation layer 7, and the first line layer 9 may also be referred to as RDL (redistribution layer).
Further, the carrier-board embedded package structure with the UBM structure may further include a solder mask 100 for covering the accumulation layer 7 and the first circuit layer 9 on the accumulation layer 7; also included is a solder joint array 102 disposed in a solder mask opening 101 covering the accumulation layer 7 and the surface of the first wiring layer 9 on the accumulation layer 7 and electrically connected to the accumulation layer 7, the solder joint array 102 including a ball grid array bga (ball grid array) or a contact array lga (landgrid array).
Another aspect of the present invention also provides a method for fabricating the carrier-board embedded package structure with the UBM structure, which can be implemented in various ways.
For example, one implementation may include the following steps:
(1) providing a circuit board 1, wherein the circuit board 1 is provided with at least one opening or cavity 2 for accommodating a semiconductor chip 3, and a module alignment mark 4 is arranged on a first surface 11 of the circuit board 1, around an individual carrier-board level package module region, or around the opening or cavity 2 in the individual carrier-board level package module, please refer to fig. 1 a-1 d and fig. 2;
(2) attaching an adhesive film 5 on the second surface 12 of the circuit board 1, placing the chip 3 into the opening or cavity 2 in an inverted manner, and adhering and fixing the electrode 31 of the chip 3 and the adhesive film 5, please refer to fig. 3a and fig. 3 b;
(3) applying an encapsulation material 6 at least on the first surface 11 of the circuit board 1, the module alignment mark 4 and the opening or cavity 2, so that the first surface 11 of the circuit board 1 and the module alignment mark 4 are covered by the encapsulation material 6, and the opening or cavity 2 is completely filled with the encapsulation material 6 and the chip 3, please refer to fig. 4;
in this step, the encapsulating material 6 may also be subjected to a planarization process.
The encapsulating material 6 may be a molding compound (molding compound), an epoxy resin, an epoxy/filler compound, or the like, which fills the cavity 2 and covers the first surface 11 as a flat stack layer.
(4) Removing the adhesive film 5 and turning over the circuit board 1, please refer to fig. 5;
(5) referring to fig. 6 a-6 d, nickel is chemically plated on the electrode 31 of the semiconductor chip 3, the thickness of the nickel layer 81 is 5-15 μm, Au is sputter deposited on the nickel layer 81, the thickness of the Au layer 82 is 0.05-0.2 μm, the second surface 12 of the circuit board 1, the semiconductor chip 3 and the surface of the packaging material 6 coplanar with the second surface 12 are covered with a layer of accumulation layer 7, the accumulation layer 7 above the semiconductor chip electrode 31 is removed to form an opening 71, and the form of the opening 71 includes laser drilling and photolithography;
(6) referring to FIGS. 7a to 7b, an adhesion layer 83 of NiCr or TiW is sputtered on the Au layer 82 and the opening 71 of the accumulation layer in the step (5), the thickness of the adhesion layer 83 is 50 to 100nm, a Cu layer 84 is formed by copper plating on the adhesion layer 83 of NiCr or TiW, and the thickness of the Cu layer 84 is 0.5 to 2 μm.
(7) Forming a first circuit layer 9, which may also be referred to as RDL (redistribution layer), on the accumulation layer 7, as shown in fig. 8, wherein the forming method includes dry film lamination, pattern exposure, development, copper plating, film removal, and copper etching; or copper plating, dry film lamination, pattern exposure, development, copper etching and film removal;
(8) a solder mask 100 is disposed on the accumulation layer 7 and the first circuit layer 9 on the accumulation layer 7, and a solder pad array 102 is disposed in a solder mask opening 101 covering the accumulation layer 7 and the surface of the first circuit layer 9 on the accumulation layer 7, and the solder pad array 102 is electrically connected to the first circuit layer 9, as shown in fig. 12 a-12 b. Here, the solder mask 100 may be formed by coating or compositing, photolithography, and annealing, and the solder pad array 102 may be formed by photolithography forming holes through the solder mask 100 on the first circuit layer 9, and embedding Ball Grid Array (BGA) or Land Grid Array (LGA) into the corresponding holes.
For another example, another implementation manner may include the following steps:
(1) providing a circuit board 1, wherein the circuit board 1 is provided with at least one opening or cavity 2 for accommodating a semiconductor chip, and a module alignment mark 4 is arranged on a first surface 11 of the circuit board, around an individual carrier-board level package module region, or around the opening or cavity in the individual carrier-board level package module, please refer to fig. 1 a-2;
(2) attaching an adhesive film 5 on the second surface 12 of the circuit board, placing the chip 3 into the opening or cavity 2 in an inverted manner, and adhering and fixing the surface of the chip 3 with the electrode 31 to the adhesive film 5, please refer to fig. 3 a-3 b;
(3) applying an encapsulation material 6 at least on the first surface 11 of the circuit board 1, the module alignment mark 4 and the opening or cavity 2, so that the first surface 11 of the circuit board 1 and the module alignment mark 4 are covered by the encapsulation material 6, and the opening or cavity 2 is completely filled with the encapsulation material 6 and the chip 3, please refer to fig. 4;
in this step, the encapsulating material 6 may also be subjected to a planarization process.
The encapsulating material 6 may be a molding compound (molding compound), an epoxy resin, an epoxy/filler compound, or the like, which fills the cavity 2 and covers the first surface 11 as a flat stack layer.
(4) Removing the adhesive film 5 and turning over the circuit board 1, please refer to fig. 5;
(5) covering a layer of accumulation layer 7 on the second surface 12 of the circuit board, the semiconductor chip 3 and the surface of the packaging material 6 coplanar with the second surface 12, and removing the accumulation layer 7 above the electrode 31 of the semiconductor chip to form an opening 71, wherein the form of the formed opening 71 includes laser drilling and photolithography, please refer to fig. 9 a-9 b;
(6) performing a UBM process on the accumulation layer opening 71 and the electrode 31 of the semiconductor chip 3 to form a UBM structure 8, please refer to fig. 10a to 10 d;
wherein the UBM process comprises the following steps:
(a) electroless nickel plating on the electrode 31 of the semiconductor chip 3, covering the whole of the semiconductor chip electrode 31 in the accumulation layer opening 71, wherein the thickness of the nickel layer 81 is 5-15 μm, as shown in FIG. 10 a;
(b) sputtering and depositing Au on the nickel layer 81 in the step (1), wherein the thickness of the Au layer 82 is 0.05-0.2 μm, as shown in FIG. 10 b;
(c) sputtering and depositing an adhesion layer 83 of NiCr or TiW on the Au layer 82 and the opening 71 of the accumulation layer 7 in the step (2), wherein the thickness of the adhesion layer 83 is 50-100 nm, as shown in FIG. 10 c;
(d) and (4) sputtering and depositing a Cu layer 84 on the NiCr or TiW bonding layer 83 in the step (3), wherein the thickness of the Cu layer 84 is 0.5-2 μm, as shown in FIG. 10 d.
(7) Forming a first circuit layer 9, which may also be referred to as RDL (redistribution layer), on the accumulation layer 7, as shown in fig. 11, the forming method includes dry film lamination, pattern exposure, development, copper plating, film removal, and copper etching; or copper plating, dry film lamination, pattern exposure, development, copper etching and film removal;
(8) a solder mask 100 is disposed on the accumulation layer 7 and the first circuit layer 9 on the accumulation layer 7, and a solder pad array 102 is disposed in a solder mask opening 101 covering the accumulation layer 7 and the surface of the first circuit layer 9 on the accumulation layer 7, so that the solder pad array 102 is electrically connected to the first circuit layer 9, please refer to fig. 12a and 12 b. Here, the solder mask 100 may be formed by coating, photolithography, development, exposure curing and baking, and the solder pad array 102 may be formed by photolithography forming a hole through the solder mask 100 on the first circuit layer 9, and embedding a Ball Grid Array (BGA) or a Land Grid Array (LGA) into the corresponding hole.
The invention effectively solves the compatibility problem of the embedded packaging process of the semiconductor chip 3 with the AlSi electrode and the carrier-grade semiconductor chip through the UBM structure.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.