技术领域technical field
本发明是有关于一种存储器装置及其制造方法，特别是指用于多阶三维叠层装置的内连接结构。The present invention relates to a memory device and its manufacturing method, in particular to an internal connection structure for a multi-level three-dimensional laminated device.
背景技术Background technique
在集成电路的制造中，某些工艺使用活化性离子(activated ions)。举例来说，包括金属刻蚀、光刻胶剥离，以及金属间介电质沉积等后端工艺，皆涉及等离子体，以在受处理晶粒内的结构感应电荷。此种在工艺期间对结构的充电被称为天线效应。In the manufacture of integrated circuits, certain processes use activated ions. For example, back-end processes including metal etch, photoresist stripping, and intermetal dielectric deposition all involve plasmas to induce charges in structures within the processed die. This charging of the structure during processing is known as the antenna effect.
天线效应感应的电荷可能损坏装置中的结构，包括影响装置效能的结构。举例来说，在存储器装置中，字线或其它相对较大的导电结构可以承受较大的天线效应的累积电荷。字线上的电荷累积可暴露闪存内的隧穿介电质、栅极介电质，以及多晶硅内的介电质，使其被累积电荷损坏。此外，使用在介电电荷储存单元的电荷储存结构特别容易受到此类损坏。Charges induced by antenna effects can damage structures in the device, including structures that affect device performance. For example, in a memory device, a word line or other relatively large conductive structure can sustain a large antenna effect of accumulated charge. The buildup of charge on the word line can expose the tunneling dielectric in the flash memory, the gate dielectric, and the dielectric in the polysilicon to damage from the accumulated charge. Furthermore, charge storage structures used in dielectric charge storage cells are particularly susceptible to such damage.
等离子体感应电荷可为正或负，此为其一特征，因其感应电荷的种类可产生不同类型的损坏。Plasma induced charges can be positive or negative, which is a characteristic, because different types of damage can be caused by the type of induced charge.
一种防止或减少天线效应的方法于在美国专利7,196,369中描述，发明名称为″PLASMA DAMAGE PROTECTION CIRCUIT FOR A SEMICONDUCTOR DEVICE″，发明人为Chou etal.。亦可参照美国专利7,317,633，发明名称为″PROTECTION OF NROM DEVICES FROMCHARGE DAMAGE″，发明人为Lusky et al.A method to prevent or reduce the antenna effect is described in US Patent No. 7,196,369, the title of the invention is "PLASMA DAMAGE PROTECTION CIRCUIT FOR A SEMICONDUCTOR DEVICE", and the inventor is Chou et al. You can also refer to US Patent 7,317,633, the title of the invention is "PROTECTION OF NROM DEVICES FROMCHARGE DAMAGE", and the inventor is Lusky et al.
已有报导指出等离子体充电效应在SONOS电荷捕获装置具有关键作用。多数的闪存产品采用PN二极管保护，或聚合物保险丝(poly fuse)保护。然而，这两种方法都有限制。对于PN二极管保护，字线WL的操作电压被限制在二极管的反向，且必须低于崩溃电压(breakdown voltage)。此外，PN二极管仅在崩溃电压之后提供保护，因此不能保护中程电压(medium-range voltages)。对于聚合物保险丝保护，则必须在测量之前使保险丝破裂。保险丝保护只适合小的测试装置，而不适合用于产品设计。此外，如果破裂偏差过大，也可能会干扰装置。It has been reported that the plasma charging effect plays a key role in SONOS charge trapping devices. Most flash memory products are protected by PN diodes or poly fuses. However, both methods have limitations. For PN diode protection, the operating voltage of the word line WL is limited to the reverse direction of the diode and must be lower than the breakdown voltage (breakdown voltage). In addition, PN diodes only provide protection after the breakdown voltage, so they cannot protect medium-range voltages. For polymer fuse protection, the fuse must be blown prior to measurement. Fuse protection is only suitable for small test setups, not for product design. In addition, if the rupture deviation is too large, it may also interfere with the device.
静电放电(electro static discharge，ESD)电路已设置在集成电路的探测垫中，以防止膨胀的外部电子脉冲损坏装置。然而，静电放电电路通常藉相对高的电压启用，不能提供中电压保护。Electrostatic discharge (ESD) circuits have been built into the probe pads of the integrated circuits to prevent the expanding external electrical pulses from damaging the device. However, ESD circuits are usually activated by relatively high voltages and cannot provide medium voltage protection.
因此，需要提供一种保护电路，可在集成电路的工艺中避免电荷损坏。此外，保护电路不应在工艺后影响装置运作。Therefore, there is a need to provide a protection circuit that can avoid charge damage in the process of integrated circuits. In addition, protection circuits should not affect device operation after processing.
发明内容Contents of the invention
有鉴于此，本发明实施例提供了一种天线效应放电电路，用于具有多个图案化导体的装置，图案化导体例如是图案化多晶硅层及金属层，且其在工艺中可能暴露在高能量等离子体或其它电荷感应环境。天线效应放电电路具有一端及一栅极，该端连接装置上的一节点，节点受保护以避免电荷累积，栅极例如是电路中场效应晶体管的栅极。一电容耦接在天线效应放电电路的栅极至基板。一电压供应电路用以提供电压，在装置的操作期间，此电压足够于关闭状态偏置天线效应放电电路。上层的一图案化导体(较佳为最上层)连接天线效应放电电路的栅极与电压供应电路。In view of this, an embodiment of the present invention provides an antenna effect discharge circuit for a device with multiple patterned conductors, such as patterned polysilicon layers and metal layers, which may be exposed to high Energy plasma or other charge-inducing environments. The antenna effect discharge circuit has a terminal connected to a node on the device, the node being protected from charge accumulation, and a gate, such as the gate of a field effect transistor of the circuit. A capacitor is coupled between the gate of the antenna effect discharge circuit and the substrate. A voltage supply circuit is used to provide a voltage sufficient to bias the antenna effect discharge circuit in an off state during operation of the device. A patterned conductor on the upper layer (preferably the uppermost layer) is connected to the gate of the antenna effect discharge circuit and the voltage supply circuit.
天线效应放电电路可包含场效应晶体管，其在一通道阱区内具有一通道、一源极及一栅极。通道阱区可以通过在上层中的图案化导体连接栅极，或直接连接电压供给电路。一实施例中，在受保护节点上的正电压及负电压皆为放电，天线效应放电电路包括一n通道场效应晶体管(例如NMOS)和p通道场效应晶体管(例如PMOS)，其配置于以下详细描述。The antenna effect discharge circuit may include a field effect transistor having a channel, a source and a gate in a channel well region. The channel well region can be connected to the gate through a patterned conductor in the upper layer, or directly connected to the voltage supply circuit. In one embodiment, both the positive voltage and the negative voltage on the protected node are discharged, and the antenna effect discharge circuit includes an n-channel field effect transistor (such as NMOS) and a p-channel field effect transistor (such as PMOS), which are configured in the following Detailed Description.
利用栅极中的一电容，可防止栅极上的电压在暴露于天线效应充电的期间追踪通道阱区内的电压。天线效应放电电路保持其栅极和通道阱未连接的状态，直到形成多个图案化导体层中的上层形成。With a capacitance in the gate, the voltage on the gate is prevented from tracking the voltage in the well region of the channel during exposure to antenna effect charging. The antenna effect discharge circuit keeps its gate and channel well unconnected until the upper layer of the plurality of patterned conductor layers is formed.
本发明实施例还提供了一天线效应放电电路包含一开关，用以在来装置运作期间关闭，并具有第一端和第二端。该第一端通过一第一连接器连接天线效应放电电路的栅极，第二端通过一第二连接器连接电压供应电路。第一连接器及第二连接器其中的一个或两个包括最上层的图案化导体，其用以连接栅极与电压供应电路。在具有开关的实施例中，天线效应放电电路在整个工艺皆维持有效，直到电压供给电路于装置运作时启用。The embodiment of the present invention also provides an antenna effect discharge circuit comprising a switch, which is used to close during the operation of the device, and has a first terminal and a second terminal. The first end is connected to the grid of the antenna effect discharge circuit through a first connector, and the second end is connected to the voltage supply circuit through a second connector. One or both of the first connector and the second connector include an uppermost patterned conductor for connecting the gate and the voltage supply circuit. In embodiments with switches, the antenna effect discharge circuit remains active throughout the process until the voltage supply circuit is enabled during device operation.
本发明实施例害提供了一种制造集成电路装置的方法，包括于一基板上形成一集成电路系统，电路系统具一节点，节点被保护以避免天线效应放电。此方法包括于基板上形成一天线效应放电电路，具有一端及一栅极，该端连接至节点。此外，方法包括形成一电容耦接栅极与基板。于该基板上提供一电压供应电路，以在运作时偏置栅极，以关闭天线效应放电电路。本文中所描述的方法包含以装置之上或最上图案化导体层连接栅极至电压供应电路。在一些实施例中，方法包含在装置上栅极及电压供应电路间提供一开关，配置成在运作时关闭开关，使栅极通过开关连接电压供应电路。Embodiments of the present invention provide a method of manufacturing an integrated circuit device, including forming an integrated circuit system on a substrate, the circuit system having a node, and the node is protected from antenna effect discharge. The method includes forming an antenna effect discharge circuit on the substrate, having an end and a grid, and the end is connected to the node. Additionally, the method includes forming a capacitively coupled gate and the substrate. A voltage supply circuit is provided on the substrate to bias the grid to turn off the antenna effect discharge circuit during operation. The methods described herein include connecting the gate to a voltage supply circuit with a patterned conductor layer on or above the device. In some embodiments, the method includes providing a switch on the device between the gate and the voltage supply circuit, configured to, in operation, close the switch such that the gate is connected to the voltage supply circuit through the switch.
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附图式，作详细说明如下：In order to have a better understanding of the above and other aspects of the present invention, the following specific examples, together with the accompanying drawings, are described in detail as follows:
附图说明Description of drawings
图1是基于动态阈值电压MOSFE的现有技术天线效应放电电路示意图。FIG. 1 is a schematic diagram of an antenna effect discharge circuit in the prior art based on a dynamic threshold voltage MOSFET.
图2为现有技术集成电路一例的立体图，包括多个图案化导体层，其可如以下所述被天线效应放电电路保护。Fig. 2 is a perspective view of an example of a prior art integrated circuit, including a plurality of patterned conductor layers, which can be protected by an antenna effect discharge circuit as described below.
图3为天线效应放电电路的示意图，包含耦接到场效应晶体管的栅极的电容。3 is a schematic diagram of an antenna effect discharge circuit including a capacitor coupled to a gate of a field effect transistor.
图4绘示天线效应放电电路的装置基板的配置，包括如下所述的高电压、n通道及p通道场效应晶体管。Figure 4 shows the configuration of the device substrate of the antenna effect discharge circuit, including high voltage, n-channel and p-channel field effect transistors as described below.
图5是形成最上层图案化导体层之前，天线效应放电电路的示意图，其绘示负电压的放电集中在受保护的节点。5 is a schematic diagram of the antenna effect discharge circuit before forming the uppermost patterned conductor layer, which shows that the discharge of negative voltage is concentrated on the protected node.
图6是形成最上层图案化导体层之前，天线效应放电电路的示意图，其绘示正电压的放电集中在受保护的节点。6 is a schematic diagram of the antenna effect discharge circuit before forming the uppermost patterned conductor layer, which shows that the discharge of positive voltage is concentrated on the protected node.
图7是另一种天线效应放电电路的实施例，包含耦接场效应晶体管的栅极的电容，以与栅极与电压供应电路之间的开关。FIG. 7 is another embodiment of an antenna effect discharge circuit, including a capacitor coupled to a gate of a field effect transistor, and a switch between the gate and a voltage supply circuit.
图8是一实施例中天线效应放电电路的布局，用以保护集成电路上的多个节点。FIG. 8 is a layout of an antenna effect discharge circuit for protecting multiple nodes on an integrated circuit in an embodiment.
图9是集成电路存储器阵列的简化方块图，包含如本文所述的天线效应放电电路。Fig. 9 is a simplified block diagram of an integrated circuit memory array including an antenna effect discharge circuit as described herein.
图10集成电路制造方法的简化流程图，其利用如本文所述的天线效应放电电路。Figure 10 is a simplified flowchart of a method of manufacturing an integrated circuit utilizing an antenna effect discharge circuit as described herein.
图11绘示在CCFG NMOS保护电路的装置中，漏极电流与漏极电压(IdVd)的曲线，以及漏极电压与基底电流Ib(IbVd)的曲线。FIG. 11 shows the curves of the drain current and the drain voltage (IdVd) and the drain voltage and the substrate current Ib (IbVd) in the device of the CCFG NMOS protection circuit.
图12所示的实验数据包括在CCFG PMOS保护电路的装置中，漏极电流与漏极电压(IdVd)的曲线，以及漏极电压与基底电流Ib(IbVd)的曲线。The experimental data shown in FIG. 12 includes the curve of drain current and drain voltage (IdVd) and the curve of drain voltage and substrate current Ib (IbVd) in the device of CCFG PMOS protection circuit.
图13所示的实验数据包括完整CCFG CMOS保护电路的放电电流(当栅极和阱浮置)，类似图5和图6。The experimental data shown in Figure 13 includes the discharge current (when the gate and well are floating) of the complete CCFG CMOS protection circuit, similar to Figures 5 and 6.
图14为测量8层3DVG装置的TEM剖面图的影像。FIG. 14 is an image of a TEM cross-sectional view of an 8-layer 3DVG device measured.
图15绘示受测装置的多层中，存储器单元的初始阈值电压分布。FIG. 15 shows initial threshold voltage distributions of memory cells in multiple layers of a device under test.
图16绘示受测电路的SSL Vt分布。Figure 16 shows the SSL Vt distribution of the tested circuit.
图17是一简化NAND串的示意图。Figure 17 is a schematic diagram of a simplified NAND string.
图18绘示随着σ的增加，3个SSL阈值电压的分布图(Vt范围)。Fig. 18 shows the distribution of 3 SSL threshold voltages (Vt range) as σ increases.
图19绘示用于编程棋盘窗口测试时，受测装置的低和高阈值状态。Figure 19 depicts the low and high threshold states of a device under test for a programmed checkerboard window test.
图20为应用于CMOS译码器设计的天线保护电路的电路图范例。FIG. 20 is an example circuit diagram of an antenna protection circuit applied to a CMOS decoder design.
【符号说明】【Symbol Description】
102-105、112-115、171-178：有源层带102-105, 112-115, 171-178: active layer belt
102B-105B、112A-115A：接触垫102B-105B, 112A-115A: Contact pads
109、119：SSL栅极结构109, 119: SSL gate structure
121-1-121-N：字线121-1-121-N: word line
126、127：接地选择线GSL126, 127: Ground selection line GSL
161-168：存储单元161-168: storage unit
172-175：层间连接器172-175: interlayer connector
180：顶端绝缘层带180: top insulation tape
181-187：绝缘层带181-187: Insulation tape
188：底端有源层带188: bottom active layer belt
190：导线190: Wire
201：第一存储单元201: The first storage unit
203：第三存储单元203: The third storage unit
210-240、610-640：次叠层210-240, 610-640: Secondary stack
211、221、231、241：第一有源层带211, 221, 231, 241: the first active layer zone
212、222、232、242：第一绝缘层带212, 222, 232, 242: first insulating layer belt
231、223、233、243：第二有源层带231, 223, 233, 243: the second active layer zone
214、224、234、244：第二绝缘层带214, 224, 234, 244: second insulating layer tape
250、650：顶端绝缘层250, 650: top insulation layer
271-272：多层阵列271-272: Multilayer Arrays
290：导电材料层290: layer of conductive material
295：直线295: Straight line
305、505：着陆区域305, 505: Landing area
390、590、690、790、890、990：刻蚀掩模390, 590, 690, 790, 890, 990: etch mask
391、392、591、592、691-698、795-798、893-894、897-898、992、994、996、998：掩模开口391, 392, 591, 592, 691-698, 795-798, 893-894, 897-898, 992, 994, 996, 998: mask opening
611、621、631、641：第一有源层611, 621, 631, 641: first active layer
612、622、632、642：第一绝缘层612, 622, 632, 642: first insulating layer
613、623、633、643：第二有源层613, 623, 633, 643: second active layer
614、624、634、644：第二绝缘层614, 624, 634, 644: second insulating layer
750、760、770、780、830、840、870、880、920：通孔750, 760, 770, 780, 830, 840, 870, 880, 920: through hole
765：特定深度765: specific depth
1010-1050、1110-1140：步骤1010-1050, 1110-1140: Steps
1200：集成电路1200: integrated circuit
1205：数据输入线路1205: Data input line
1210：控制器1210: Controller
1220、1280：区块1220, 1280: block
1230、1255、1275：总线1230, 1255, 1275: bus
1240：列译码器1240: column decoder
1245：字线1245: word line
1250：记忆库译码器1250: memory bank decoder
1260：存储器阵列1260: memory array
1265：位线1265: bit line
1270：行译码器1270: row decoder
1285：数据输出线路1285: Data output line
1290：输出线路1290: output line
O1-O4：绝缘层O1-O4: insulating layer
P1-P4：有源层P1-P4: active layer
ML1、ML2、ML3：金属层ML1, ML2, ML3: metal layers
具体实施方式Detailed ways
本发明实施例的详细描述请参照图1至图20。For detailed description of the embodiment of the present invention, please refer to FIG. 1 to FIG. 20 .
图1绘示现有技术中用于天线效应的保护电路，其基于动态阈值MOS晶体管对10、11。PMOS晶体管的漏极耦接基板接地12。相同地，NMOS晶体管11的漏极耦接到基板接地12。PMOS晶体管的通道区内的通道阱13通过下图案化导体(例如第一金属层)连接PMOS晶体管的栅极。相同地，NMOS晶体管11的通道区内的通道阱14通过下图案化导体(例如第一金属层)连接到NMOS晶体管11的栅极。PMOS晶体管10和NMOS晶体管11的源极连接节点15，其被保护以避免受天线效应引起的电荷集中。FIG. 1 shows a protection circuit for antenna effect in the prior art, which is based on a dynamic threshold MOS transistor pair 10 , 11 . The drain of the PMOS transistor is coupled to the substrate ground 12 . Likewise, the drain of NMOS transistor 11 is coupled to substrate ground 12 . The channel well 13 in the channel region of the PMOS transistor is connected to the gate of the PMOS transistor through a lower patterned conductor (such as the first metal layer). Similarly, the channel well 14 in the channel region of the NMOS transistor 11 is connected to the gate of the NMOS transistor 11 through the lower patterned conductor (eg, the first metal layer). The sources of the PMOS transistor 10 and the NMOS transistor 11 are connected to the node 15, which are protected from charge concentration caused by the antenna effect.
「源极」和「漏极」名词依惯例依照晶体管内主电流流动方向，指定场效应晶体管的终端。在某些情况下，此些传统的描述较为模糊，例如当装置支持双向电流时，以及当描述装置具有对称结构的终端时。「源极」和「漏极」名词仅用于给场效应晶体管的两终端区别，并不意味一主电流流动方向或终端结构。因此，本文中的「源极」和「漏极」两名词可互相调换。The terms "source" and "drain" conventionally designate the terminals of field effect transistors according to the direction of the main current flow within the transistor. In some cases, such conventional descriptions are ambiguous, such as when the device supports bidirectional current flow, and when the device is described as having symmetrically structured terminals. The terms "source" and "drain" are only used to distinguish the two terminals of a field effect transistor, and do not imply a main current flow direction or terminal structure. Therefore, the terms "source" and "drain" in this article can be interchanged.
MOS对10、11的栅极氧化物足够厚，以使闪存装置或其他高电压集成电路维持高电压运作。可使用如生产厚氧化物电荷泵晶体管的相同步骤，轻易制造闪存装置的厚栅极氧化层。The gate oxide of the MOS pair 10, 11 is thick enough to enable high voltage operation of flash memory devices or other high voltage integrated circuits. Thick gate oxides for flash memory devices can be easily fabricated using the same steps as for producing thick oxide charge pump transistors.
在工艺中，正电荷通过PMOS晶体管10传导到接地12，且负电荷在极低的电压经由NMOS晶体管11传导到接地。举例来说，NMOS晶体管11将在接近结正向开启电压(例如0.6V)时导通。同样地，PMOS晶体管将在电压接近结正向开启电压(例如-0.6V)时导通。对于动态阈值MOS装置之运作的讨论，可参照IEEE ELECTRON DEVICES，Vol.38，No.11，1991年11月。也可参照美国专利7,196,369，发明名称″PLASMA DAMAGE PROTECTION CIRCUIT FOR ASEMICONDUCTOR DEVICE″，发证日2007年3月27日。In the process, positive charges are conducted through the PMOS transistor 10 to ground 12 and negative charges are conducted at very low voltages through the NMOS transistor 11 to ground. For example, NMOS transistor 11 will turn on close to the junction forward turn-on voltage (eg, 0.6V). Likewise, a PMOS transistor will turn on at a voltage close to the junction forward turn-on voltage (eg -0.6V). For a discussion of the operation of dynamic threshold MOS devices, see IEEE ELECTRON DEVICES, Vol. 38, No. 11, November 1991. Also refer to US Patent No. 7,196,369, the title of the invention "PLASMA DAMAGE PROTECTION CIRCUIT FOR ASEMICONDUCTOR DEVICE", issued on March 27, 2007.
集成电路运作期间，PMOS装置10的栅极藉线路16连接高正电压VPP，VPP足够高以在最高操作电位施加于受保护节点时，可关闭装置10。同样地，NMOS装置11的栅极藉线路17连接高负电压VNP，其具有足够的大小，当最负的操作电位施加于受保护节点时，可关闭装置11。During integrated circuit operation, the gate of PMOS device 10 is connected to a high positive voltage VPP via line 16, which is high enough to turn off device 10 when the highest operating potential is applied to the protected node. Likewise, the gate of NMOS device 11 is connected via line 17 to a high negative voltage VNP, which is of sufficient magnitude to turn off device 11 when the most negative operating potential is applied to the protected node.
工艺期间，如果受保护节点上的电压突然升高，在晶体管的栅极和基板端的充电将非常迅速，如图1所示的动态阈值结构。如此可能出现非常低的栅极到基板电位，使开启装置非常困难。因此，图1的保护电路在某些条件下可能无法完全开启。因此，其所提供的保护对于受保护节点的快速放电累积电荷可能不是非常有效，例如工艺中暴露在大量电荷效应的字线。During the process, if the voltage on the protected node suddenly rises, the charging at the gate and substrate terminals of the transistor will be very rapid, as shown in Figure 1 with the dynamic threshold structure. This can result in very low gate-to-substrate potentials, making turning on the device very difficult. Therefore, the protection circuit of Figure 1 may not fully turn on under certain conditions. Therefore, the protection it provides may not be very effective against rapidly discharging accumulated charge of protected nodes, such as word lines exposed to the effects of large charges in the process.
图2绘示三维NAND闪存阵列结构的立体图，此处作为范例的装置具有多个图案化导体层，包含图案化多晶硅层及图案化金属层，且可使用本文所述天线效应放电电路。参照美国专利8,503,213。当然，其它使用多个图案化导体层的装置也可使用本文所述的天线效应放电电路进行保护。图2中，绝缘材料由图中移除，以暴露更多的结构。举例来说，绝缘材料系从半导体层带之间、脊状叠层之内移除，并从半导体层带的脊状叠层之间移除。FIG. 2 is a perspective view of a three-dimensional NAND flash memory array structure. Here, the device as an example has a plurality of patterned conductor layers, including a patterned polysilicon layer and a patterned metal layer, and can use the antenna effect discharge circuit described herein. See US Patent 8,503,213. Of course, other devices using multiple patterned conductor layers can also be protected using the antenna effect discharge circuit described herein. In Figure 2, the insulating material has been removed from the figure to expose more of the structure. For example, insulating material is removed from between the semiconductor layer strips, within the ridge stack, and from between the semiconductor layer strips' ridge stack.
多层阵列于一绝缘层上形成，且包含多个图案化多晶硅层，其提供多个字线425-1、…、425-n-1、425-n，字线与脊状叠层共形。此些脊状叠层包含多个半导体层带412、413、414、415。同一平面上的半导体层带通过阶梯结构相互电性耦接。The multilayer array is formed on an insulating layer and includes multiple patterned polysilicon layers that provide multiple wordlines 425-1, . . . , 425-n-1, 425-n conformal to the ridge stack . The ridge stacks comprise a plurality of strips 412 , 413 , 414 , 415 of semiconductor layers. The semiconductor layer strips on the same plane are electrically coupled to each other through the ladder structure.
阶梯结构412A、413A、414A、415A终止半导体层带，例如半导体层带412、413、414、415。如图所示，这些阶梯结构412A、413A、414A、415A电性连接到不同的位线，以连接选择阵列中特定平面的译码线路。这些阶梯结构412A、413A、414A、415A，可以在多个脊状叠层被定义时同时图案化。The stepped structures 412A, 413A, 414A, 415A terminate semiconductor layer strips, eg semiconductor layer strips 412 , 413 , 414 , 415 . As shown in the figure, these ladder structures 412A, 413A, 414A, 415A are electrically connected to different bit lines, so as to connect to the decoding lines that select a specific plane in the array. These stepped structures 412A, 413A, 414A, 415A can be patterned simultaneously when multiple ridge stacks are defined.
阶梯结构402B、403B、404B、405B终止半导体层带，如半导体层带402、403、404、405。如图所示，这些阶梯结构402B、403B、404B、405B电性连接到不同的位线，用以连接位于阵列内之特定平面的译码线路。这些阶梯结构402B、403B、404B、405B，可以在多个脊状叠层被定义时同时图案化。The stepped structures 402B, 403B, 404B, 405B terminate the semiconductor layer strips, such as the semiconductor layer strips 402 , 403 , 404 , 405 . As shown in the figure, these ladder structures 402B, 403B, 404B, 405B are electrically connected to different bit lines, and are used to connect the decoding lines in a specific plane within the array. These stepped structures 402B, 403B, 404B, 405B can be patterned simultaneously when multiple ridge stacks are defined.
此配置中，任何给定的半导体层带的叠层与阶梯结构412A、413A、414A、415A，或是阶梯结构402B、403B、404B、405B中任一者连接，但并非同时连接两者。半导体层带的叠层具有两种相反方向其中之一，一为位线端至源极线端方向，一为源极线端至位线端方向。举例来说，半导体层带叠层412、413、414、415具有位线端至源极线端方线；半导体层带叠层402、403、404、405具有源极线端至位线端方向。In this configuration, any given stack of semiconductor layer ribbons is connected to either, but not both, of the stepped structures 412A, 413A, 414A, 415A, or the stepped structures 402B, 403B, 404B, 405B. The stacking of semiconductor layer strips has one of two opposite directions, one is the direction from the bit line end to the source line end, and the other is the direction from the source line end to the bit line end. For example, semiconductor ribbon stacks 412, 413, 414, 415 have a bit line end to source line end square line; semiconductor layer stacks 402, 403, 404, 405 have a source line end to bit line end direction .
半导体层带叠层412、413、414、415其中一端终止于阶梯结构412A、413A、414A、415A，另一端穿过SSL栅极结构419，接地选择线GSL426，字线425-1WL至425-N WL，接地选择线GSL426，并终止于对应的源极线。半导体层带叠层412、413、414、415与阶梯结构402B、403B、404B、405B并无连接。One end of the semiconductor layer stack 412, 413, 414, 415 is terminated by the ladder structure 412A, 413A, 414A, 415A, and the other end passes through the SSL gate structure 419, the ground selection line GSL426, and the word lines 425-1WL to 425-N WL, the ground select line GSL426, terminates at the corresponding source line. The semiconductor ribbon stacks 412 , 413 , 414 , 415 are not connected to the stepped structures 402B, 403B, 404B, 405B.
半导体层带的叠层402、403、404、405其中一端终止于阶梯结构402B、403B、404B、405B，另一端穿过SSL栅极结构409，接地选择线GSL427，字线425-N WL至425-1WL，接地选择线GSL426，并终止于源极线(被本图的其他部分所掩盖)。半导体层带的叠层402、403、404、405不会到达阶梯结构412A、413A、414A、415A。One end of the semiconductor layer stacks 402, 403, 404, 405 is terminated at the ladder structure 402B, 403B, 404B, 405B, and the other end passes through the SSL gate structure 409, the ground selection line GSL427, and the word lines 425-N WL to 425 -1WL, ground select line GSL426, and terminate at source line (masked by the rest of this diagram). The stacks 402 , 403 , 404 , 405 of semiconductor layer strips do not reach the stepped structures 412A, 413A, 414A, 415A.
如现有图式所描述，一存储材料层自半导体层带412-415及402-405分隔字线425-1到425-N。接地选择线GSL426及接地选择线GSL427与脊状叠层共形，和字线相似。As depicted in the prior drawings, a memory material layer separates word lines 425-1 to 425-N from semiconductor layer strips 412-415 and 402-405. Ground select line GSL426 and ground select line GSL427 are conformal to the ridge stack, similar to word lines.
位线及串选择线形成于金属层ML1、ML2和ML3。Bit lines and string selection lines are formed on metal layers ML1, ML2 and ML3.
晶体管形成在阶梯结构412A、413A、414A与字线425-1之间。在晶体管中，半导体层带(例如413)作为装置的通道区。SSL栅极结构(例如419、409)在字线425-1至425-n被定义的相同步骤图案化。硅化物层可沿字线的顶表面、接地选择线与栅极结构409、419上形成。存储材料层可作为晶体管的栅极介电质。这些晶体管作为串选择栅极，耦接译码电路，用以选择阵列中特定脊状叠层。Transistors are formed between the ladder structures 412A, 413A, 414A and the word line 425-1. In a transistor, a strip of semiconductor layers (eg, 413) acts as the channel region of the device. The SSL gate structures (eg, 419, 409) are patterned in the same steps as wordlines 425-1 to 425-n are defined. A silicide layer may be formed along the top surfaces of the word lines, ground select lines and gate structures 409 , 419 . The layer of memory material may serve as a gate dielectric for the transistor. These transistors serve as string select gates, coupled to the decoding circuit, to select specific ridge stacks in the array.
第一金属层ML1包括串选择线，具有与平行于半导体材料层带的纵向方向。这些ML1串选择线由层间连接器连接到不同的SSL栅极结构(例如409、419)。The first metal layer ML1 includes string selection lines having a longitudinal direction parallel to the semiconductor material layer strips. These ML1 string select lines are connected to the different SSL gate structures (eg 409, 419) by interlayer connectors.
第二金属层ML2包括串选择线，具有平行于字线的宽度方向。这些ML2串选择线由层间连接器连接到不同的ML1串选择线。The second metal layer ML2 includes string selection lines having a width direction parallel to the word lines. These ML2 string selection lines are connected to different ML1 string selection lines by interlayer connectors.
结合来说，这些ML1串选择线和ML2串选择线允许一个串选择讯号选择半导体层带的特定叠层。In combination, these ML1 string select lines and ML2 string select lines allow one string select signal to select a particular stack of semiconductor layer strips.
第一金属层ML1还包括2源极线，其具有平行于字线的宽度方向。The first metal layer ML1 also includes 2 source lines having a width direction parallel to the word lines.
第三金属层ML3包括位线，具有平行于半导体材料层带的纵向方向。不同的位线通过层间连接器电性连接到不同的阶梯结构的不同步阶412A、413A、414A、415A和402B、403B、404B、405B。这些ML3位线允许位线信号选择半导体层带的特定水平面。The third metal layer ML3 comprises bit lines having a longitudinal direction parallel to the semiconductor material layer strips. Different bit lines are electrically connected to different steps 412A, 413A, 414A, 415A and 402B, 403B, 404B, 405B of different ladder structures through interlayer connectors. These ML3 bit lines allow the bit line signal to select a specific level of the semiconductor layer strip.
第四金属层(ML4，未绘示)可以用于连接外围电路至存储器阵列，例如驱动器、感应放大器、译码器，电压供应发电器等。The fourth metal layer (ML4, not shown) can be used to connect peripheral circuits to the memory array, such as drivers, sense amplifiers, decoders, voltage supply generators, and the like.
层间连接器(有绘出但是未标示)位于图案化层之间的通孔中，提供多个图案化导电层级其他装置内元件中，节点和导体之间的连接。Interlayer connectors (shown but not labeled) are located in the vias between the patterned layers and provide connections between nodes and conductors in other devices within the multiple patterned conductive levels.
图3为天线效应放电电路的示意图，包含一场效应晶体管，其栅极经一电容耦接到半导体基板。天线效应放电电路具有一终端(例如场效应晶体管50的漏极)、一栅极及另一终端(例如场效应晶体管50的源极)，一终端连接到装置上受保护的节点55，以避免节点遭受电荷累积，栅极例如是电路中场效应晶体管50的栅极，累积电荷可透过另一终端放电至基板上。3 is a schematic diagram of an antenna effect discharge circuit, which includes a field effect transistor whose gate is coupled to a semiconductor substrate through a capacitor. The antenna effect discharge circuit has a terminal (such as the drain of field effect transistor 50), a gate and another terminal (such as the source of field effect transistor 50), one terminal is connected to the protected node 55 on the device to avoid The node is subject to charge accumulation, the gate is for example the gate of field effect transistor 50 of the circuit, and the accumulated charge can be discharged to the substrate through the other terminal.
在电路中，p通道场效应晶体管50和n通道场效应晶体管51具有漏极，其耦接至节点55以避免受天线效应充电。场效应晶体管50、51的源极连接到基板52。场效应晶体管50的栅极通过一图案化导体57(例如多晶硅导线)连接到电容65，电容65具有连接到导体57的第一端，以及位于基板52内，或连接于基板52的第二端。场效应晶体管51的栅极通过图案化导体60(例如多晶硅导线)连接到电容66，电容66具有连接到导体60的第一端，以及位于基板52内，或连接于基板52的第二端。In the circuit, p-channel FET 50 and n-channel FET 51 have drains coupled to node 55 to avoid antenna effect charging. The sources of the field effect transistors 50 , 51 are connected to the substrate 52 . The gate of the field effect transistor 50 is connected to a capacitor 65 through a patterned conductor 57 (such as a polysilicon wire). The capacitor 65 has a first end connected to the conductor 57 and a second end located in the substrate 52 or connected to the substrate 52. . The gate of the field effect transistor 51 is connected to a capacitor 66 through a patterned conductor 60 (such as a polysilicon wire). The capacitor 66 has a first terminal connected to the conductor 60 and a second terminal located in the substrate 52 or connected to the substrate 52 .
p通道场效应晶体管50在基板上的n型半导体区内具有一通道，此处称为通道阱53。通道阱53连接导体56。在上图案化导体层(较佳为最上层图案化导体层)形成前，导体56、57在装置工艺中并未连接。上图案化导体层包括导体58，其通过导体57、56，提供通道阱53及场效应晶体管50的栅极间的连接。此外，导体58连接电压供应电路，其提供偏置电压VPP。The p-channel field effect transistor 50 has a channel in the n-type semiconductor region on the substrate, which is called a channel well 53 here. The channel well 53 is connected to a conductor 56 . Before the upper patterned conductor layer (preferably the uppermost patterned conductor layer) is formed, the conductors 56 and 57 are not connected in the device process. The upper patterned conductor layer includes a conductor 58 that provides a connection between the channel well 53 and the gate of the field effect transistor 50 through conductors 57 , 56 . In addition, conductor 58 is connected to a voltage supply circuit, which provides a bias voltage VPP.
n通道场效应晶体管51在基板上的p型半导体区内具有一通道，此处称为通道阱54。通道阱54连接导体61。在上图案化导体层(较佳为最上层图案化导体层)形成前，导体61、60在装置工艺中并未连接。上图案化导体层包括导体62，其通过导体60、61，提供通道阱54及场效应晶体管51的栅极间的连接。此外，导体62连接电压供应电路，其提供偏置电压VNP。The n-channel field effect transistor 51 has a channel in the p-type semiconductor region on the substrate, which is called a channel well 54 here. The channel well 54 is connected to the conductor 61 . Before the upper patterned conductor layer (preferably the uppermost patterned conductor layer) is formed, the conductors 61 and 60 are not connected in the device process. The upper patterned conductor layer includes a conductor 62 that provides a connection between the channel well 54 and the gate of the field effect transistor 51 through conductors 60 , 61 . Furthermore, conductor 62 is connected to a voltage supply circuit, which provides a bias voltage VNP.
图4绘示可用于图3电路中的高电压、P通道和高压n通道场效应晶体管(HV-PMOS和HV-NMOS)的基板与阱结构。本例中，装置形成在p型基板100之上。p通道场效应晶体管形成在n型半导体阱103内，其对应于图3中的通道阱53。n通道场效应晶体管形成在p型半导体阱102内，其藉深n型阱101自基板100中分离。p型半导体阱102对应于图3的通道阱54。FIG. 4 illustrates the substrate and well structures of high voltage, p-channel and high voltage n-channel field effect transistors (HV-PMOS and HV-NMOS) that can be used in the circuit of FIG. 3 . In this example, the device is formed on a p-type substrate 100 . The p-channel field effect transistor is formed in the n-type semiconductor well 103, which corresponds to the channel well 53 in FIG. The n-channel field effect transistor is formed in the p-type semiconductor well 102 separated from the substrate 100 by the deep n-type well 101 . The p-type semiconductor well 102 corresponds to the channel well 54 of FIG. 3 .
图4绘示p型场效应晶体管(HV-PMOS)的源极区、漏极区106、107，栅极105和栅极绝缘体108。此外，n型接触区104形成在n型阱103内，以提供连接到通道阱的本体。此外，图中绘示n型场效应晶体管(HV-NMOS)的源极和漏极区113、114，栅极112，以与栅极绝缘体115。此外，p型接触区111形成在p型阱102内，以提供连接到通道阱的本体。另外，n型接触区110形成在深n型阱101内，以提供深n阱至偏压电路系统的连接，帮助通道阱102的隔离。为提供电容和基板的连接(未绘示)，P型接触区117、118可设置在阱101、103之外的基板。浅沟道隔离STI结构(例如119)可如图所示设置在掺杂区之间，以增进隔离。FIG. 4 illustrates source regions, drain regions 106 , 107 , gate 105 and gate insulator 108 of a p-type field effect transistor (HV-PMOS). Furthermore, an n-type contact region 104 is formed in the n-type well 103 to provide a body connection to the channel well. In addition, the figure shows source and drain regions 113 , 114 , gate 112 , and gate insulator 115 of an n-type field effect transistor (HV-NMOS). Furthermore, a p-type contact region 111 is formed within the p-type well 102 to provide a body connection to the channel well. In addition, an n-type contact region 110 is formed in the deep n-type well 101 to provide a connection of the deep n-well to the biasing circuitry to aid in the isolation of the channel well 102 . P-type contact regions 117 , 118 may be provided on the substrate outside the wells 101 , 103 to provide a connection between the capacitor and the substrate (not shown). Shallow trench isolation STI structures (eg, 119 ) can be placed between doped regions as shown to improve isolation.
如图1所提及，在现有技术的DTMOS型天线效应放电电路中，栅极和通道阱接触(例如105、104)在工艺中连接。这种连接将使在充电期间正电压施加到漏极107时，栅极和通道阱之间的电压维持接近零。在图3所描述的电路中，栅极和通道阱接触(例如105、104)在所有或或大部分的图案化导体层形成时并未连接。更确切地说，栅极(如105)连接到一电容，而通道阱(例如104、103)为浮接。因此，即使在通道阱藉受保护节点上的电压增加而增强，因为电容和晶体管的栅极至阱电容率造成电压差，栅极电位仅受栅极耦合率的因素变化。这使得场效应晶体管在天线效应充电时更快开启，更有效地放电不需要的电压。As mentioned in Fig. 1, in prior art DTMOS type antenna effect discharge circuits, the gate and channel well contacts (eg 105, 104) are connected in-process. This connection will maintain the voltage between the gate and channel well near zero when a positive voltage is applied to the drain 107 during charging. In the circuit depicted in FIG. 3, the gate and channel well contacts (eg, 105, 104) are not connected when all or most of the patterned conductor layer is formed. More specifically, the gate (eg 105) is connected to a capacitor, while the channel wells (eg 104, 103) are floating. Thus, even though the channel well is enhanced by an increase in voltage on the protected node, the gate potential changes only by a factor of the gate coupling ratio because of the voltage difference caused by the capacitance and gate-to-well permittivity of the transistor. This allows the field effect transistor to turn on faster during antenna effect charging, discharging unwanted voltage more efficiently.
电容65、66可以使用一电容连接实现，P型基板内的高压NMOS晶体管，与源极和漏极连接在一起，其具有由图案化导体形成的栅极，例如是与形成场效应晶体管(HV-PMOS或HV-NMOS)的栅极对应的相同图案化导体。或者，电容可藉一单一连续阱实现，其透过一介电层自导体分离，例如是用于形成图3的HV-NMOS和HV-PMOS装置的栅极介电质，其导体之下没有通道面积。为确立高耦合比(coupling ratio)，电容上的导体面积约可大于对应的场效应晶体管50、51上的栅极面积。在一实施例中，电容上的栅极的面积约可比栅极的面积大约4倍，使栅极耦合比约0.8。Capacitors 65, 66 can be realized using a capacitive connection, a high-voltage NMOS transistor in a P-type substrate, connected together with source and drain, which has a gate formed by a patterned conductor, such as a field-effect transistor (HV -PMOS or HV-NMOS) gate corresponding to the same patterned conductor. Alternatively, the capacitance can be realized by a single continuous well separated from the conductor by a dielectric layer, such as the gate dielectric used to form the HV-NMOS and HV-PMOS devices of FIG. channel area. To establish a high coupling ratio, the conductor area on the capacitor can be approximately larger than the gate area on the corresponding field effect transistor 50 , 51 . In one embodiment, the area of the gate on the capacitor is approximately four times the area of the gate, resulting in a gate coupling ratio of approximately 0.8.
图5和图6绘示图3的天线效应放电电路的下图案化导体的形成，其发生在形成栅极与通道阱的连接前。与图3对应的元件使用相同标号，并且不再赘述。FIGS. 5 and 6 illustrate the formation of the lower patterned conductor of the antenna effect discharge circuit of FIG. 3, which occurs before forming the connection between the gate and the channel well. Components corresponding to those in FIG. 3 use the same reference numerals and will not be described again.
在图5所示的状态中，受保护节点(例如字线)可在工艺步骤中被充电至约-2V。在此情况下，p-通道场效应晶体管50中，p+源极至n型通道阱结为反向偏压。因此p通道场效应晶体管50保持关闭状态。但是，n通道场效应晶体管51的n+漏极到p型通道阱结为正向偏压。电容66防止n-通道场效应晶体管51的栅极充电到与p型通道阱54相同的电压。因此，当受保护节点达到约负2V，n通道场效应晶体管的浮接p型通道阱藉正向结被快速充电到与受保护节点大约相同的电压。如果电容66有足够的电容率，可提供一个相对较大的栅极耦合比，栅极电压将藉电容分压(VWL*(1-GCR))漂移至大于负1V的值(例如＞-1V)，接近p型基板52的零电压。如此维持栅极到通道阱的正偏压Vgb，其大小在本图中约低于1V，足以在工艺步骤中开启n通道场效应晶体管中，对受保护节点不需要充电的快速放电。In the state shown in FIG. 5, the protected node (eg, word line) may be charged to about -2V during a process step. In this case, in the p-channel field effect transistor 50, the p+ source to n-channel well junction is reverse biased. Therefore, the p-channel field effect transistor 50 remains off. However, the n+ drain to p-type channel well junction of the n-channel field effect transistor 51 is forward biased. Capacitor 66 prevents the gate of n-channel field effect transistor 51 from charging to the same voltage as p-channel well 54 . Therefore, when the protected node reaches approximately negative 2V, the floating p-channel well of the n-channel FET is rapidly charged to approximately the same voltage as the protected node through the forward junction. If the capacitor 66 has sufficient permittivity, a relatively large gate coupling ratio can be provided, and the gate voltage will drift to a value greater than minus 1V (for example, >-1V) by the capacitor voltage divider (VWL*(1-GCR) ), close to the zero voltage of the p-type substrate 52. In this way, the positive bias voltage Vgb from the gate to the channel well is maintained, and its magnitude is approximately lower than 1V in this figure, which is sufficient to turn on the fast discharge of the n-channel field effect transistor in the process step without charging the protected node.
在图6所示的状态中，受保护节点(例如字线)可在工艺步骤中被充电至约+2V。在此情况下，m通道场效应晶体管51中，n+源极至p型通道阱结为反向偏压。因此n通道场效应晶体管50保持关闭。但是，p通道场效应晶体管50的p+漏极到n型通道阱结为正向偏压。电容65防止p通道场效应晶体管50的栅极充电到与n型通道阱53相同的电压。因此，当受保护节点达到约正2V，p通道场效应晶体管的浮接n型通道阱藉正向结被快速充电到与受保护节点大约相同的电压。如果电容65有足够的电容率，可提供一个相对较大的栅极耦合比，栅极电压将藉电容分压(VWL*(1-GCR))漂移至小于1V的值(例如＜1V)，接近p型基板52的零电压。如此维持栅极到通道阱的负偏压Vgb，其大小在本图中约低于1V，足以在工艺步骤中开启p通道场效应晶体管中，对受保护节点不需要充电的快速放电。In the state shown in FIG. 6, the protected node (eg, word line) may be charged to about +2V during a process step. In this case, in the m-channel field effect transistor 51, the junction from the n+ source to the p-type channel well is reverse biased. The n-channel field effect transistor 50 therefore remains off. However, the p+ drain to n-channel well junction of p-channel FET 50 is forward biased. Capacitor 65 prevents the gate of p-channel field effect transistor 50 from charging to the same voltage as n-channel well 53 . Therefore, when the protected node reaches approximately positive 2V, the floating n-channel well of the p-channel FET is rapidly charged to approximately the same voltage as the protected node through the forward junction. If the capacitor 65 has sufficient permittivity, a relatively large gate coupling ratio can be provided, and the gate voltage will drift to a value less than 1V (for example, <1V) by the capacitor voltage divider (VWL*(1-GCR)), Close to the zero voltage of the p-type substrate 52 . Thus maintaining the negative bias voltage Vgb from the gate to the channel well, which is approximately lower than 1V in this figure, is sufficient to turn on the rapid discharge of the p-channel field effect transistor without charging the protected node during the process step.
在图3的电路中，上图案化导体层制成之后可为最上方的图案化导体层，且栅极和通道阱相连接。一些可能会发生充电的工艺，例如钝化或在上图案化导体覆盖其他层，在连接栅极和通道阱之后，由天线效应放电电路提供的保护可能较差。In the circuit of FIG. 3 , the upper patterned conductor layer can be the uppermost patterned conductor layer after fabrication, and the gate is connected to the channel well. Some processes where charging may occur, such as passivation or patterning conductors over other layers, may be less protected by the antenna effect discharge circuit after connecting the gate and channel well.
图7绘示另一种天线效应放电电路的实施例，可在形成用以连接栅极和通道阱的图案化导体层之后维持保护。当适合时，电路元件使用与图3相同的标记。本例中，在电容和电压供应电路之间加入开关，直到装置接收可关闭开关的运作电压之前，其允许一步骤保持场效应晶体管50、51的栅极从通道阱53、54分离。以此方法，可在整个工艺中防止天线效应。FIG. 7 illustrates another embodiment of an antenna effect discharge circuit that maintains protection after forming a patterned conductor layer connecting the gate and the channel well. Where appropriate, circuit elements use the same references as in FIG. 3 . In this example, a switch is added between the capacitor and the voltage supply circuit, which allows a step to keep the gates of the field effect transistors 50,51 separated from the channel wells 53,54 until the device receives an operating voltage that closes the switch. In this way, antenna effects can be prevented throughout the process.
本例中，用于p通道场效应晶体管50的开关为高电压n通道场效应晶体管70(例如图4所示的HV-NMOS)，其具有第一端(源极或漏极)，通过第一连接器70-1及导体57连接栅极，以及一第二端(源极或漏极)，其通过第二连接器70-2连接供应电压电路。连接器70-1、70-2的一个或两个可形成装置的图案化导体层的上部(较佳的为最上层)。n通道场效应晶体管70的栅极连接至电压供应电路，以于运作期间接受例如VPP的一偏压，以关闭开关。In this example, the switch for the p-channel field effect transistor 50 is a high voltage n-channel field effect transistor 70 (such as HV-NMOS shown in FIG. A connector 70-1 and conductor 57 are connected to the gate, and a second terminal (source or drain) is connected to the supply voltage circuit through the second connector 70-2. One or both of the connectors 70-1, 70-2 may form the upper portion (preferably the uppermost layer) of the patterned conductor layer of the device. The gate of the n-channel field effect transistor 70 is connected to the voltage supply circuit to receive a bias voltage such as VPP during operation to turn off the switch.
本例中，用于n通道场效应晶体管51的开关为高电压p通道场效应晶体管71(例如图4所示的HV-PMOS)，其具有第一端(源极或漏极)，通过第一连接器71-1及导体60连接栅极，以及一第二端(源极或漏极)，其通过第二连接器71-2连接供应电压电路。连接器71-1、71-2的一个或两个可形成装置的图案化导体层的上部(较佳的为最上层)。p通道场效应晶体管701栅极连接至电压供应电路，以于运作期间接受例如VNP的一偏压，以关闭开关。In this example, the switch for the n-channel field effect transistor 51 is a high voltage p-channel field effect transistor 71 (such as HV-PMOS shown in FIG. A connector 71-1 and the conductor 60 are connected to the gate, and a second terminal (source or drain) is connected to the supply voltage circuit through the second connector 71-2. One or both of the connectors 71-1, 71-2 may form the upper portion (preferably the uppermost layer) of the patterned conductor layer of the device. The gate of the p-channel field effect transistor 701 is connected to the voltage supply circuit to receive a bias voltage such as VNP during operation to turn off the switch.
以此方式，直到开关晶体管70、71被开启以关闭开关前，天线效应放电电路仍然有效。In this way, until the switch transistors 70, 71 are turned on to close the switch, the antenna effect discharge circuit is still effective.
图8是一天线效应放电电路的布局，包含耦接于该电压场效应晶体管的栅极的电容。本例中，布局形成在一p型基板100上。一n型通道阱103形成在基板100上。此外，形成一深n型阱101上，内部有一p型通道阱102。基板接触(如图4的104、110、111)可在阱周围排列，以在运作期间提供适当偏压。此外，保护环(未绘示)使用例如多晶硅层的导体在阱周围形成。深n型阱、p型基板和保护环可通过接点连接在一起，并且在操作期间接地。FIG. 8 is a layout of an antenna effect discharge circuit including a capacitor coupled to the gate of the voltage field effect transistor. In this example, the layout is formed on a p-type substrate 100 . An n-type channel well 103 is formed on the substrate 100 . In addition, a deep n-type well 101 is formed with a p-type channel well 102 inside. Substrate contacts such as 104, 110, 111 of FIG. 4 can be arranged around the well to provide proper bias during operation. Additionally, a guard ring (not shown) is formed around the well using a conductor such as a polysilicon layer. The deep n-type well, p-type substrate and guard ring can be connected together by a junction and grounded during operation.
一组高电压、n通道场效应晶体管在p型阱102内形成。本例中，阱102内有三个晶体管。第一晶体管包含漏极端202和源极端206。第二晶体管包括漏极端203和源极端207。第三晶体管包括漏极端204和源极端208。漏极端202、203和204分别连接下图案化导体层中的一个图案化导体210、211、212，例如第一金属层，或于由图中以小方格表示的层间连接器。源极端206、207、208连接图案化导体214、215、216，其连接到对应于由电路保护的节点。举例来说，图案化导体214可为第一金属层导体，连接到存储器结构中的共享源极线231，如图2所示。图案化导体215可为第二金属层导体，连接到存储器结构中的串选择线232，如图2所示。图案化导体216可为第一金属层导体，连接到一个或多个字线233，如图2所示。A set of high voltage, n-channel field effect transistors is formed within p-type well 102 . In this example, there are three transistors in well 102 . The first transistor includes a drain terminal 202 and a source terminal 206 . The second transistor includes a drain terminal 203 and a source terminal 207 . The third transistor includes a drain terminal 204 and a source terminal 208 . The drain terminals 202 , 203 and 204 are respectively connected to a patterned conductor 210 , 211 , 212 in the lower patterned conductor layer, such as the first metal layer, or an interlayer connector represented by a small square in the figure. Source terminals 206, 207, 208 are connected to patterned conductors 214, 215, 216, which are connected to corresponding nodes protected by the circuit. For example, the patterned conductor 214 can be a first metal layer conductor connected to the shared source line 231 in the memory structure, as shown in FIG. 2 . The patterned conductor 215 may be a second metal layer conductor connected to a string select line 232 in the memory structure, as shown in FIG. 2 . The patterned conductor 216 may be a first metal layer conductor connected to one or more word lines 233 as shown in FIG. 2 .
三个晶体管的栅极是由单一的图案化多晶硅导线200形成，其朝通道阱102之外的区域延伸，通道阱102位于第二、n型电容端扩散201之上，n型电容端扩散201作用为电容的第二端。多晶硅导线200在电容端扩散201之上的面积作为电容的第一端，且应大于p型阱102内晶体管的栅极面积，以如上所述建立高栅极耦合比。The gates of the three transistors are formed by a single patterned polysilicon wire 200, which extends towards the area outside the channel well 102, which is located on the second, n-type capacitor terminal diffusion 201, and the n-type capacitor terminal diffusion 201 Acts as the second terminal of the capacitor. The area of the polysilicon wire 200 above the capacitor terminal diffusion 201 serves as the first terminal of the capacitor and should be larger than the gate area of the transistor in the p-type well 102 to establish a high gate coupling ratio as described above.
图案化导体210、211、212如由图中的箭头标示，连接到p型基板100。The patterned conductors 210 , 211 , 212 are connected to the p-type substrate 100 as indicated by arrows in the figure.
图案化导体258藉层间连接器连接到栅极多晶硅导线200。相同地，图案化导体250藉层间连接器连接通道阱102。图案化导体258和250可以形成在装置上的图案化导体层的下方，例如在第一金属层内。导体258和250连接到上图案化导体层的导体260，此处标记为ML4，表示4道金属工艺。The patterned conductor 258 is connected to the gate polysilicon wire 200 by an interlayer connector. Similarly, the patterned conductor 250 is connected to the channel well 102 through an interlayer connector. Patterned conductors 258 and 250 may be formed below a patterned conductor layer on the device, eg, within the first metal layer. Conductors 258 and 250 are connected to conductor 260 of the upper patterned conductor layer, here labeled ML4, representing a 4-pass metal process.
另外，高电压、p通道场效应晶体管形成在n型通道阱103内。本例中，阱103内有三个晶体管。第一晶体管包括漏极端306和源极端302。第二晶体管包括漏极端307和源极端303。第三晶体管包括一个漏极端308和源极端304。漏极端306、307和308分别连接下图案化导体层中的一图案化导体314、315、316，例如第一金属层，或层间连接器。源极端302、303、304连接图案化导体310、311、312，其连接到对应于由电路保护的节点。例如，图案化导体310可连接共享源极线231，图案化导体311可连接串选择线232。图案化导体312可以连接到一个或多个字线233。In addition, high voltage, p-channel field effect transistors are formed within n-channel well 103 . In this example, there are three transistors in the well 103 . The first transistor includes a drain terminal 306 and a source terminal 302 . The second transistor includes a drain terminal 307 and a source terminal 303 . The third transistor includes a drain terminal 308 and a source terminal 304 . The drain terminals 306 , 307 and 308 are respectively connected to a patterned conductor 314 , 315 , 316 in the lower patterned conductor layer, such as the first metal layer, or an interlayer connector. Source terminals 302, 303, 304 are connected to patterned conductors 310, 311, 312, which are connected to corresponding nodes protected by the circuit. For example, the patterned conductor 310 can be connected to the shared source line 231 , and the patterned conductor 311 can be connected to the string selection line 232 . Patterned conductor 312 may be connected to one or more word lines 233 .
三个晶体管的栅极是由单一的图案化多晶硅导线300形成，其朝通道阱103之外的区域延伸，通道阱103位于第二、n型电容端扩散301之上，其作用为电容的第二端。多晶硅导线300在电容端扩散301之上的面积作为电容的第一端，且应大于p型阱103内晶体管的栅极面积，以如上所述建立高栅极耦合比。The gates of the three transistors are formed by a single patterned polysilicon wire 300, which extends towards the area outside the channel well 103, which is located above the second, n-type capacitor terminal diffusion 301, which acts as the first capacitor of the capacitor. Two ends. The area of the polysilicon wire 300 above the capacitor terminal diffusion 301 serves as the first terminal of the capacitor and should be larger than the gate area of the transistor in the p-type well 103 to establish a high gate coupling ratio as described above.
图案化导体314、315、316如图中的箭头所示连接到p型基板100。The patterned conductors 314, 315, 316 are connected to the p-type substrate 100 as indicated by the arrows in the figure.
图案化导体358藉层间连接器连接到多晶硅导线300。同样地，图案化导体350藉层间连接体连接到通道阱103。图案化导体358、350可形成在装置图案化导体层的下部之一，例如在第一金属层。导体358和350连接到上部图案化导体层的导体360，此处标记为ML4，表示4道金属工艺。The patterned conductor 358 is connected to the polysilicon wire 300 by an interlayer connector. Likewise, the patterned conductor 350 is connected to the channel well 103 by an interlayer connector. The patterned conductor 358, 350 may be formed in one of the lower portions of the patterned conductor layer of the device, for example in the first metal layer. Conductors 358 and 350 are connected to conductor 360 of the upper patterned conductor layer, here labeled ML4, representing a 4-pass metal process.
图9是集成电路525的简化方块图，包含存储器阵列510，其包括天线放电电路527。一些实施例中，阵列510是一个三维存储器，并且包括多级单元。行译码器511耦接存储器阵列510中的多个字线、串选择线和接地选择线(512)。区块513的级/列译码器耦接至一组页缓冲器516，在该示例中通过总线517，并经由全局位线和源极线514。地址被供应至总线515、级/列译码器(区块513)和行译码器(区块511)。数据经由集成电路上其他电路系统524的数据输入线路(例如包含输入/输出端)供应，例如一般用途之处理器、特殊用途的应用电路，或结合模块以提供阵列510所支持的系统单芯片(system-on-a-chip)功能。数据经由数据输入线路523，输入/输出端、或从集成电路525内部或外部其他的数据源接收。FIG. 9 is a simplified block diagram of integrated circuit 525 , including memory array 510 , which includes antenna discharge circuit 527 . In some embodiments, array 510 is a three-dimensional memory and includes multiple levels of cells. The row decoder 511 is coupled to a plurality of word lines, string select lines and ground select lines in the memory array 510 (512). The stage/column decoders of block 513 are coupled to a set of page buffers 516 , in this example by bus 517 , and via global bit and source lines 514 . The address is supplied to bus 515, level/column decoder (block 513) and row decoder (block 511). Data is supplied via data input lines (eg, including input/output ports) from other circuitry 524 on the integrated circuit, such as a general-purpose processor, a special-purpose application circuit, or a combination of modules to provide a system-on-a-chip (SOC) supported by array 510. system-on-a-chip) function. Data is received via data input lines 523 , input/output terminals, or other data sources internal or external to integrated circuit 525 .
控制器，于本例中为状态机519，提供讯号控制偏压安排供应电压的产生，经由区块518中的电压供应电路或提供多种操作，例如读取，擦除，编程。控制器可以使用本领域已知的专用逻辑电路。在其他实施例中，控制器包括一般用途处理器，而一般用途处理器可以施行于同样的集成电路并执行计算机程序以控制装置的操作。在另外的实施例中，控制器的执行可以利用特殊用途逻辑电路以及一般用途处理器的组合。The controller, in this example the state machine 519, provides signals to control the bias to arrange the generation of the supply voltage through the voltage supply circuit in the block 518 or provide various operations, such as reading, erasing, programming. The controller may use dedicated logic circuitry known in the art. In other embodiments, the controller includes a general purpose processor, and the general purpose processor may be implemented on the same integrated circuit and execute a computer program to control the operation of the device. In other embodiments, the implementation of the controller may utilize a combination of special purpose logic circuits and general purpose processors.
如图3和图7的电路所示，天线效应放电电路527具有连接栅极的一电容，其耦接范例中存储器阵列的导体，由导线526表示。导线526可以是字线、位线、串选择线、接地选择线，或可以在工艺中充电的其他导电线路。天线效应放电电路527藉装置最上面的图案化导体层528，连接电压供应电路518，在此标记为ML4为，表示4金属装置。电压供应电路518包括电压提供电路，例如正和负电压的电荷泵，水平转换器(level shifters)和电压调节器(voltage regulators)。在一代表性的三维NAND装置中，正电压和负电压的电荷泵可以产生高达30V和-10V的运作电压。当然，此处最高值的正运作电压与负运作电压标示为VPP和VNP，需要特定的装置。As shown in the circuits of FIG. 3 and FIG. 7 , the antenna effect discharge circuit 527 has a capacitor connected to the gate, which is coupled to a conductor of the memory array in the example, represented by the conductor 526 . Conductor 526 may be a word line, a bit line, a string select line, a ground select line, or other conductive lines that may be charged during the process. The antenna effect discharge circuit 527 is connected to the voltage supply circuit 518 through the uppermost patterned conductor layer 528 of the device, and is marked as ML4 here, representing a 4-metal device. The voltage supply circuit 518 includes voltage supply circuits such as charge pumps for positive and negative voltages, level shifters and voltage regulators. In a typical 3D NAND device, positive and negative charge pumps can generate operating voltages as high as 30V and -10V. Of course, the highest positive and negative operating voltages here are denoted VPP and VNP, requiring specific devices.
一特定的集成电路内所提供的天线效应放电电路数目依工艺环境、的可用的空间，以及产品的需求而定。在一些产品中，可能是每字线包括一天线效应放电电路。在其他例子的产品中，多个字线可共享一保护装置。在装置上集成电路系统的其他节点亦可被保护。The number of AED circuits provided in a particular integrated circuit depends on the process environment, available space, and product requirements. In some products, each word line may include an antenna effect discharge circuit. In other example products, multiple word lines may share a protection device. Other nodes of the integrated circuit system on the device may also be protected.
图10为工艺的简化流程图，包括如本文所述等离子体效应放电电路。此方法包括在基板(600)上形成集成电路。还有，此方法包括于基板上形成天线效应放电电路(601)，以及使用电容耦接天线效应放电电路的栅极与基板(602)。工艺包括提供电压供应电路于集成电路上，或耦接集成电路(603)。最后，在工艺时使用上层(较佳的为最上端)的图案化导电层连接栅极与电压供应电路(604)。Figure 10 is a simplified flow diagram of a process including a plasma effect discharge circuit as described herein. The method includes forming an integrated circuit on a substrate (600). In addition, the method includes forming an antenna effect discharge circuit (601) on a substrate, and coupling the grid of the antenna effect discharge circuit and the substrate using a capacitor (602). The process includes providing a voltage supply circuit on or coupled to the integrated circuit (603). Finally, the upper layer (preferably the uppermost) patterned conductive layer is used to connect the gate and the voltage supply circuit during the process ( 604 ).
虽然图10中未绘示，此工艺可包括在栅极和电压供应电路之间提供一开关，如图7所示。开关可配置为在栅极运作期间关密，且藉开关连接电压供应电路。开关可使用以高电压场效应晶体管，例如HV-NMOS或HV-PMOS装置，其具有连接到电压供应电路的栅极。Although not shown in FIG. 10 , the process may include providing a switch between the gate and the voltage supply circuit, as shown in FIG. 7 . The switch can be configured to be closed during gate operation, and the voltage supply circuit is connected by the switch. The switch may use a high voltage field effect transistor, such as a HV-NMOS or HV-PMOS device, with a gate connected to a voltage supply circuit.
其中形成天线效应放电电路的方法包括形成一n型通道阱及一p型通道阱于基板上，以及一第一电容端扩散及一第二电容端扩散于基板上。一p通道场效应晶体管形成于n型通道阱内上，其具有一栅极、一源极及一漏极，源极及漏极位于n型通道阱中。一n通道场效应晶体管形成于p型通道阱中，其具有一栅极、一源极及一漏极，源极及漏极位于p型通道阱中。此外，形成一第一电容，具有一第一端及一第二端，第一端位于或连接于第一电容端扩散，第二端耦接p通道场效应晶体管的栅极。形成一第二电容，具有一第一端及一第二端，第一端位于或连接于第一电容端扩散，第二端耦接n通道场效应晶体管的栅极。此工艺包括以一图案化导体连接p通道场效应晶体管的源极与漏极的其中之一和受保护节点，源极与漏极的其中之另一连接基板。此外，此工艺包括以一图案化导体连接n通道场效应晶体管之源极与漏极的其中之一和受保护节点，源极与漏极的其中之另一连接基板。The method for forming the antenna effect discharge circuit includes forming an n-type channel well and a p-type channel well on the substrate, and spreading a first capacitor terminal and a second capacitor terminal on the substrate. A p-channel field effect transistor is formed on the n-type channel well, and has a gate, a source and a drain, and the source and drain are located in the n-type channel well. An n-channel field effect transistor is formed in a p-type channel well, and has a gate, a source and a drain, and the source and drain are located in the p-type channel well. In addition, a first capacitor is formed, which has a first terminal and a second terminal, the first terminal is located at or connected to the diffusion of the first capacitor terminal, and the second terminal is coupled to the gate of the p-channel field effect transistor. A second capacitor is formed, which has a first terminal and a second terminal, the first terminal is located at or connected to the diffusion of the first capacitor terminal, and the second terminal is coupled to the gate of the n-channel field effect transistor. The process includes connecting one of the source and the drain of the p-channel field effect transistor and the protected node with a patterned conductor, and the other of the source and the drain is connected to the substrate. In addition, the process includes connecting one of the source and the drain of the n-channel field effect transistor and the protected node with a patterned conductor, and the other of the source and the drain is connected to the substrate.
本例中，提供电压供应电路的步骤包括提供一电压供应电路，其具有一第一电压输出，可提供VPP，并通过上层内的第一图案化导体连接p通道场效应晶体管的栅极，以在运作期间关闭p通道场效应晶体管；以及具有第一电压输出，可提供VNP，并通过上层内的第二图案化导体连接n通道场效应晶体管的栅极，以在运作期间关闭n通道场效应晶体管。In this example, the step of providing a voltage supply circuit includes providing a voltage supply circuit having a first voltage output that can provide VPP, and connecting the gate of the p-channel field effect transistor through a first patterned conductor in the upper layer to Turning off the p-channel field effect transistor during operation; and having a first voltage output that provides VNP and is connected to the gate of the n-channel field effect transistor through a second patterned conductor in the upper layer to turn off the n-channel field effect transistor during operation transistor.
提供一开关的步骤可以包括于装置内形成一第一开关，其具有一第一端和一第二端，第一端连接上层内的第一图案化导体，第二端连接电压供应电路，配置第一开关在运作期间关闭；以及于装置上形成第二开关，其具有一第一端和一第二端，第一端连接该上层内的第一图案化导体，第二端连接电压供应电路，配置第二开关在运作期间关闭。The step of providing a switch may include forming a first switch in the device, which has a first terminal and a second terminal, the first terminal is connected to the first patterned conductor in the upper layer, and the second terminal is connected to the voltage supply circuit, configured The first switch is closed during operation; and a second switch is formed on the device, which has a first terminal and a second terminal, the first terminal is connected to the first patterned conductor in the upper layer, and the second terminal is connected to the voltage supply circuit , configuring the second switch to be closed during operation.
描述一种新的天线保护电路及其制造方法。如图3、图5和图6所示，n通道和p通道场效应晶体管的栅极在第一金属层ML1之后分别被浮接，而不是如1图的现有技术电路中连接。A new antenna protection circuit and its fabrication method are described. As shown in FIG. 3 , FIG. 5 and FIG. 6 , the gates of the n-channel and p-channel field effect transistors are respectively floating behind the first metal layer ML1 , instead of being connected as in the prior art circuit in FIG. 1 .
栅极连接到大型电容，且耦接于到P型基板。在天线充电期间，栅极因电容而接近p型基板电位。这使得场效应晶体管更容易导通。正电荷将通过p通道场效应晶体管而放出，而负电荷将通过n通道场效应晶体管放出。实验数据显示，在新的保护电路中使用的p通道场效应晶体管与n通道场效应晶体管可以在小于2V的正或负值作用，进而为新设备提供非常优异的工艺内天线保护。另外，证明较大的电容面积与栅极面积笔会导致较高的放电电流。The gate is connected to a bulk capacitor and coupled to a P-type substrate. During antenna charging, the gate is brought close to the p-type substrate potential due to capacitance. This makes it easier for the field effect transistor to turn on. Positive charge will be discharged through the p-channel field effect transistor, and negative charge will be discharged through the n-channel field effect transistor. Experimental data shows that the p-channel FETs and n-channel FETs used in the new protection circuit can function at positive or negative values less than 2V, thereby providing excellent in-process antenna protection for the new device. In addition, it was proved that larger capacitor area and gate area pen will lead to higher discharge current.
较高的栅极到基板耦合比(gate to substrate coupling ratio，GCR)可使栅极更接近基板电位，提供更低的导通电压(＜2V)与更加的保护。A higher gate-to-substrate coupling ratio (GCR) can make the gate closer to the substrate potential, providing lower turn-on voltage (<2V) and better protection.
在例如最上端金属层的最后图案化导体层，天线保护电路连接电压供应电路的VPP和VNP端，以使它们在操作中关闭，且不会影响装置的运作。On the last patterned conductor layer such as the uppermost metal layer, the antenna protection circuit connects the VPP and VNP terminals of the voltage supply circuit so that they are turned off during operation without affecting the operation of the device.
为了防止钝化过程或其他高层工艺中任何可能的充电，可于保护电路栅极及电压供应电路间加入缓冲晶体管开关。To prevent any possible charging during the passivation process or other high-level processes, a buffer transistor switch can be added between the gate of the protection circuit and the voltage supply circuit.
新的天线保护电路可应用于普通的闪存阵列、其他存储器装置、逻辑电路，以及其他类型的集成电路装置。The new antenna protection circuit can be applied to common flash memory arrays, other memory devices, logic circuits, and other types of integrated circuit devices.
极低的保护电压(＜+/-2V)的可应用进阶存储器装置，例如可编程电阻的ReRAM或相变化PCRAM，其工艺间充电的低电压(＜3V)可能会导致设备效能的劣化。For advanced memory devices with extremely low protection voltage (<+/-2V), such as programmable resistance ReRAM or phase-change PCRAM, the low voltage (<3V) charged between processes may degrade device performance.
工艺中的充电效应过会劣化3D NAND闪存集成电路的初始Vt分布。使用电容耦合浮接栅极(capacitive coupled floating gate，CCFG)CMOS电路的天线保护电路的范例如前所述，可应用在存储器集成电路的字线(WL)和选择晶体管(SSL)的译码器。电路的实验结果显示，放电的极低导通电压(＜+/-2V)，提供存储器装置的保护。利用这种技术，一个完全集成的三维NAND快闪装置在存储器阵列显示优异的初始阈值电压Vt分布，不受充电效应影响。The charging effect in the process will degrade the initial Vt distribution of the 3D NAND flash IC. An example of an antenna protection circuit using a capacitive coupled floating gate (CCFG) CMOS circuit, as described above, can be applied to a decoder for word lines (WL) and select transistors (SSL) of memory integrated circuits . The experimental results of the circuit show that the extremely low turn-on voltage (<+/-2V) of the discharge provides the protection of the memory device. Using this technique, a fully integrated 3D NAND flash device exhibits excellent initial threshold voltage Vt distribution in a memory array, independent of charging effects.
此外，串选择线SSL晶体管阈值电压Vt分布(变异)可对最小Vdd的偏压产生影响。随着SSL Vt分布的进步，可如图3、图5及图6一般使用天线保护电路，其证明了3D VG NAND闪存可支持小于1.6V的Vdd以及成功编程窗口。In addition, the string selection line SSL transistor threshold voltage Vt distribution (variation) can have an effect on the bias voltage of the minimum Vdd. With the advancement of SSL Vt distribution, the antenna protection circuit can be used as shown in Figure 3, Figure 5 and Figure 6, which proves that 3D VG NAND flash can support Vdd less than 1.6V and a successful programming window.
本文所描述的天线保护电路可应用于字线WL、串选择线SSL/接地选择线GSL译码器。三维NAND快闪集成电路的实验结果证实。The antenna protection circuit described herein can be applied to word line WL, string select line SSL/ground select line GSL decoders. The experimental results of 3D NAND flash integrated circuit confirmed it.
完全集成的拆分页3DVG NAND闪存在S.H.Chen，H.T.Lue，et al.的“A highlyscalable8-layer vertical gate3D NAND with split-pahe bit line layout andefficient binary-sum MilC(Minimal incremental layer cost)staircase contacts“，IEDM pp.21-24，2012，有详细说明，此文件中更研究了周边CMOS装置。Fully integrated split-page 3DVG NAND flash in S.H.Chen, H.T.Lue, et al. "A highlyscalable8-layer vertical gate3D NAND with split-pahe bit line layout and efficient binary-sum MilC(Minimal incremental layer cost) staircase contacts", IEDM pp.21-24, 2012, has a detailed description, and the peripheral CMOS device is studied in this document.
例如图3、图5及图6的保护电路配置在受测装置。For example, the protection circuits shown in FIG. 3 , FIG. 5 and FIG. 6 are configured in the device under test.
图11绘示在CCFG NMOS保护电路的装置中，漏极电流与漏极电压(IdVd)的曲线，以及漏极电压与基底电流Ib(IbVd)的曲线，其是处于如图5所示的状态，当栅极和PWI浮接时，p基板、源极和DNW接地。其不对正偏压放电，但很容易于低于-2V开启，对负电压放电。在-7V时，可观察到明显的基底电流(Ib)。这是由于寄生双极导通透过N+-PW1-DNW寄生BJT开启。FIG. 11 shows the curves of the drain current and the drain voltage (IdVd) and the drain voltage and the base current Ib (IbVd) in the device of the CCFG NMOS protection circuit, which are in the state shown in FIG. 5 , when the gate and PWI are floating, the p substrate, source and DNW are grounded. It does not discharge to positive biases, but turns on easily below -2V and discharges to negative voltages. At -7V, a significant basal current (Ib) was observed. This is due to the parasitic bipolar turn-on through the N+-PW1-DNW parasitic BJT turn-on.
图12所示的实验数据包括在CCFG PMOS保护电路的装置中，漏极电流与漏极电压(IdVd)的曲线，以及漏极电压与基底电流Ib(IbVd)的曲线，其是处于如图5所示的状态，其栅极和N阱为浮接。其显示低的导通电压(＜+2V)。没有观察到寄生双极导通模式，因此也没有观测到基底电流。导通电压在正偏压时低于2V，于低电压下提供优异的保护。基底电流(Ib)很小，显示无寄生BJT模式。The experimental data shown in Fig. 12 includes in the device of CCFG PMOS protection circuit, the curve of drain current and drain voltage (IdVd), and the curve of drain voltage and base current Ib (IbVd), and it is in Fig. 5 In the state shown, the gate and N-well are floating. It exhibits low turn-on voltage (<+2V). No parasitic bipolar conduction mode, and thus no substrate current, was observed. The turn-on voltage is lower than 2V under positive bias, providing excellent protection under low voltage. The base current (Ib) is small, showing a parasitic-free BJT mode.
图13所示的实验数据包括完整CCFG CMOS保护电路的放电电流(当栅极和阱浮置)，类似图5和图6。其显示低于+/-2V的极低导通电压，提供装置的理想保护。在FG面积上较高的电容比提供更高的导通电流。值得注意的是，NMOS和PMOS两者可为高电压(HV)装置，以维持WL、SSL或GSL的高运作电压。The experimental data shown in Figure 13 includes the discharge current (when the gate and well are floating) of the complete CCFG CMOS protection circuit, similar to Figures 5 and 6. It exhibits an extremely low turn-on voltage of less than +/-2V, providing ideal protection for the device. A higher capacitance ratio over the FG area provides a higher on-current. It is worth noting that both NMOS and PMOS can be high voltage (HV) devices to maintain the high operating voltage of WL, SSL or GSL.
图14为测量8层3DVG装置的TEM剖面图的影像。图15绘示受测装置的多层中，存储器单元的初始阈值电压分布。由于保护电路，如图15中的初始状态具有优异且接近正常的Vt分布。意料之中，因为存储层之间的工艺和尺寸偏差，PL1到PL88层之间观察到某些特定偏差。FIG. 14 is an image of a TEM cross-sectional view of an 8-layer 3DVG device measured. FIG. 15 shows initial threshold voltage distributions of memory cells in multiple layers of a device under test. Due to the protection circuit, the initial state as in Fig. 15 has excellent and close to normal Vt distribution. As expected, some specific deviations were observed between PL1 to PL88 layers due to process and dimensional deviations between memory layers.
图16绘示SSL Vt分布。SSL的内置sigma可小于250mV。透过某些藉一个软编程和验证的微调，sigma可以进一步减少到近100mV。Figure 16 shows the SSL Vt distribution. The built-in sigma of SSL can be less than 250mV. With some fine-tuning by a soft programming and verification, sigma can be further reduced to nearly 100mV.
SSL分布的影响绘示于图17和图18。图17是一简化NAND串的示意图。在自增压编程期间，Vdd施加在BL偏压和SSL栅极偏压上。图18绘示随着σ(sigma)的增加，3个SSL阈值电压的分布图(Vt范围)。Vt范围的下边界应高于0.4V，以保证足够的穿透免疫，以维持自增压。另一方面，Vt范围的较高边界限制SSL和BL上的最小Vdd应用。较严格的SSL分布(下σ)可以降低VDD。The effect of SSL distribution is plotted in Figure 17 and Figure 18. Figure 17 is a schematic diagram of a simplified NAND string. During self-boost programming, Vdd is applied on the BL bias and SSL gate bias. Fig. 18 shows the distribution graphs (Vt range) of 3 SSL threshold voltages as σ(sigma) increases. The lower boundary of the Vt range should be above 0.4V to ensure sufficient shoot-through immunity to maintain self-boosting. On the other hand, the upper bounds of the Vt range limit the minimum Vdd application on SSL and BL. Tighter SSL distribution (lower σ) can reduce VDD.
SSL的严格Vt分布对减少Vdd有重要影响。图19绘示用于编程棋盘窗口测试时，受测装置的低和高阈值状态，其显示改进的SSL Vt分布，受测的3D VG NAND快闪可在最小Vdd＝1.6V运作。低Vdd的有助于减少功率消耗。The tight Vt distribution of SSL has an important effect on reducing Vdd. Figure 19 shows the low and high threshold states of the tested device for the programming checkerboard window test, which shows an improved SSL Vt distribution, and the tested 3D VG NAND flash can operate at a minimum Vdd=1.6V. Low Vdd helps reduce power consumption.
图20为应用于CMOS译码器设计的天线保护电路的电路图范例。天线效应放电电路保护一电路，其为CMOS译码器的一部分，包括一个p通道场效应晶体管772和一n通道场效应晶体管771，具有耦接到节点755的漏极，节点连接到字线，并被译码器驱动。根据译码器的设计，晶体管771、772的栅极连接到译码信号。n通道场效应晶体管771形成在P型阱773。p通道场效应晶体管772形成在n型阱774。FIG. 20 is an example circuit diagram of an antenna protection circuit applied to a CMOS decoder design. The antenna effect discharge circuit protects a circuit, which is part of a CMOS decoder, including a p-channel field effect transistor 772 and an n-channel field effect transistor 771, having a drain coupled to a node 755, which is connected to a word line, and is driven by the decoder. Depending on the decoder design, the gates of the transistors 771, 772 are connected to the decode signal. The n-channel field effect transistor 771 is formed in the p-type well 773 . P-channel field effect transistor 772 is formed in n-type well 774 .
综上所述，虽然本发明已以实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视随附的权利要求范围所界定的为准。To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410258533.XACN105185776B (en) | 2014-06-11 | 2014-06-11 | Antenna effect discharge circuit and method for manufacturing the same |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410258533.XACN105185776B (en) | 2014-06-11 | 2014-06-11 | Antenna effect discharge circuit and method for manufacturing the same |
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| CN105185776A CN105185776A (en) | 2015-12-23 |
| CN105185776Btrue CN105185776B (en) | 2018-08-31 |
| Application Number | Title | Priority Date | Filing Date |
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| CN201410258533.XAActiveCN105185776B (en) | 2014-06-11 | 2014-06-11 | Antenna effect discharge circuit and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9773811B2 (en)* | 2016-02-22 | 2017-09-26 | Globalfoundries Inc. | Reducing antenna effects in SOI devices |
| CN110098726B (en)* | 2018-01-29 | 2020-08-14 | 株洲中车时代电气股份有限公司 | Switch device buffer circuit board |
| CN113095036B (en)* | 2021-03-30 | 2024-03-22 | 上海华力微电子有限公司 | Method for judging antenna effect of three-dimensional structure |
| US11521695B1 (en)* | 2021-06-14 | 2022-12-06 | Texas Instruments Incorporated | Digital bit generators for trim circuits |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5946177A (en)* | 1998-08-17 | 1999-08-31 | Motorola, Inc. | Circuit for electrostatic discharge protection |
| CN102610259A (en)* | 2011-01-19 | 2012-07-25 | 旺宏电子股份有限公司 | Memory device and method of operating the same |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5946177A (en)* | 1998-08-17 | 1999-08-31 | Motorola, Inc. | Circuit for electrostatic discharge protection |
| CN102610259A (en)* | 2011-01-19 | 2012-07-25 | 旺宏电子股份有限公司 | Memory device and method of operating the same |
| Publication number | Publication date |
|---|---|
| CN105185776A (en) | 2015-12-23 |
| Publication | Publication Date | Title |
|---|---|---|
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