Accompanying drawing explanation
Fig. 1 is the prior art antenna effect discharge circuit schematic diagram based on dynamic threshold voltage MOSFE.
Fig. 2 is the stereogram of prior art integrated circuit one example, comprises multiple patterning conductor layer, and it can be protected by antenna effect discharge circuit as described below.
Fig. 3 is the schematic diagram of antenna effect discharge circuit, comprises the electric capacity of the grid being couple to field-effect transistor.
Fig. 4 illustrates the configuration of the device substrate of antenna effect discharge circuit, comprises high voltage as described below, n passage and p channel fet.
Before Fig. 5 is formation the superiors patterning conductor layer, the schematic diagram of antenna effect discharge circuit, its electric discharge illustrating negative voltage concentrates on shielded node.
Before Fig. 6 is formation the superiors patterning conductor layer, the schematic diagram of antenna effect discharge circuit, its electric discharge illustrating positive voltage concentrates on shielded node.
Fig. 7 is the embodiment of another kind of antenna effect discharge circuit, comprises the electric capacity of the grid coupling field-effect transistor, with the switch between grid and voltage supply circuit.
Fig. 8 is the layout of antenna effect discharge circuit in an embodiment, in order to the multiple nodes on Protective IC.
Fig. 9 is the simplification calcspar of integrated circuit memory array, comprises antenna effect discharge circuit as described herein.
The simplified flow chart of Figure 10 method for manufacturing integrated circuit, it utilizes antenna effect discharge circuit as described herein.
Figure 11 illustrates in the device of CCFGNMOS protective circuit, the curve of drain current and drain voltage (IdVd), and the curve of drain voltage and substrate current Ib (IbVd).
Experimental data shown in Figure 12 is included in the device of CCFGPMOS protective circuit, the curve of drain current and drain voltage (IdVd), and the curve of drain voltage and substrate current Ib (IbVd).
Experimental data shown in Figure 13 comprise complete CCFGCMOS protective circuit discharging current (when grid and trap floating), similar Fig. 5 and Fig. 6.
Figure 14 is the image of the TEM profile of measurement 8 layers of 3DVG device.
Figure 15 illustrates in the multilayer of device under test, the initial threshold voltage distribution of memory cell.
The SSLVt that Figure 16 illustrates by slowdown monitoring circuit distributes.
Figure 17 is the schematic diagram that a simplification NAND goes here and there.
Figure 18 illustrates the increase along with σ, the distribution map (Vt scope) of 3 SSL threshold voltages.
When Figure 19 illustrates and tests for chessboard window of programming, the low and threshold state of device under test.
Figure 20 is the circuit diagram example of the antenna protective circuit being applied to CMOS design of encoder.
[symbol description]
102-105,112-115,171-178: active layer band
102B-105B, 112A-115A: contact pad
109,119:SSL grid structure
121-1-121-N: wordline
126,127: ground connection selects line GSL
161-168: memory cell
172-175: inter-layer connectors
180: insulation layer of top end band
181-187: insulating barrier band
188: bottom active layer band
190: wire
201: the first memory cell
203: the three memory cell
210-240,610-640: secondary lamination
211,221,231,241: the first active layer bands
212,222,232,242: the first insulating barrier bands
231,223,233,243: the second active layer bands
214,224,234,244: the second insulating barrier bands
250,650: insulation layer of top end
271-272: multiple tier array
290: conductive material layer
295: straight line
305,505: touchdown area
390,590,690,790,890,990: etching mask
391,392,591,592,691-698,795-798,893-894,897-898,992,994,996,998: mask open
611,621,631,641: the first active layers
612,622,632,642: the first insulating barriers
613,623,633,643: the second active layers
614,624,634,644: the second insulating barriers
750,760,770,780,830,840,870,880,920: through hole
765: certain depth
1010-1050,1110-1140: step
1200: integrated circuit
1205: data input line
1210: controller
1220,1280: block
1230,1255,1275: bus
1240: column decoder
1245: wordline
1250: data base decoder
1260: memory array
1265: bit line
1270: row decoder
1285: data output line
1290: outlet line
O1-O4: insulating barrier
P1-P4: active layer
ML1, ML2, ML3: metal level
Embodiment
The detailed description of the embodiment of the present invention please refer to Fig. 1 to Figure 20.
Fig. 1 illustrates the protective circuit for antenna effect in prior art, its based on dynamic threshold MOS transistor to 10,11.The drain electrode of PMOS transistor couples substrate ground 12.In the same manner, the drain electrode of nmos pass transistor 11 is couple to substrate ground 12.Passage trap 13 in the channel region of PMOS transistor connects the grid of PMOS transistor by lower patterned conductor (such as the first metal layer).In the same manner, the passage trap 14 in the channel region of nmos pass transistor 11 is connected to the grid of nmos pass transistor 11 by lower patterned conductor (such as the first metal layer).The source electrode connected node 15 of PMOS transistor 10 and nmos pass transistor 11, it is protected to avoid the charge concentration caused by antenna effect.
" source electrode " and " drain electrode " noun, according to usage according to main current flow direction in transistor, specifies the terminal of field-effect transistor.In some cases, this description traditional is a bit comparatively fuzzy, such as, when device supports bidirectional current, and when tracing device has the terminal of symmetrical structure." source electrode " and " drain electrode " noun only for giving two terminals differences of field-effect transistor, does not mean main current flow direction or a terminal structure.Therefore, " source electrode " and " drain electrode " herein two noun can exchange mutually.
MOS is enough thick to the gate oxide of 10,11, maintains high voltage running to make flash memory device or other high-voltage integrated circuits.The same steps as produced thick-oxide charge pump transistor can being used, manufacturing the thick grid oxic horizon of flash memory device easily.
In process, positive charge is transmitted to ground connection 12 by PMOS transistor 10, and negative electrical charge is transmitted to ground connection at extremely low voltage via nmos pass transistor 11.For example, nmos pass transistor 11 will the conducting when close knot forward cut-in voltage (such as 0.6V).Similarly, PMOS transistor will at voltage close to conducting during knot forward cut-in voltage (such as-0.6V).For the discussion of the running of dynamic threshold mos device, can refer to IEEEELECTRONDEVICES, Vol.38, No.11, in November, 1991.Also can refer to United States Patent (USP) 7,196,369, denomination of invention " PLASMADAMAGEPROTECTIONCIRCUITFORASEMICONDUCTORDEVICE ", date of issue on March 27th, 2007.
During integrated circuit running, the grid mat circuit 16 of PMOS device 10 connects high positive voltage VPP, and VPP is enough high with when the highest operation current potential puts on protected node, can shutoff device 10.Similarly, the grid mat circuit 17 of NMOS device 11 connects high negative voltage VNP, and it has enough sizes, when the most negative operation current potential puts on protected node, and can shutoff device 11.
During technique, if the voltage on protected node raises suddenly, in the grid of transistor and the charging of edge of substrate by very fast, dynamic threshold structure as shown in Figure 1.So may occur that low-down grid is to substrate potential, makes opening device very difficult.Therefore, the protective circuit of Fig. 1 possibly cannot be opened under certain conditions completely.Therefore, its protection provided may not be very effective for the repid discharge stored charge of protected node, such as, is exposed to the wordline of a large amount of charge effect in technique.
Fig. 2 illustrates the stereogram of three dimensional NAND flash memory array architectures, and the device herein as example has multiple patterning conductor layer, comprises patterned polysilicon layer and patterned metal layer, and can use antenna effect discharge circuit described herein.With reference to United States Patent (USP) 8,503,213.Certainly, other uses the device of multiple patterning conductor layer that antenna effect discharge circuit as herein described also can be used to protect.In Fig. 2, insulating material removes by figure, to expose more structure.For example, insulating material system between semiconductor layer band, remove within carinate lamination, and removes between the carinate lamination of semiconductor layer band.
Multiple tier array is formed on an insulating barrier, and comprises multiple patterned polysilicon layer, its provide multiple wordline 425-1 ..., 425-n-1,425-n, wordline and carinate lamination conformal.This little carinate lamination comprises multiple semiconductor layer band 412,413,414,415.Semiconductor layer band on same plane is by the mutual electric property coupling of hierarchic structure.
Hierarchic structure 412A, 413A, 414A, 415A stop semiconductor layer band, such as semiconductor layer band 412,413,414,415.As shown in the figure, these hierarchic structure 412A, 413A, 414A, 415A are electrically connected to different bit lines, to connect the decoding circuitry selecting specific plane in array.These hierarchic structure 412A, 413A, 414A, 415A, can when multiple carinate lamination is defined simultaneously patterning.
Hierarchic structure 402B, 403B, 404B, 405B stop semiconductor layer band, as semiconductor layer band 402,403,404,405.As shown in the figure, these hierarchic structure 402B, 403B, 404B, 405B are electrically connected to different bit lines, in order to connect the decoding circuitry being positioned at the specific plane of array.These hierarchic structure 402B, 403B, 404B, 405B, can when multiple carinate lamination is defined simultaneously patterning.
In this configuration, the lamination of any given semiconductor layer band and hierarchic structure 412A, 413A, 414A, 415A, or hierarchic structure 402B, any one connects in 403B, 404B, 405B, but and both non-concurrent connections.The lamination of semiconductor layer band have two kinds of rightabouts one of them, one be bit line end to source electrode line extreme direction, one is that source electrode line end is to bit line extreme direction.For example, semiconductor layer band lamination 412,413,414,415 has bit line end to source electrode line end side line; Semiconductor layer band lamination 402,403,404,405 has source electrode line end to bit line extreme direction.
Semiconductor layer band lamination 412,413,414,415 wherein one end ends at hierarchic structure 412A, 413A, 414A, 415A, the other end is through SSL grid structure 419, and ground connection selects line GSL426, wordline 425-1WL to 425-NWL, ground connection selects line GSL426, and ends at corresponding source electrode line.Semiconductor layer band lamination 412,413,414,415 there is no with hierarchic structure 402B, 403B, 404B, 405B and is connected.
The lamination 402,403,404,405 of semiconductor layer band wherein ends at hierarchic structure 402B, 403B, 404B, 405B in one end, the other end is through SSL grid structure 409, ground connection selects line GSL427, wordline 425-NWL to 425-1WL, ground connection selects line GSL426, and ends at source electrode line (cover by other parts of this figure).The lamination 402,403,404,405 of semiconductor layer band can not arrive hierarchic structure 412A, 413A, 414A, 415A.
As existing graphic described by, a storage material layer separates wordline 425-1 to 425-N from semiconductor layer band 412-415 and 402-405.Ground connection select line GSL426 and ground connection select line GSL427 and carinate lamination conformal, similar with wordline.
Bit line and string are selected linearly to be formed in metal level ML1, ML2 and ML3.
Transistor is formed in hierarchic structure 412A, between 413A, 414A and wordline 425-1.In the transistor, semiconductor layer band (such as 413) is as the channel region of device.The same steps patterning that SSL grid structure (such as 419,409) is defined at wordline 425-1 to 425-n.Silicide layer can be selected line and grid structure 409,419 are formed along the top surface of wordline, ground connection.Storage material layer can be used as the gate dielectric of transistor.These transistors select grid as string, couple decoding circuit, in order to select specific carinate lamination in array.
The first metal layer ML1 comprises string and selects line, has and the longitudinal direction being parallel to semiconductor material layer band.These ML1 go here and there and select line to be connected to different SSL grid structures (such as 409,419) by inter-layer connectors.
Second metal level ML2 comprises string and selects line, has the Width being parallel to wordline.These ML2 go here and there and select line to be connected to different ML1 string selection lines by inter-layer connectors.
In conjunction with, these ML1 go here and there and select line and ML2 string to select line to allow a string to select signal to select the specific lamination of semiconductor layer band.
The first metal layer ML1 also comprises 2 source electrode lines, and it has the Width being parallel to wordline.
3rd metal level ML3 comprises bit line, has the longitudinal direction being parallel to semiconductor material layer band.Different bit lines is electrically connected to different step 412A, 413A, 414A, 415A and 402B, 403B, 404B, 405B of different hierarchic structure by inter-layer connectors.These ML3 bit lines allow bit line signal to select the specified level face of semiconductor layer band.
4th metal level (ML4 does not illustrate) may be used for connecting peripheral circuit to memory array, such as driver, induction amplifier, decoder, voltage supply electric organ etc.
In the through hole of inter-layer connectors (but having to draw does not indicate) between patterned layer, provide in multiple other devices of pattern conductive level in element, the connection between node and conductor.
Fig. 3 is the schematic diagram of antenna effect discharge circuit, comprises a field-effect transistor, and its grid is couple to semiconductor substrate through an electric capacity.Antenna effect discharge circuit has a terminal (such as the drain electrode of field-effect transistor 50), a grid and another terminal (such as the source electrode of field-effect transistor 50); one terminal is connected to shielded node 55 on device; charge accumulation is suffered to avoid node; grid is such as the grid of field-effect transistor 50 in circuit, and stored charge can pass through another terminal and is discharged on substrate.
In circuit, p channel fet 50 and n channel fet 51 have drain electrode, and it is coupled to node 55 to avoid charging by antenna effect.The source electrode of field-effect transistor 50,51 is connected to substrate 52.The grid of field-effect transistor 50 is connected to electric capacity 65 by a patterned conductor 57 (such as polycrystalline silicon conducting wire), and electric capacity 65 has the first end being connected to conductor 57, and is positioned at substrate 52, or is connected to the second end of substrate 52.The grid of field-effect transistor 51 is connected to electric capacity 66 by patterned conductor 60 (such as polycrystalline silicon conducting wire), and electric capacity 66 has the first end being connected to conductor 60, and is positioned at substrate 52, or is connected to the second end of substrate 52.
P channel fet 50 has a passage in the n-type semiconductor district on substrate, is called passage trap 53 herein.Passage trap 53 bonding conductor 56.Before upper patterning conductor layer (being preferably the superiors' patterning conductor layer) is formed, conductor 56,57 does not connect in device technique.Upper patterning conductor layer comprises conductor 58, and it is by conductor 57,56, the connection between the grid providing passage trap 53 and field-effect transistor 50.In addition, conductor 58 connects voltage supply circuit, and it provides bias voltage VPP.
N channel fet 51 has a passage in the p-type semiconductor district on substrate, is called passage trap 54 herein.Passage trap 54 bonding conductor 61.Before upper patterning conductor layer (being preferably the superiors' patterning conductor layer) is formed, conductor 61,60 does not connect in device technique.Upper patterning conductor layer comprises conductor 62, and it is by conductor 60,61, the connection between the grid providing passage trap 54 and field-effect transistor 51.In addition, conductor 62 connects voltage supply circuit, and it provides bias voltage VNP.
Fig. 4 illustrates substrate and the well structure of the high voltage that can be used in Fig. 3 circuit, P channel and high pressure n channel fet (HV-PMOS and HV-NMOS).In this example, device is formed on p-type substrate 100.P channel fet is formed in n-type semiconductor trap 103, and it corresponds to the passage trap 53 in Fig. 3.N channel fet is formed in p-type semiconductor trap 102, and its mat deep n-trap 101 is separated in substrate 100.P-type semiconductor trap 102 corresponds to the passage trap 54 of Fig. 3.
Fig. 4 illustrates source area, drain region 106,107, grid 105 and the gate insulator 108 of p-type field-effect transistor (HV-PMOS).In addition, N-shaped contact zone 104 is formed in N-shaped trap 103, to provide the body being connected to passage trap.In addition, illustrate source electrode and the drain region 113,114 of N-shaped field-effect transistor (HV-NMOS) in figure, grid 112, with gate insulator 115.In addition, p-type contact district 111 is formed in p-type trap 102, to provide the body being connected to passage trap.In addition, N-shaped contact zone 110 is formed in deep n-trap 101, to provide dark n trap to the connection of bias circuit system, helps the isolation of passage trap 102.For providing the connection of electric capacity and substrate (not illustrating), P type contact zone 117,118 can be arranged on the substrate outside trap 101,103.Shallow trench isolation sti structure (such as 119) can be arranged between doped region as shown in the figure, to promote isolation.
As mentioned with reference to fig. 1, in the DTMOS type antenna effect discharge circuit of prior art, grid is connected in process with passage trap contact (such as 105,104).When this connection will make that positive voltage is applied to drain electrode 107 between charge period, the voltage between grid and passage trap maintains close to zero.In the circuit described by Fig. 3, grid and passage trap contact (such as 105,104) all or or most patterning conductor layer formed time be not connected.Or rather, grid (as 105) is connected to an electric capacity, and passage trap (such as 104,103) is suspension joint.Therefore, even if the voltage on passage trap mat protected node increases and strengthens, because the grid of electric capacity and transistor to trap permittivity causes voltage difference, grid potential is only by the factors vary of grid coupling efficiency.This makes field-effect transistor open sooner when antenna effect is charged, and more effectively discharge unwanted voltage.
Electric capacity 65,66 can use an electric capacity to connect and realize, High voltage NMOS transistor in P type substrate, link together with source electrode and drain electrode, it has the grid formed by patterned conductor, such as, be the phase diagram patterned conductor corresponding with the grid forming field-effect transistor (HV-PMOS or HV-NMOS).Such as, or electric capacity can realize by the single continuous trap of mat one, and it from free of conductors through a dielectric layer, is the gate dielectric of HV-NMOS and the HV-PMOS device for the formation of Fig. 3, does not have aisle spare under its conductor.For establishing high coupling ratio (couplingratio), the conductor area on electric capacity about can be greater than the gate area on corresponding field-effect transistor 50,51.In one embodiment, about 4 times of the area of the about comparable grid of area of the grid on electric capacity, makes gate coupling ratio about 0.8.
Fig. 5 and Fig. 6 illustrates the formation of the lower patterned conductor of the antenna effect discharge circuit of Fig. 3, before it occurs in the connection forming grid and passage trap.The element corresponding with Fig. 3 uses identical label, and repeats no more.
In the state shown in Fig. 5, protected node (such as wordline) can be charged to about-2V in processing step.In the case, in p-channel fet 50, p+ source electrode becomes reverse biased to N-shaped passage trap.Therefore p channel fet 50 keeps closed condition.But the n+ of the n channel fet 51 p-type passage trap that drains becomes forward bias.Electric capacity 66 prevents the gate charges of n-channel fet 51 to the voltage identical with p-type passage trap 54.Therefore, the voltage approximately identical with protected node is rapidly charged when protected node reaches the suspension joint p-type passage trap mat forward junction about bearing 2V, n channel fet.If electric capacity 66 has enough permittivity, the gate coupling ratio that one relatively large can be provided, mat capacitance partial pressure (VWL* (1-GCR)) is drifted to the value (such as >-1V) being greater than negative 1V by grid voltage, close to the no-voltage of p-type substrate 52.Maintenance grid like this is to the positive bias Vgb of passage trap, and its size is less than about 1V in detail in this figure, is enough to open in processing step in n channel fet, protected node is not needed to the repid discharge of charging.
In the state shown in Fig. 6, protected node (such as wordline) can be charged to about+2V in processing step.In the case, in m channel fet 51, n+ source electrode becomes reverse biased to p-type passage trap.Therefore n channel fet 50 keeps closing.But the p+ of the p channel fet 50 N-shaped passage trap that drains becomes forward bias.Electric capacity 65 prevents the gate charges of p channel fet 50 to the voltage identical with N-shaped passage trap 53.Therefore, the suspension joint N-shaped passage trap mat forward junction reaching about positive 2V, p channel fet when protected node is rapidly charged the voltage approximately identical with protected node.If electric capacity 65 has enough permittivity, the gate coupling ratio that one relatively large can be provided, mat capacitance partial pressure (VWL* (1-GCR)) is drifted to the value (such as < 1V) being less than 1V by grid voltage, close to the no-voltage of p-type substrate 52.Maintenance grid like this is to the back bias voltage Vgb of passage trap, and its size is less than about 1V in detail in this figure, is enough to open in processing step in p channel fet, protected node is not needed to the repid discharge of charging.
In the circuit of Fig. 3, upper patterning conductor layer can be the patterning conductor layer of the top after making, and grid is connected with passage trap.May be there is the technique of charging in some, such as passivation or cover other layers in upper patterned conductor, and after connection grid and passage trap, the protection provided by antenna effect discharge circuit may be poor.
Fig. 7 illustrates the embodiment of another kind of antenna effect discharge circuit, can maintain protection after forming the patterning conductor layer in order to connect grid and passage trap.When appropriate, circuit element uses the mark identical with Fig. 3.In this example, between electric capacity and voltage supply circuit, add switch, until device receive can the operating voltage of closing switch, it allows a step to keep the grid of field-effect transistor 50,51 to be separated from passage trap 53,54.In this approach, antenna effect can be prevented in whole technique.
In this example, switch for p channel fet 50 is high voltage n channel fet 70 (HV-NMOS such as shown in Fig. 4), it has first end (source electrode or drain electrode), grid is connected by the first connector 70-1 and conductor 57, and one second end (source electrode or drain electrode), it connects supply voltage circuit by the second connector 70-2.One or two of connector 70-1,70-2 can the top (being preferably the superiors) of patterning conductor layer of forming apparatus.The grid of n channel fet 70 is connected to voltage supply circuit, to accept a bias voltage of such as VPP during running, with closing switch.
In this example, switch for n channel fet 51 is high voltage p channel fet 71 (HV-PMOS such as shown in Fig. 4), it has first end (source electrode or drain electrode), grid is connected by the first connector 71-1 and conductor 60, and one second end (source electrode or drain electrode), it connects supply voltage circuit by the second connector 71-2.One or two of connector 71-1,71-2 can the top (being preferably the superiors) of patterning conductor layer of forming apparatus.P channel fet 701 grid is connected to voltage supply circuit, to accept a bias voltage of such as VNP during running, with closing switch.
In this way, until switching transistor 70,71 is unlocked with before closing switch, antenna effect discharge circuit is still effective.
Fig. 8 is the layout of an antenna effect discharge circuit, comprises the electric capacity of the grid being coupled to this voltage field effect transistor.In this example, layout is formed on a p-type substrate 100.One N-shaped passage trap 103 is formed on the substrate 100.In addition, formed on a deep n-trap 101, there is a p-type passage trap 102 inside.Substrate contacts (as 104,110,111 of Fig. 4) can arrange, to provide suitable bias voltage during operating around trap.In addition, guard ring (not illustrating) uses the conductor of such as polysilicon layer to be formed around trap.Deep n-trap, p-type substrate and guard ring link together by contact, and ground connection during operation.
One group of high voltage, n channel fet are formed in p-type trap 102.In this example, in trap 102, there are three transistors.The first transistor comprises drain electrode end 202 and source terminal 206.Transistor seconds comprises drain electrode end 203 and source terminal 207.Third transistor comprises drain electrode end 204 and source terminal 208.Drain electrode end 202,203 and 204 is connected the patterned conductor 210,211,212 in lower patterning conductor layer respectively, such as the first metal layer, or with the inter-layer connectors that lattice represents in Yu Youtu.Source terminal 206,207,208 connection layout patterned conductor 214,215,216, it is connected to the node corresponded to by circuit protection.For example, patterned conductor 214 can be the first metal layer conductor, is connected to the shared source electrode line 231 in memory construction, as shown in Figure 2.Patterned conductor 215 can be the second metal level conductor, and the string be connected in memory construction selects line 232, as shown in Figure 2.Patterned conductor 216 can be the first metal layer conductor, is connected to one or more wordline 233, as shown in Figure 2.
The grid of three transistors is formed by single patterned polysilicon wire 200, and it extends towards the region outside passage trap 102, and passage trap 102 is positioned at second, on N-shaped capacitance terminal diffusion 201, N-shaped capacitance terminal diffusion 201 act as the second end of electric capacity.The area of polycrystalline silicon conducting wire 200 on capacitance terminal diffusion 201 as the first end of electric capacity, and should be greater than the gate area of transistor in p-type trap 102, to set up high gate coupling ratio as mentioned above.
Patterned conductor 210,211,212, as by the arrows in figure, is connected to p-type substrate 100.
Patterned conductor 258 mat inter-layer connectors is connected to grid polycrystalline silicon wire 200.In the same manner, patterned conductor 250 mat inter-layer connectors interface channel trap 102.Patterned conductor 258 and 250 can be formed in the below of the patterning conductor layer on device, such as, in the first metal layer.Conductor 258 and 250 is connected to the conductor 260 of patterning conductor layer, is labeled as ML4 herein, represents 4 road smithcrafts.
In addition, high voltage, p channel fet are formed in N-shaped passage trap 103.In this example, in trap 103, there are three transistors.The first transistor comprises drain electrode end 306 and source terminal 302.Transistor seconds comprises drain electrode end 307 and source terminal 303.Third transistor comprises a drain electrode end 308 and source terminal 304.Drain electrode end 306,307 and 308 is connected the patterned conductor 314,315,316 in lower patterning conductor layer respectively, such as the first metal layer, or inter-layer connectors.Source terminal 302,303,304 connection layout patterned conductor 310,311,312, it is connected to the node corresponded to by circuit protection.Such as, patterned conductor 310 can Connection Sharing source electrode line 231, and patterned conductor 311 can connect string and select line 232.Patterned conductor 312 can be connected to one or more wordline 233.
The grid of three transistors is formed by single patterned polysilicon wire 300, and it extends towards the region outside passage trap 103, and passage trap 103 is positioned at second, on N-shaped capacitance terminal diffusion 301, it act as the second end of electric capacity.The area of polycrystalline silicon conducting wire 300 on capacitance terminal diffusion 301 as the first end of electric capacity, and should be greater than the gate area of transistor in p-type trap 103, to set up high gate coupling ratio as mentioned above.
Patterned conductor 314,315,316 is connected to p-type substrate 100 as shown by the arrow.
Patterned conductor 358 mat inter-layer connectors is connected to polycrystalline silicon conducting wire 300.Similarly, patterned conductor 350 mat interlayer connector is connected to passage trap 103.Patterned conductor 358,350 can be formed in one of bottom of device patterning conductor layer, such as, at the first metal layer.Conductor 358 and 350 is connected to the conductor 360 of top patterning conductor layer, is labeled as ML4 herein, represents 4 road smithcrafts.
Fig. 9 is the simplification calcspar of integrated circuit 525, comprises memory array 510, and it comprises antenna discharge circuit 527.In some embodiments, array 510 is three-dimensional storages, and comprises multi-level unit.Multiple wordline in row decoder 511 couples memory array 510, string select line and ground connection to select line (512).Level/the column decoder of block 513 is coupled to one group of page buffer 516, in this example by bus 517, and via global bit line and source electrode line 514.Address is provided to bus 515, level/column decoder (block 513) and row decoder (block 511).Data are supplied via the data input line (such as comprising input/output terminal) of other Circuits System 524 on integrated circuit, the processor of such as general service, the application circuit of special purpose, or system single chip (system-on-a-chip) function that binding modules is supported to provide array 510.Data via data input line 523, input/output terminal or other the data sources inner or outside from integrated circuit 525.
Controller is state machine 519 in this example, provides signal to control bias voltage and arranges the generation of supply voltage, via the voltage supply circuit in block 518 or provide multiple operation, such as, reads, erasing, programming.Controller can use dedicated logic circuit known in the art.In other embodiments, controller comprises general service processor, and general service processor can be performed in same integrated circuit and perform computer program with the operation of control device.In a further embodiment, the execution of controller can utilize the combination of special purpose logic circuitry and general service processor.
As shown in the circuit of Fig. 3 and Fig. 7, antenna effect discharge circuit 527 has the electric capacity connecting grid, and it couples the conductor of memory array in example, is represented by wire 526.Wire 526 can be wordline, bit line, string select line, ground connection selects line, or other conducting wires that can charge in process.The uppermost patterning conductor layer 528 of antenna effect discharge circuit 527 mat device, connect voltage supply circuit 518, being labeled as ML4 at this is represent 4 metal devices.Voltage supply circuit 518 comprises circuit for providing voltage, the charge pump of such as positive and negative voltage, horizontal switches (levelshifters) and voltage regulator (voltageregulators).In a representational three dimensional NAND device, the charge pump of positive voltage and negative voltage can produce the operating voltage up to 30V and-10V.Certainly, the positive operating voltage of peak and negative operating voltage are denoted as VPP and VNP herein, need specific device.
The antenna effect discharge circuit number provided in one specific integrated circuit according to process environments, available space, and the demand of product and determining.In some products, may be that every wordline comprises an antenna effect discharge circuit.In the product of other examples, multiple wordline can share a protective device.On device, other nodes of integrated circuit (IC) system also can be protected.
Figure 10 is the simplified flow chart of technique, comprises plasma effect discharge circuit as described herein.The method is included on substrate (600) and forms integrated circuit.Further, the method is included on substrate and forms antenna effect discharge circuit (601), and uses grid and the substrate (602) of electric capacity coupling antenna effect discharge circuit.Technique comprises provides voltage supply circuit on integrated circuit, or couples integrated circuit (603).Finally, use the patterned conductive layer on upper strata (being preferably topmost) to connect grid and voltage supply circuit (604) when technique.
Although do not illustrate in Figure 10, this technique can be included between grid and voltage supply circuit and provide a switch, as shown in Figure 7.Switch can be configured to grid running during close close, and mat switch connect voltage supply circuit.Switch can use with high-voltage field effect transistor, such as HV-NMOS or HV-PMOS device, and it has the grid being connected to voltage supply circuit.
The method wherein forming antenna effect discharge circuit comprises formation one N-shaped passage trap and a p-type passage trap on substrate, and the diffusion of one first capacitance terminal and one second capacitance terminal are spread on substrate.One p channel fet is formed in N-shaped passage trap, and it has a grid, one source pole and a drain electrode, and source electrode and drain electrode are arranged in N-shaped passage trap.One n channel fet is formed in p-type passage trap, and it has a grid, one source pole and a drain electrode, and source electrode and drain electrode are arranged in p-type passage trap.In addition, form one first electric capacity, have a first end and one second end, first end is positioned at or is connected to the first capacitance terminal diffusion, and the second end couples the grid of p channel fet.Form one second electric capacity, have a first end and one second end, first end is positioned at or is connected to the first capacitance terminal diffusion, and the second end couples the grid of n channel fet.This technique comprises one of them and the protected node that connect the source electrode of p channel fet and drain electrode with a patterned conductor, another connection substrate wherein of source electrode and drain electrode.In addition, this technique comprises one of them and the protected node that connect the source electrode of n channel fet and drain electrode with a patterned conductor, another connection substrate wherein of source electrode and drain electrode.
In this example, there is provided the step of voltage supply circuit to comprise and provide a voltage supply circuit, it has one first voltage and exports, and can provide VPP, and connected the grid of p channel fet by the first patterned conductor in upper strata, to close p channel fet during operating; And there is the first voltage output, can VNP be provided, and connect the grid of n channel fet by the second patterned conductor in upper strata, to close n channel fet during operating.
There is provided the step of a switch can be included in device and form one first switch, it has a first end and one second end, and first end connects the first patterned conductor in upper strata, and the second end connects voltage supply circuit, configures the first switch and closes during operating; And second switch is formed on device, it has a first end and one second end, and first end connects the first patterned conductor in this upper strata, and the second end connects voltage supply circuit, and configuration second switch is closed during operating.
A kind of new antenna protective circuit and manufacture method thereof are described.As shown in Figure 3, Figure 5 and Figure 6, the grid of n passage and p channel fet after the first metal layer ML1 respectively by suspension joint, instead of as 1 figure prior art circuits in connect.
Grid is connected to large-scale capacitor, and is coupled to P type substrate.Between antenna charge period, grid because of electric capacity close to p-type substrate potential.This makes the easier conducting of field-effect transistor.Positive charge will be released by p channel fet, and negative electrical charge will be released by n channel fet.Experimental data shows, and the p channel fet used in new protective circuit and n channel fet can be less than the plus or minus value effect of 2V, and then provides the protection of very excellent technique internal antenna for new equipment.In addition, prove that larger capacity area and gate area Pen Association cause higher discharging current.
Higher grid can make grid closer to substrate potential to substrate coupling ratio (gatetosubstratecouplingratio, GCR), provides lower conducting voltage (< 2V) and more protects.
In the last patterning conductor layer of such as the top metal level, antenna protective circuit connects VPP and the VNP end of voltage supply circuit, to make them close in operation, and can not affect the running of device.
In order to prevent any possible charging in passivating process or other high layer process, buffer transistor switch can be added between protective circuit grid and voltage supply circuit.
New antenna protective circuit can be applicable to common flash array, other storage arrangements, logical circuit, and the integrated circuit (IC) apparatus of other types.
Extremely low protection voltage (< +/-2V) apply advanced storage arrangement; the ReRAM of such as programmable resistance or phase change PCRAM, the low-voltage of charging between its technique (< 3V) may cause the deterioration of equipment effectiveness.
Charge effects in technique crosses the initial Vt distribution of the deteriorated 3DNAND flash memory integrated circuit of meeting.Use capacitive coupling Floating gate (capacitivecoupledfloatinggate; CCFG) example of the antenna protective circuit of cmos circuit as previously mentioned, can be applicable to the wordline (WL) of memory integrated circuit and select the decoder of transistor (SSL).The experimental result display of circuit, the extremely low conducting voltage (< +/-2V) of electric discharge, provides the protection of storage arrangement.Utilize this technology, fully-integrated three dimensional NAND flash device, in the excellent initial threshold voltage Vt distribution of memory array display, does not affect by charge effects.
In addition, string selects line SSL transistor threshold voltage Vt distribution (variation) can have an impact to the bias voltage of minimum Vdd.Along with the progress of SSLVt distribution, antenna protective circuit can be used as Fig. 3, Fig. 5 and Fig. 6, which demonstrate Vdd and successful program window that 3DVGNAND flash memory can support to be less than 1.6V.
Antenna protective circuit described herein can be applicable to wordline WL, string selects line SSL/ ground connection to select line GSL decoder.The experimental result of three dimensional NAND quick flashing integrated circuit confirms.
Fully-integrated fractionation page 3DVGNAND flash memory is at S.H.Chen, H.T.Lue, etal. " Ahighlyscalable8-layerverticalgate3DNANDwithsplit-pahebi tlinelayoutandefficientbinary-sumMilC (Minimalincrementallayercost) staircasecontacts ", IEDMpp.21-24,2012, be described in detail, in this file, more have studied periphery CMOS device.
The protective circuit of such as Fig. 3, Fig. 5 and Fig. 6 is configured in device under test.
Figure 11 illustrates in the device of CCFGNMOS protective circuit; the curve of drain current and drain voltage (IdVd); and the curve of drain voltage and substrate current Ib (IbVd); it is the state be in as shown in Figure 5; when grid and PWI suspension joint, p substrate, source electrode and DNW ground connection.Its not forward bias electric discharge, but be easy in opening, to negative voltage discharge lower than-2V.When-7V, can be observed obvious substrate current (Ib).This is because parasitic bipolar conducting is opened through the parasitic BJT of N+-PW1-DNW.
Experimental data shown in Figure 12 is included in the device of CCFGPMOS protective circuit; the curve of drain current and drain voltage (IdVd); and the curve of drain voltage and substrate current Ib (IbVd), it is the state be in as shown in Figure 5, and its grid and N trap are suspension joint.It shows low conducting voltage (<+2V).Do not observe parasitic bipolar conduction mode, therefore do not observe substrate current yet.Conducting voltage lower than 2V, provides excellent protection when positive bias under low-voltage.Substrate current (Ib) is very little, shows without parasitic BJT pattern.
Experimental data shown in Figure 13 comprise complete CCFGCMOS protective circuit discharging current (when grid and trap floating), similar Fig. 5 and Fig. 6.Its display is lower than the extremely low conducting voltage of +/-2V, and the ideal of generator is protected.Capacity ratio higher on FG area provides higher On current.It should be noted that NMOS and PMOS can be high voltage (HV) device, to maintain the high operating voltage of WL, SSL or GSL.
Figure 14 is the image of the TEM profile of measurement 8 layers of 3DVG device.Figure 15 illustrates in the multilayer of device under test, the initial threshold voltage distribution of memory cell.Due to protective circuit, as the initial condition in Figure 15, there is excellence and distribute close to normal Vt.In accordance with expectation, because the technique between accumulation layer and dimensional discrepancy, some special tolerances between PL1 to PL88 layer, is observed.
Figure 16 illustrates SSLVt distribution.The built-in sigma of SSL can be less than 250mV.Through the fine setting of some mat soft programming and checking, sigma can reduce to nearly 100mV further.
The impact of SSL distribution is illustrated in Figure 17 and Figure 18.Figure 17 is the schematic diagram that a simplification NAND goes here and there.During supercharging programming, Vdd is applied in BL bias voltage and SSL grid bias.Figure 18 illustrates the increase along with σ (sigma), the distribution map (Vt scope) of 3 SSL threshold voltages.The lower boundary of Vt scope should higher than 0.4V, to ensure enough to penetrate immunity, to maintain from supercharging.On the other hand, the minimum Vdd application on the higher boundary limitation SSL of Vt scope and BL.Stricter SSL distribution (lower σ) can reduce VDD.
The strict Vt distribution of SSL has material impact to minimizing Vdd.When Figure 19 illustrates and tests for chessboard window of programming, the low and threshold state of device under test, SSLVt distribution that its display improves, tested 3DVGNAND quick flashing can operate at minimum Vdd=1.6V.Low Vdd contributes to minimizing power consumption.
Figure 20 is the circuit diagram example of the antenna protective circuit being applied to CMOS design of encoder.A circuit protected by antenna effect discharge circuit, and it is a part for CMOS decoder, and comprise a p channel fet 772 and a n channel fet 771, have the drain electrode being couple to node 755, node is connected to wordline, and decoded device drives.According to the design of decoder, the grid of transistor 771,772 is connected to decoded signal.N channel fet 771 is formed in P type trap 773.P channel fet 772 is formed in N-shaped trap 774.
In sum, although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.