Background technology
Due to becoming more and more important of various Portable (Portable) electronic products such as communication, network and computer and the compact trend of peripheral product thereof, and these electronic products are towards multi-functional and high performance future development, the then continuous processing procedure evolution higher towards long-pending bodyization on manufacture of semiconductor, and highdensity assembling structure is the target that dealer pursues.Therefore, semiconductor and encapsulation manufacturer start the development of semi-conductor packaging to turn to three-dimensional packaging technology, to realize the high density structure assembling system can supporting the better required by electronic product of these more frivolous usefulness further.
Three-dimensional packaging technology and so-called 3D integrated circuit (3D IC) are integrated in single integrated circuit by various mode multiple layer wafer or circuit substrate with active member.Specifically, multiple wafer is arranged in single integrated circuit in three-dimensional or three-dimensional structure dress mode by 3D integrated circuit technology jointly.Therefore, in 3D integrated circuit technology, need highdensity electrical interconnects technology, to arrange electrical contact in the active surface of wafer and/or the back side, to provide three-dimensional stacking and/or highdensity encapsulation.
Tool silicon perforation (Through silicon via, the technology of intermediate plate (interposer) TSV) is at present in order to realize one of key technology of 3D integrated circuit, by being arranged in wafer or substrate as the silicon perforation that vertical electrical connects, stacking more multi-wafer on given area, thus increase stacking density.And can to provide by silicon perforated design and more effectively integrate, such as can integrate different processing procedure or reduce transmission delay, simultaneously more because there is shorter interconnection length, and then reduce power consumption, enhanced performance and increase transmitting bandwidth.Therefore, silicon puncturing technique makes the technology of wafer stacking composite construction to stride forward towards the trend of low-power, high density and micro processing procedure further.
As shown in Figure 1A to Fig. 1 F, it is the generalized section of the method for making of existing semiconductor structure 1.
As shown in Figure 1A, one intermediate plate 10 is provided, it has relative put brilliant side 10a and dorsal part 13 and is multiplely communicated with the conductive through holes 100 that this puts brilliant side 10a, and this puts circuit rerouting structure (the Redistribution layer brilliant side 10a having and is electrically connected this conductive through holes 100, RDL) 11, and to put on brilliant side 10a by binder course 120 in conjunction with a glass plate 12 in this.
As shown in Figure 1B, grind this dorsal part 13, form relatively that this puts the intermediary side 10b of brilliant side 10a with this intermediate plate 10 of thinning, and make this conductive through holes 100 be communicated with this intermediary side 10b.
As shown in Figure 1 C, formation exposes the insulating barrier 14 of this conductive through holes 100 on this intermediary side 10b, and form projection underlying metal layer (Under Bump Metallurgy, UBM) 15 on the exposed junction of this conductive through holes 100, make this projection underlying metal layer 15 be electrically connected this conductive through holes 100.
As shown in figure ip, on those projection underlying metal layer 15 in conjunction with multiple as after the conducting element 16 of soldered ball, then with those conducting elements 16 coated of the glue material 17 on another glass plate 12 '.
As referring to figure 1e, remove this glass plate 12 and binder course 120, then carry out cutting single processing procedure.
As shown in fig. 1f, cover crystalline substance in conjunction with semiconductor element 18 in this circuit rerouting structure 11 by multiple conductive projection 180, and remove this another glass plate 12 ' and glue material 17, to make this semiconductor structure 1.
In successive process, the intermediary side 10b of this intermediate plate 10 can be connected to a base plate for packaging 9 by those conducting elements 16 by this semiconductor structure 1.
But, in the method for making of existing semiconductor structure 1, this intermediate plate 10 is used to realize 3D integrated circuit, and the processing procedure on this intermediate plate 10 need utilize and puts brilliant side 10a and dorsal part 13 carries out double-sided circuit conducting design (as this conducting element 16, making such as semiconductor element 18 grade) and carry the operations such as the intermediate plate 10 after thinning, so carry out those operations by temporary joint (Temporary Bond) technology, namely utilize harder, can resistant to elevated temperatures material (as this glass plate 12, 12 ' or Silicon Wafer) be used as bearing part, cause and need repeatedly to carry out combining/remove this glass plate 12 in processing procedure, the step of 12 ', and this glass plate 12, 12 ' can not reuse, cost of manufacture is caused to be difficult to reduce.
Therefore, how to solve the various shortcoming of above-mentioned prior art, the real technical problem being current all circles and desiring most ardently solution.
Summary of the invention
For solving the variety of problems of above-mentioned prior art, main purpose of the present invention, for disclosing a kind of semiconductor structure and method for making thereof, can simplify processing procedure and reduce cost of manufacture.
Semiconductor structure of the present invention, comprising: the first semiconductor substrate, and it has the first relative side and the second side and multiple first conductive through holes being communicated with this first side and the second side; Second semiconductor substrate, it has the 3rd relative side and the 4th side and multiple second conductive through holes being communicated with the 3rd side and the 4th side, and the first side of this first semiconductor substrate is bonded to the 3rd side of this second semiconductor substrate, this first conductive through holes and this second conductive through holes are electrically conducted mutually; And at least one electronic component, it is located at the second side of this first semiconductor substrate and is electrically connected this first conductive through holes.
The present invention provides again a kind of method for making of semiconductor structure, it comprises: provide one first semiconductor substrate and one second semiconductor substrate, this first semiconductor substrate has the first relative side and the second side and is positioned at wherein and expose to multiple first conductive through holes of this first side, and this second semiconductor substrate has the 3rd relative side and the 4th side and is positioned at wherein and expose to multiple second conductive through holes of the 3rd side; In conjunction with the first side of this first semiconductor substrate and the 3rd side of this second semiconductor substrate, this first conductive through holes and this second conductive through holes are electrically conducted mutually; And arrange at least one electronic component on the second side of this first semiconductor substrate, and this electronic component is electrically connected this this first conductive through holes.
In aforesaid method for making, be also included in after this electronic component is set, carry out cutting processing procedure.
In aforesaid semiconductor structure and method for making thereof, the first side of this first semiconductor substrate has oxide layer, with the 3rd side in conjunction with this second semiconductor substrate.Or the 3rd side of this second semiconductor substrate has oxide layer, with the first side in conjunction with this first semiconductor substrate.Or the first side of this first semiconductor substrate has the first oxide layer, and the 3rd side of this second semiconductor substrate has the second oxide layer, makes this first oxide layer in conjunction with this second oxide layer, with in conjunction with this first and second semiconductor substrate.
In aforesaid semiconductor structure and method for making thereof, the first side of this first semiconductor substrate has circuit redistribution layer, with in conjunction with the 3rd side of this second semiconductor substrate and this second conductive through holes.Such as, the 3rd side of this second semiconductor substrate has oxide layer, with in conjunction with this circuit redistribution layer.
In aforesaid semiconductor structure and method for making thereof, this electronic component is semiconductor element.
In aforesaid semiconductor structure and method for making thereof, also comprise and form encapsulated layer with this electronic component coated on the second side of this first semiconductor substrate, and this encapsulated layer exposes the part surface of this electronic component.Such as, before this encapsulated layer of formation, form primer between second side and this electronic component of this first semiconductor substrate.
In aforesaid semiconductor structure and method for making thereof, also comprise and form multiple conducting element on the 4th side of this second semiconductor substrate, and those conducting elements are electrically connected this second conductive through holes.
In aforesaid semiconductor structure and method for making thereof, also be included in before this electronic component is set, form first line rerouting structure on the second side of this first semiconductor substrate, and this first line rerouting structure is electrically connected this first conductive through holes, this electronic component is located in this first line rerouting structure and is electrically connected this first line rerouting structure.
In addition, in aforesaid semiconductor structure and method for making thereof, also comprise formation second circuit rerouting structure on the 4th side of this second semiconductor substrate, and this second circuit rerouting structure is electrically connected this second conductive through holes.
As from the foregoing, semiconductor structure of the present invention and method for making thereof, mainly by the second semiconductor substrate simultaneously as bearing part and base plate for packaging, thus without the need to removing this second semiconductor substrate, and without the need to setting up as existing base plate for packaging in successive process, so compared to prior art, method for making of the present invention does not need the processing procedure repeatedly carrying out combining/removing bearing part, thus can simplify processing procedure, and reduce cost of manufacture simultaneously.
In addition, this first and second semiconductor substrate can utilize oxide layer to combine and utilize this first and second conductive through holes to dock, and merges docking, and promote associativity to be formed.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only in order to coordinate specification to disclose, for understanding and the reading of those skilled in the art, and be not used to limit the enforceable qualifications of the present invention, so the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, quote in this specification as " on ", " first ", " second " and " one " etc. term, be also only be convenient to describe understand, and be not used to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 F is the generalized section of the method for making of the first embodiment of semiconductor structure 2 of the present invention.
As shown in Figure 2 A, one first semiconductor substrate 20 and one second semiconductor substrate 22 is provided, this first semiconductor substrate 20 has the first relative side 20a and the second side 20b and is positioned at wherein and expose to multiple first conductive through holes 200 of this first side 20a, and this second semiconductor substrate 22 has the 3rd relative side 22a and the 4th side 22b and is positioned at wherein and expose to multiple second conductive through holes 220 of the 3rd side 22a.
In the present embodiment, this first semiconductor substrate 20 is silicon intermediate plate, and this second semiconductor substrate 22 is glass plate.
In addition, have as silica (SiO around the first side 20a of this first semiconductor substrate 20 and this first conductive through holes 2002) one first oxide layer 201, have as silica (SiO around the 3rd side 22a of this second semiconductor substrate 22 and this second conductive through holes 2202) one second oxide layer 221.Particularly, the thickness of this first oxide layer 201 and the thickness of this second oxide layer 221 are about 1.0um.
Again, as shown in Fig. 2 A ', in the first side 20a(of this first semiconductor substrate 20 or this first oxide layer 201) also can have a circuit redistribution layer 202.Particularly, this circuit redistribution layer 202 has one and is positioned in this first side 20a(or this first oxide layer 201) insulation division 202a be positioned at circuit 202b on this first conductive through holes 200, wherein, this insulation division 202a is oxidation material, and this first conductive through holes 200 is electrically connected this circuit 202b.
In addition, the processing procedure of described conductive through holes be first etching semiconductor substrate to form perforation, then form oxide layer in this perforation, form conduction material (as copper) afterwards in this perforation, to make this conductive through holes.
As shown in Figure 2 B, the processing procedure of hookup 2A, in conjunction with the first side 20a of this first semiconductor substrate 20 and the 3rd side 22a of this second semiconductor substrate 22, makes this first conductive through holes 200 mutually electrically conduct with this second conductive through holes 220.
In the present embodiment, this first semiconductor substrate 20 is with second oxide layer 221 of this first oxide layer 201 in conjunction with this second semiconductor substrate 22.Particularly, this first oxide layer 201 is temperature 800 to 1000 DEG C with the combination process condition of this second oxide layer 221, and in conjunction with pressure 5 to 10KN under 1 to 2MPa, vacuum pressure is less than 4 to 10 Bristols (Torr).
In addition, the end face of this first conductive through holes 200 and the end face of this second conductive through holes 220 are direct correspondingly to contact.
As shown in Figure 2 C, form a first line rerouting structure (RDL) 21 in the second side 20b of this first semiconductor substrate 20, and this first line rerouting structure 21 is electrically connected this first conductive through holes 200.
In the present embodiment, this first line rerouting structure 21 have at least one dielectric layer 210, in conjunction with this dielectric layer 210 line layer 211 and be arranged in the conductive blind hole 212 of this dielectric layer 210, and the line layer 211 of this first line rerouting structure 21 is electrically connected this first conductive through holes 200 by this conductive blind hole 212.
In addition, before this first line rerouting structure 21 of making, first with the second side 20b of this first semiconductor substrate 20 of lapping mode thinning, again with reactive ion etch (Reactive IonEtch, RIE) the second side 20b of this first semiconductor substrate 20 of method thinning, make this first conductive through holes 200 protrude this second side 20b, then, form ㄧ as silica or silicon nitride (SiNx) passivation layer 203 on the second side 20b of this first semiconductor substrate 20, and make this passivation layer 203 surface of end face of this first conductive through holes 200, to expose the end face of this first conductive through holes 200, just form this first line rerouting structure 21 afterwards on this passivation layer 203.
Again, in other embodiment, this passivation layer 203 can not be formed on the second side 20b of this first semiconductor substrate 20, so this second side of the end face of this first conductive through holes 200 20b is surperficial.
As shown in Figure 2 D, multiple electronic component 23 is set in this first line rerouting structure 21, and this electronic component 23 is electrically connected the line layer 211 of this first line rerouting structure 21.Then, ㄧ encapsulated layer 24 is formed between this first line rerouting structure 21 and this electronic component 23 and those electronic components 23 coated.
In the present embodiment, this electronic component 23 is semiconductor element, so this electronic component 23 has relative acting surface 23a and non-active face 23b, and its acting surface 23a is to cover crystal type to be electrically connected this first line rerouting structure 21 line layer 211 by multiple conductive projection 230.
In addition, the formation of this encapsulated layer 24 is packing colloid, the dry film (dry film) or other isolation material etc. of mold pressing processing procedure.Such as, if this encapsulated layer 24 is packing colloid, it first forms the colloid that thickness is 300 to 500um, then removes the thick colloid of 300um at the most, makes the thickness of this encapsulated layer 24 be 100 to 200um.
Again, also first can form primer 27 with those conductive projections 230 coated between this first line rerouting structure 21 and acting surface 23a of this electronic component 23, then form this encapsulated layer 24 ' with those electronic components 23 coated and this primer 27, as Fig. 2 F " shown in.
In addition, this encapsulated layer 24 does not expose the non-active face 23b of this electronic component 23; In other embodiment, as Fig. 2 F " shown in, this encapsulated layer 24 ' can expose the non-active face 23b of this electronic component 23.
As shown in Figure 2 E, the 4th side 22b of this second semiconductor substrate 22 of thinning, and end face the 4th side 22b surface making this second conductive through holes 220, to expose this second conductive through holes 220 in the 4th side 22b on the surface.
In the present embodiment, with the 4th side 22b of this second semiconductor substrate 22 of lapping mode thinning.
As shown in Figure 2 F, cutting processing procedure is carried out along the cutting path S shown in Fig. 2 E, to obtain multiple semiconductor structure 2, and form multiple conducting element 25 as soldered ball on second conductive through holes 220 of the 4th side 22b of this second semiconductor substrate 22, and those conducting elements 25 are electrically connected this second conductive through holes 220.
In the present embodiment, this second semiconductor substrate 22 can simultaneously as bearing part and base plate for packaging, so without the need to removing this second semiconductor substrate 22.
In another embodiment, also can first in conjunction with multiple conducting element 25 as soldered ball on this second conductive through holes 220, then carry out cutting processing procedure.
Method for making of the present invention by the second semiconductor substrate 22 as bearing part, and also as base plate for packaging, thus without the need to removing this second semiconductor substrate 22, also without the need to setting up as existing base plate for packaging, so compared to prior art, method for making of the present invention does not need the processing procedure repeatedly carrying out combining/removing bearing part, thus can significantly reduce fabrication steps and material cost.
In addition, utilize this first oxide layer 201 in conjunction with this second oxide layer 221, and the end face of this first conductive through holes 200 docks mutually with the end face of this second conductive through holes 220, make this first and second semiconductor substrate 20,22 form fusion docking (Fusion Bonding), to promote the associativity of this first and second semiconductor substrate 20,22.
Again, if the processing procedure of hookup 2A ', the semiconductor structure 2 ' as shown in Fig. 2 F ' will be obtained, namely this first semiconductor substrate 20 is by second oxide layer 221 of this insulation division 202a in conjunction with this second semiconductor substrate 22, and this circuit 202b docks mutually with the end face of this second conductive through holes 220, cause this first and second semiconductor substrate 20,22 to be formed and merge docking, to promote the associativity of this first and second semiconductor substrate 20,22.
In addition, in other embodiment, as Fig. 2 F " shown in, also can form the second circuit rerouting structure 26 on the 4th side 22b of this second semiconductor substrate 22, and this second circuit rerouting structure 26 is electrically connected this second conductive through holes 220.
Particularly, this the second circuit rerouting structure 26 have at least one dielectric layer 260, in conjunction with this dielectric layer 260 line layer 261 and be arranged in the conductive blind hole 262 of this dielectric layer 260, make this second conductive through holes 220 be electrically connected conductive blind hole 262 and the line layer 261 of this second circuit rerouting structure 26.
Fig. 3 and Fig. 3 ' is the generalized section of the different embodiments of the second embodiment of semiconductor structure 3,3 ' of the present invention.The difference of the present embodiment and the first embodiment is not form this first line rerouting structure 21, and other processing procedure is roughly the same.
As shown in Figure 3, the second side 20b of this first semiconductor substrate 20 is located at by this electronic component 23, and those conductive projections 230 are directly bonded to the end face of this first conductive through holes 200, is electrically connected this first conductive through holes 200 to make this electronic component 23.
As shown in Fig. 3 ', also in the step of Fig. 2 C, change formation second circuit rerouting structure 26 on the 4th side 22b of this second semiconductor substrate 22, and this second circuit rerouting structure 26 can be electrically connected this second conductive through holes 220.Afterwards, then this electronic component 23 is located at the second side 20b of this first semiconductor substrate 20, and those conductive projections 230 are directly bonded to the end face of this first conductive through holes 200, are electrically connected this first conductive through holes 200 to make this electronic component 23.
The present invention also provides a kind of semiconductor structure 2,2 ', 2 ", 3,3 ', comprising: the first mutually stacking semiconductor substrate 20 and the second semiconductor substrate 22 and at least one electronic component 23 be located on this first semiconductor substrate 20.
The first described semiconductor substrate 20 has the first relative side 20a and the second side 20b and multiple first conductive through holes 200 being communicated with this first side 20a and the second side 20b.
The second described semiconductor substrate 22 has the 3rd relative side 22a and the 4th side 22b and multiple second conductive through holes 220 being communicated with the 3rd side 22a and the 4th side 22b, and the first side 20a of this first semiconductor substrate 20 is bonded to the 3rd side 22a of this second semiconductor substrate 22, this first conductive through holes 200 is electrically conducted mutually with this second conductive through holes 220.
In an embodiment, the first side 20a of this first semiconductor substrate 20 has the first oxide layer 201, with the 3rd side 22a in conjunction with this second semiconductor substrate 22.
In an embodiment, the 3rd side 22a of this second semiconductor substrate 22 has the second oxide layer 221, with the first side 20a in conjunction with this first semiconductor substrate 20.
In an embodiment, first side 20a of this first semiconductor substrate 20 has the first oxide layer 201, and the 3rd side 22a of this second semiconductor substrate 22 has the second oxide layer 221, make this first oxide layer 201 in conjunction with this second oxide layer 221, with in conjunction with this first and second semiconductor substrate 20,22.
In an embodiment, the first side 20a of this first semiconductor substrate 20 has a circuit redistribution layer 202, with in conjunction with the 3rd side 22a of this second semiconductor substrate 22 and this second conductive through holes 220.Preferably, the 3rd side 22a of this second semiconductor substrate 22 has the second oxide layer 221, with in conjunction with this circuit redistribution layer 202.
Described electronic component 23 is semiconductor element and is located on the second side 20b of this first semiconductor substrate 20, and is electrically connected this first conductive through holes 200.
In an embodiment, described semiconductor structure 2,2 '; 2 ", 3,3 ' also comprises an encapsulated layer 24, with this electronic component 23 coated on 24 ', its second side 20b being located at this first semiconductor substrate 20, and expose or do not expose the end face (i.e. this non-active face 23b) of this electronic component 23.In a wherein embodiment, described semiconductor structure 2 " also comprise primer 27, it is located between the second side 20b of this first semiconductor substrate 20 and this electronic component 23, makes this encapsulated layer 24 ' also this primer 27 coated.
In an embodiment, described semiconductor structure 2,2 ', 2 ", 3,3 ' also comprises multiple conducting element 25, and its 4th side 22b being located at this second semiconductor substrate 22 is electrically connected this second conductive through holes 220.
In an embodiment, described semiconductor structure 2,2 '; 2 " also comprise first line rerouting structure 21, it is located at the second side 20b of this first semiconductor substrate 20 and is electrically connected this first conductive through holes 200, this electronic component 23 is located in this first line rerouting structure 21 and is electrically connected this first line rerouting structure 21.
In an embodiment, described semiconductor structure 2 ", 3 ' also comprises the second circuit rerouting structure 26, and its 4th side 22b being located at this second semiconductor substrate 22 is electrically connected this second conductive through holes 220.
In sum, semiconductor structure of the present invention and method for making thereof, by the second semiconductor substrate as bearing part and base plate for packaging, thus without the need to removing this second semiconductor substrate, also without the need to setting up as existing base plate for packaging, so do not need the processing procedure repeatedly carrying out combining/removing bearing part, thus can significantly reduce fabrication steps and material cost.
In addition, this first and second semiconductor substrate utilizes oxide layer to make binding member, and conductive through holes is docked, and merges docking, to promote both associativities so can be formed.
Those embodiments above-mentioned are illustrative effect of the present invention only, but not for limiting the present invention, any those skilled in the art all without prejudice under spirit of the present invention and category, can implement embodiment to above-mentioned those and carry out modifying and change.In addition, illustrative is only in the quantity of the above-mentioned element that those are implemented in embodiment, also non-for limiting the present invention.Therefore the scope of the present invention, should listed by claims.