CN104768189B - Real-time communication method and real-time communication system between DSP and FPGA - Google Patents

Abstract

The invention discloses the real-time communication methods and real-time communication system between a kind of DSP and FPGA.When real-time communication method between the DSP and FPGA includes a transmission frame synchronizing signal for often receiving FPGA, all data-movings to be sent of DSP will be stored in and deposit in data transmitter register, and it will be temporarily stored into the data to be sent of data transmitter register in the next transmission frame synchronizing signal for receiving FPGA while being transmitted to the data transmission flow of FPGA, and when often receiving a reception frame synchronizing signal of FPGA, it receives and data is received by a part of the FPGA specified data length inputted simultaneously, part reception data are deposited in into data receiver register, and then the part reception data transmission of data receiver register will be deposited in the data receiver process of DSP.The present invention substantially increases the data exchange rate between DSP and FPGA, realizes two-way, real-time, high efficiency of transmission of the data between DSP and FPGA, meets the requirement that user obtains instant messaging service.

Description

Real-time communication method and real-time communication system between DSP and FPGA

Technical field

The present invention relates to fields of communication technology, more specifically to the real-time communication method between a kind of DSP and FPGAAnd real-time communication system.

Background technique

In data processing chip field, DSP has high data processing rate, and fpga chip has because of repeatable programmingThere is higher flexibility, generallys use in the industry and the DSP mode combined with FPGA is constructed one with high data-handling efficiencySignal processing system.Since there is stringent limit in processing time of the communication system (such as GSM, TD-SCDMA) to transmission dataSystem meets requirement of the user for instant messaging to reach the real-time processing of transmission data.And in above-mentioned signal processing systemIn, there are still certain delays for the data exchange process between DSP and FPGA.The data exchange effect being limited between DSP and FPGARate, above-mentioned signal processing system are still difficult to meet the requirement of user's instant messaging.

Summary of the invention

The technical problem to be solved in the present invention is that in view of the above drawbacks of the prior art, a kind of achievable data are provided and are existedReal-time communication method and real-time communication system between two-way between DSP and FPGA, real-time, high efficiency of transmission DSP and FPGA.

The technical solution adopted by the present invention to solve the technical problems is: constructing real-time logical between a kind of DSP and FPGALetter method, comprising:

When often receiving a transmission frame synchronizing signal of FPGA, all data-movings to be sent of DSP will be stored in simultaneouslyData transmitter register is deposited in, and data transmission will be temporarily stored into the next transmission frame synchronizing signal for receiving FPGA and postedThe data to be sent of storage are transmitted to the data transmission flow of FPGA simultaneously；

And when often receiving a reception frame synchronizing signal of FPGA, it is long to receive the specified data inputted simultaneously by FPGAA part of degree receives data, part reception data is deposited in data receiver register, and then will deposit in data receiverThe part of register receives data transmission to the data receiver process of DSP.

In real-time communication method between the above-mentioned DSP and FPGA of the present invention, a transmission for often receiving FPGAWhen frame synchronizing signal, all data-movings to be sent of DSP will be stored in and deposit in data transmitter register, and receivedIt will be temporarily stored into the data to be sent of data transmitter register when next transmission frame synchronizing signal of FPGA while being transmitted to FPGAData transmission flow include the following steps:

S1, McBSP carry out real time scan to FSX pin and judge that it receives a transmission frame synchronization from FPGA and believesNumber when, triggering and execute a part of data that data length is once determined for the data middle finger to be sent of the RAM that will be stored in DSPMove to the first data-moving operation of data transmitter register；

When the operation of first data-moving is finished by S2, McBSP, the part is then sent into data and is posted from data transmissionStorage moves to inner buffer；

Whether the data to be sent that S3, judgement are stored in RAM, which have been moved, finishes；If data-moving to be sent finishes, thenPerform the next step rapid S4；

S4, McBSP carry out real time scan to FSX pin and judge that it receives next transmission frame synchronization from FPGAIt will be temporarily stored into all data to be sent of caching when signal while being transmitted to FPGA.

In real-time communication method between the above-mentioned DSP and FPGA of the present invention, execution described in the step S1 is primary to be usedIt is removed in the first data that a part of data of designated length in the data to be sent for being stored in RAM are moved to data transmitter registerMoving the step of operating includes:

When S11, McBSP receive a transmission frame synchronizing signal of FPGA by FSX pin, the first number of triggering and generationIt is instructed according to moving, and sends the instruction of the first data-moving to memory management module；

S12, memory management module receive the instruction of the first data-moving, choose and refer to from the data to be sent for be stored in RAMThe a part for determining data length sends data, and the part is sent data conversion storage to data transmitter register.

In real-time communication method between the above-mentioned DSP and FPGA of the present invention, the step S3 further includes following steps:

S31, the data to be sent for such as judging in RAM are not yet moved and are finished, then trigger and execute the operation of the first data-moving,And when the operation of the first data-moving is finished, return step S2.

It further include as follows after the step S4 in real-time communication method between the above-mentioned DSP and FPGA of the present inventionStep:

S5, stop the secondary data transmission flow, generate interrupt signal, the setting ginseng of management module is internally deposited during interruptionNumber is reconfigured, and when the operation of the setting parameter reconfiguration of memory management module is finished, return step S1.

In real-time communication method between the above-mentioned DSP and FPGA of the present invention, a reception for often receiving FPGAIt when frame synchronizing signal, receives and data is received by a part of the FPGA specified data length inputted simultaneously, which is received into numberAccording to depositing in data receiver register, and then the part for depositing in data receiver register reception data transmission is arrived DSP'sData receiver process includes the following steps:

When S1 ', McBSP carry out real time scan and detect a reception frame synchronizing signal from FPGA to FSR pin,The a part for receiving the specified data length inputted from DR pin simultaneously receives data, and part reception data are stored in numberAccording to receiving register；

While part reception data are stored in data receiver register, execution connects the part by S2 ', McBSPReceive the second data-moving operation that data move to DSP.

In real-time communication method between the above-mentioned DSP and FPGA of the present invention, triggering described in the step S2 ' and executionThe part, which is received the step of data move to the second data-moving operation of DSP, includes:

When the part receives data deposit data receiver register, triggering and generation are used for the part by S21 ', McBSPThe second data-moving instruction that data move to RAM from data receiver register is received, and sends the second number to memory management moduleIt is instructed according to moving；

When S22 ', memory management module receive the instruction of the second data-moving, being somebody's turn to do for data receiver register will be temporarily stored intoPart receives data-moving and dumps to RAM.

In real-time communication method between the above-mentioned DSP and FPGA of the present invention, the step S22 ' further include later asLower step:

S23 ', real time scan is carried out to FSR pin to judge whether to continue to the reception frame synchronization letter from FPGANumber；The reception frame synchronizing signal from FPGA is such as continued to, then return step S1 '；Otherwise, stop the secondary data receiving streamJourney.

In real-time communication method between the above-mentioned DSP and FPGA of the present invention, the step S23 ' further include later asLower step:

S24 ', interrupt signal is generated, the setting parameter that management module is internally deposited during interruption is reconfigured, and in memoryWhen the setting parameter reconfiguration operation of management module is finished, return step S1 '.

The present invention also constructs the real-time communication system between a kind of DSP and FPGA, including DSP and FPGA, the DSP configurationThere is at least one McBSP and established by the McBSP and FPGA and communicated to connect, the McBSP includes data transmitter registerAnd data receiver register；

When each McBSP is used to receive a transmission frame synchronizing signal of the FPGA, it will be stored in describedAll data-movings to be sent of DSP simultaneously deposit in the data transmitter register, and are provided receiving by the FPGAIt by the data to be sent being temporarily stored into the data transmitter register while being transmitted to described when next transmission frame synchronizing signalFPGA；

Each McBSP is also used in a reception frame synchronizing signal for often receiving the FPGA, is received by instituteThe a part for stating FPGA while the specified data length of input receives data, and part reception data are deposited in the data and are connectRegister is received, and then the part for depositing in the data receiver register is received into data transmission to the DSP.

Real-time communication method and real-time communication system between implementation DSP and FPGA of the present invention is, it can be achieved that following beneficial to effectFruit:

1, the present invention is greatly improved using the McBSP in DSP as the data transmit-receive terminal between DSP and FPGAData exchange efficiency between DSP and the FPGA of outside.

2, the present invention uses the data exchange between the McBSP and RAM in EDMA technical application to DSP simultaneouslyThe data synchronization processing mechanism of McBSP and memory management module.On the one hand, the work of the memory management module in DSP is without accounting forWith the processor resource of DSP, the operating load of DSP is reduced；On the other hand, the above-mentioned data synchronization processing mechanism of the present invention is very bigGround improves the data exchange rate between DSP internal element (i.e. McBSP and RAM), realizes data between DSP and FPGATwo-way, real-time Transmission.

3, controlling mechanism is interrupted in setting during data transmit-receive of the present invention between DSP/FPGA, and the present invention can will be in thisDisconnected controlling mechanism is closely connected with the data handling procedure of DSP, to be adapted to require the data process limited harsh communication systemSystem.

Detailed description of the invention

Fig. 1 is the structure of the real-time communication system between DSP and FPGA that first preferred embodiment of the invention providesBlock diagram；

The structural block diagram of the DSP of real-time communication system of the Fig. 2 between DSP shown in FIG. 1 and FPGA；

Fig. 3 is the structural block diagram of the McBSP of DSP shown in Fig. 2；

Fig. 4 is in real-time communication method between DSP and FPGA that second preferred embodiment of the invention providesThe flow chart of data transmission flow from DSP to FPGA；

Fig. 5 is in real-time communication method between DSP and FPGA that third preferred embodiment of the present invention providesThe flow chart of data receiver process from FPGA to DSP.

Specific embodiment

There are one between DSP100 and FPGA200 in order to solve the existing signal processing system applied to communication base stationFixed data transmission delay causes communication base station that can not provide the defect of instant messaging service, innovative point of the invention for userIt is:

1, by McBSP101 (the Multichannel Buffered Serial Port, i.e. multichannel buffer in DSP100Serial port) as the data transmit-receive terminal between communicating pair DSP100 and FPGA200, improve DSP100 and outsideData exchange efficiency between FPGA200.

2, the present invention is by EDMA (Enhanced Direct MemoryAccess) technical application into DSP100Data exchange between McBSP101 and RAM103, while it is synchronous with the data of memory management module 102 to use McBSP101Treatment mechanism.

The data synchronization processing mechanism is as follows: in the data transmission flow from DSP100 to FPGA200, McBSP101 mono-Denier detects a transmission frame synchronizing signal from FPGA200, then first all moves to the data to be sent in RAM103 interiorPortion's caching, then an EDMA event is triggered and generates, so that the data to be sent for being temporarily stored into inner buffer all be dumped toFPGA200；In the data receiver process from FPGA200 to DSP100, McBSP101 often detects one from FPGA200It when receiving frame synchronizing signal, while receiving and data is received by the part that FPGA200 is provided, and trigger and generate an EDMA thingPart, so that part reception data to be dumped to the RAM103 of DSP100 from McBSP101.

Thus, on the one hand, processor resource of the work of the memory management module 102 of DSP100 without occupying DSP100,The operating load of DSP100 is reduced, on the other hand, the present invention is greatly mentioned applied to the data synchronization processing mechanism of DSP100Data exchange rate between high DSP100 internal element (i.e. McBSP101 and RAM103), reached data DSP100 withThe technical effect of real-time Transmission between FPGA200.

3, controlling mechanism is interrupted in setting during data transmit-receive between DSP100/FPGA200, and can pass through the interruptionControlling mechanism is closely connected with the data handling procedure of DSP100, to be adapted to require the data process limited harsh communication systemSystem.

Since present invention employs using the McBSP101 in DSP100 as between communicating pair DSP100 and FPGA200Data transmit-receive terminal, and by EDMA technical application to the design of the data exchange between DSP100 internal element, so solutionDetermined in the prior art applied to communication base station signal processing system DSP100 and FPGA200 between there are certain dataPropagation delay time causes communication base station that can not provide the technical issues of instant messaging services for user, realizes data in DSP100Two-way, real-time, high efficiency of transmission between FPGA200, and realize and provide instant messaging service by base station for userPurpose.

Below in conjunction with accompanying drawings and embodiments, the invention will be further described:

Firstly, being applied to by taking first better embodiment of the invention as an example in conjunction with attached drawing 1 to 3 couples of present invention of attached drawingThe system architecture of the communication system of DSP100 and FPGA200 is illustrated:

As shown in Figure 1, being applied to DSP100 (Digital Signal Processor, i.e., at digital signal in the present inventionManage device) and the communication system of FPGA200 (Field-Programable Gate Array, i.e. field programmable gate array) in,The DSP100 is configured at least one McBSP101 (Multichannel Buffered Serial Port, i.e. multichannel bufferSerial port), and established and communicated to connect by McBSP101 and FPGA200.Each McBSP101 includes that data send depositDevice 1019 (DXR) and data receiver register 1018 (DRR).

When each above-mentioned McBSP101 is used to receive a transmission frame synchronizing signal of FPGA200, it will be stored inData transmitter register 1019 is all moved and deposited in the data to be sent of DSP100, and is receiving the next of FPGA200It by all data to be sent being temporarily stored into data transmitter register 1019 while being transmitted to when a transmission frame synchronizing signalFPGA200。

Each above-mentioned McBSP101 is also used to when often receiving from FPGA200 reception frame synchronizing signal,It receives and data is received by a part of the FPGA200 specified data length inputted simultaneously, part reception data are deposited in into numberData transmission is received to DSP100 according to receiving register 1018, and then by the part for depositing in data receiver register 1018.

As shown in Fig. 2, in the present invention, DSP100 includes at least one sequentially connected McBSP101, memory management mouldBlock 102 and RAM103 (RandomAccess Memory).

The RAM103 is for storing data to be sent and the reception data from FPGA200.

When the McBSP101 is used to receive a transmission frame synchronizing signal from FPGA200, triggering and generation firstData-moving instruction, and the instruction of the first data-moving is sent to memory management module 102.

The memory management module 102 is for executing the instruction of the first data-moving, from the data to be sent for being stored in RAM103Middle a part for choosing specified data length sends data (i.e. 32bit data), and the part is sent data-moving and storageIn the data transmitter register 1019 of McBSP101.

When the McBSP101 is also used to judge that part transmission data move to caching, triggering and the first data-moving of generation refer toIt enables, and sends the instruction of the first data-moving to memory management module 102.

The McBSP101, which is also used to the part for being temporarily stored into data transmitter register 1019 sending data, moves to caching, withAnd the data to be sent in caching are transmitted to when having moved into caching by the data to be sent for judging in RAM103 togetherFPGA200。

The McBSP101 is also used to receive the reception frame synchronizing signal inputted by FPGA200 by FSR pin and pass throughDR pin, which is received, receives data (i.e. 32bit data) by a part of the FPGA200 specified data length inputted simultaneously, and shouldPart receives data and is temporarily stored into data receiver register 1018.

The processing module is also used to generate the instruction of the second data-moving, and control memory management module 102 will be temporarily stored into dataThe part of receiving register 1018 receives data-moving and dumps to RAM103.

The present invention has arrived EDMA (Enhanced Direct Memory Access) technical application in DSP100Data-moving process between McBSP101 and RAM103 substantially increases the data exchange efficiency of DSP100 internal element.

As shown in figure 3, McBSP101 of the present invention includes FSR pin 1011 (receiving frame synchronization), (transmission of FSX pin 1012Frame synchronization), DR pin 1013 (Serial data receiving), DX pin 1014 (serial data transmission), CLKR pin 1015 is (when receptionClock), CLKX pin 1016 (tranmitting data register), caching 1017, data receiver register 1018 (DRR) and data transmitter register1019(DXR)。

Below by by taking second better embodiment of the invention as an example, in conjunction with Fig. 4 to the present invention from DSP100 toThe data transmission flow of FPGA200 is illustrated:

As shown in figure 4, in step s101, the tranmitting data register signal and hair to be received from FPGA200 such as McBSP101Send frame synchronizing signal.

In step s 102, McBSP101 comes from the progress real time scan of FSX pin 1012 to judge whether it receivesThe tranmitting data register signal and transmission frame synchronizing signal of FPGA200.As McBSP101 receives the transmission frame synchronization letter of FPGA200Number, then follow the steps S103.Otherwise, previous step S101 is returned.

In step s 103, McBSP101 triggering and generation the first data-moving instruction, and sent out to memory management module 102The first data-moving is sent to instruct.

In step S104, memory management module 102 receives the instruction of the first data-moving, from being stored in the pending of RAM103The a part for choosing specified data length in data is sent to send data (i.e. the transmission data of 32bit), and by the transmission of the 32bitThe data transmitter register 1019 of McBSP101 is arrived in data-moving and storage.

In step s105, the transmission data that McBSP101 will be temporarily stored into the 32bit of data transmitter register 1019 are movedTo its inner buffer.

In step s 106, whether McBSP101 judges the data to be sent in RAM103 by memory management module 102Have moved into the caching of McBSP101.If the data to be sent in RAM103 do not move to the caching of McBSP101 all, then recycleStep S103 to step S105 is executed, until the data to be sent in RAM103 move to the inner buffer of McBSP101.Otherwise,Perform the next step rapid S107.

In step s 107, the data that McBSP101 receives DSP100 send instruction, will be temporarily stored into the number to be sent of cachingAccording to being transmitted to FPGA200 together.

In step S108, the real-time communication system between DSP100 and FPGA200 of the present invention is completed the batchData to be sent (data of total 16 32bit) send operation from the data that DSP100 is transmitted to FPGA200, stop fromThe data transmission flow of DSP100 to FPGA200, and interrupt signal is generated by McBSP101.

In step S109, the setting parameter that DSP100 internally deposits management module 102 during interruption is reconfigured,In order to going on smoothly for next data transmission flow from DSP100 to FPGA200.

Step S109 jumps back to step S101 after being finished.

Below by by taking third better embodiment of the invention as an example, in conjunction with Fig. 5 to the present invention from FPGA200 toThe data receiver process of DSP100 is illustrated:

As shown in figure 5, in step S101 ', the reception clock signal to be received from FPGA200 such as McBSP101 and connectReceive frame synchronizing signal.

In step S102 ', McBSP101 carries out real time scan to FSR pin 1011 and is come from judging whether it receivesA reception frame synchronizing signal of FPGA200.As McBSP101 does not receive reception clock from FPGA200 and receiving frame is sameSignal is walked, then return step S101 '.As McBSP101 has received the reception clock from FPGA200 and receives frame synchronization letterNumber, then perform the next step rapid S103 '.

In step S103 ', McBSP101 is received by DR pin by the FPGA200 specified data length inputted simultaneouslyA part receives data (i.e. 32bit receives data).

In step S104 ', which is received data-moving and keeps in data receiver register by McBSP1011018。

In step S105 ', McBSP101 triggering and generation will be for that will be temporarily stored into being somebody's turn to do for data receiver register 101832bit receives data and moves to the second data-moving instruction of RAM103, and sends the second data-moving to memory management module 102Instruction.

In step S106 ', memory management module 102 receives the instruction of the second data-moving, will be temporarily stored into data receiver and postsThe 32bit of storage 1018 receives data-moving and dumps to RAM103.

In step S107 ', McBSP101 carries out real time scan to FSR pin and is come from judging whether it receivesNext reception frame synchronizing signal of FPGA200.As McBSP101 receives the letter of next reception frame synchronization from FPGA200Number, then it recycles and executes step S103 ' to S107 '.Otherwise, rapid S108 ' is performed the next step.

In step S108 ', the real-time communication system between DSP100 and FPGA200 of the present invention is completed the batchData to be received (amounting to 156 32bit data) are transmitted to the data reception operation of DSP100 from FPGA200, stop fromThe secondary data receiving stream journey of FPGA200 to DSP100, and interrupt signal is generated by FPGA200.

In step S109 ', the setting parameter that DSP100 internally deposits management module 102 during interruption is matched againIt sets, in order to going on smoothly for next data receiver process from FPGA200 to DSP100.

Step S109 ' jumps back to step S101 ' after being finished.

The embodiment of the present invention is described with above attached drawing, but the invention is not limited to above-mentioned specificEmbodiment, the above mentioned embodiment is only schematical, rather than restrictive, those skilled in the artUnder the inspiration of the present invention, without breaking away from the scope protected by the purposes and claims of the present invention, it can also make very muchForm, all of these belong to the protection of the present invention.

Claims (10)

1. the real-time communication method between a kind of DSP and FPGA, which is characterized in that a transmission frame including often receiving FPGAWhen synchronization signal, all data-movings to be sent of DSP will be stored in and deposit in data transmitter register, and receivedIt will be temporarily stored into the data to be sent of data transmitter register when next transmission frame synchronizing signal of FPGA while being transmitted to FPGAData transmission flow；

And when often receiving a reception frame synchronizing signal of FPGA, receive by the FPGA specified data length inputted simultaneouslyA part receives data, part reception data is deposited in data receiver register, and then will deposit in data receiver depositThe part of device receives data transmission to the data receiver process of DSP.

2. the real-time communication method between DSP according to claim 1 and FPGA, which is characterized in that described often to receiveWhen a transmission frame synchronizing signal of FPGA, all data-movings to be sent of DSP will be stored in and deposit in data transmission and postedStorage, and the data to be sent of data transmitter register will be temporarily stored into the next transmission frame synchronizing signal for receiving FPGAThe data transmission flow for being transmitted to FPGA simultaneously includes the following steps:

S1, McBSP carry out real time scan to FSX pin and judge that it receives a transmission frame synchronizing signal from FPGAWhen, a part of data that the data middle finger to be sent for the RAM that triggering and execution once are used to that DSP will to be stored in determines data length are movedThe first data-moving to data transmitter register operates；

When the operation of first data-moving is finished by S2, McBSP, the part is then sent into data from data transmitter registerMove to inner buffer；

Whether the data to be sent that S3, judgement are stored in RAM, which have been moved, finishes；If data-moving to be sent finishes, then executeNext step S4；

S4, McBSP carry out real time scan to FSX pin and judge that it receives next transmission frame synchronizing signal from FPGAWhen will be temporarily stored into all data to be sent of caching while being transmitted to FPGA.

3. the real-time communication method between DSP according to claim 2 and FPGA, which is characterized in that in the step S1The triggering and execution are once for moving to data hair for a part of data for being stored in designated length in the data to be sent of RAMSend register the first data-moving operate the step of include:

When S11, McBSP receive a transmission frame synchronizing signal of FPGA by FSX pin, triggering and the first data of generation are removedInstruction is moved, and sends the instruction of the first data-moving to memory management module；

S12, memory management module receive the instruction of the first data-moving, and specified number is chosen from the data to be sent for be stored in RAMData are sent according to a part of length, and the part is sent into data conversion storage to data transmitter register.

4. the real-time communication method between DSP according to claim 2 and FPGA, which is characterized in that the step S3 is alsoInclude the following steps:

S31, the data to be sent for such as judging in RAM are not yet moved and are finished, then trigger and execute the operation of the first data-moving, andWhen the operation of first data-moving is finished, return step S2.

5. the real-time communication method between DSP according to claim 2 and FPGA, which is characterized in that in the step S4Later further include following steps:

S5, stop the secondary data transmission flow, generate interrupt signal, internally deposited during interruption the setting parameter of management module intoRow reconfiguration, and when the operation of the setting parameter reconfiguration of memory management module is finished, return step S1.

6. the real-time communication method between DSP according to claim 1 and FPGA, which is characterized in that described often to receiveWhen a reception frame synchronizing signal of FPGA, receives and data is received by a part of the FPGA specified data length inputted simultaneously,Part reception data are deposited in into data receiver register, and then the part for depositing in data receiver register is received into numberInclude the following steps: according to the data receiver process for being transmitted to DSP

When S1 ', McBSP carry out real time scan and detect a reception frame synchronizing signal from FPGA to FSR pin, simultaneouslyThe a part for receiving the specified data length inputted from DR pin receives data, and part reception data are stored in data and are connectReceive register；

S2 ', McBSP are executed the part being received number while part reception data are stored in data receiver registerIt is operated according to the second data-moving for moving to DSP.

7. the real-time communication method between DSP according to claim 6 and FPGA, which is characterized in that in the step S2 'The part is received the step of data move to the second data-moving operation of DSP by the execution

When the part receives data deposit data receiver register, triggering and generation are for receiving the part by S21 ', McBSPData move to the second data-moving instruction of RAM from data receiver register, and send the second data to memory management module and removeMove instruction；

When S22 ', memory management module receive the instruction of the second data-moving, the part of data receiver register will be temporarily stored intoIt receives data-moving and dumps to RAM.

8. the real-time communication method between DSP according to claim 7 and FPGA, which is characterized in that in the stepS22 ' further includes following steps later:

S23 ', real time scan is carried out to FSR pin to judge whether to continue to the reception frame synchronizing signal from FPGA；Such asThe reception frame synchronizing signal from FPGA is continued to, then return step S1 '；Otherwise, stop the secondary data receiving stream journey.

9. the real-time communication method between DSP according to claim 8 and FPGA, which is characterized in that in the stepS23 ' further includes following steps later:

S24 ', interrupt signal is generated, the setting parameter that management module is internally deposited during interruption is reconfigured, and in memory managementWhen the setting parameter reconfiguration operation of module is finished, return step S1 '.

10. a kind of real-time communication method of application between the DSP and FPGA as described in any in claim 1 to 9 is real-time logicalLetter system, including DSP and FPGA, the DSP are communicated configured at least one McBSP and by McBSP with FPGA foundationConnection, which is characterized in that the McBSP includes data transmitter register and data receiver register；

When each McBSP is used to receive a transmission frame synchronizing signal of the FPGA, it will be stored in the DSP'sAll data-movings to be sent simultaneously deposit in the data transmitter register, and receive provided by the FPGA it is nextBy the data to be sent being temporarily stored into the data transmitter register while the FPGA is transmitted to when sending frame synchronizing signal；

Each McBSP is also used in a reception frame synchronizing signal for often receiving the FPGA, is received by describedThe a part for the specified data length that FPGA is inputted simultaneously receives data, and part reception data are deposited in the data receiverRegister, and then the part for depositing in the data receiver register is received into data transmission to the DSP.