技术领域technical field
本发明涉及半导体领域，尤其涉及金属栅极的形成方法。The invention relates to the field of semiconductors, in particular to a method for forming a metal gate.
背景技术Background technique
随着集成电路制造技术的不断发展，MOS晶体管的特征尺寸也越来越小，在MOS晶体管特征尺寸不断缩小情况下，为了降低MOS晶体管栅极的寄生电容，提高器件速度，金属栅极被引入到MOS晶体管中。With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller. In the case of continuous shrinking of the feature size of MOS transistors, in order to reduce the parasitic capacitance of the gate of the MOS transistor and increase the speed of the device, the metal gate is introduced into the MOS transistor.
图1至图4是现有技术中金属栅极的形成方法的剖面结构示意图。1 to 4 are schematic cross-sectional structure diagrams of a method for forming a metal gate in the prior art.
参考图1，提供半导体衬底100，在所述衬底100上形成伪栅极101，所述伪栅极的材料为多晶硅。接着，形成覆盖衬底100和伪栅极101的氧化硅层102，氧化硅层102的顶部与伪栅极101的顶部相平。Referring to FIG. 1 , a semiconductor substrate 100 is provided, on which a dummy gate 101 is formed, and the material of the dummy gate is polysilicon. Next, a silicon oxide layer 102 covering the substrate 100 and the dummy gate 101 is formed, and the top of the silicon oxide layer 102 is level with the top of the dummy gate 101 .
参考图2，采用干法刻蚀的方法去除伪栅极101（参考图1），在氧化硅层102的内部形成栅极凹槽103。Referring to FIG. 2 , the dummy gate 101 (refer to FIG. 1 ) is removed by dry etching, and a gate groove 103 is formed inside the silicon oxide layer 102 .
参考图3，形成铝材料层104’，所述铝材料层104’填满栅极凹槽103并覆盖氧化硅层102的顶部。Referring to FIG. 3 , an aluminum material layer 104' is formed, which fills the gate groove 103 and covers the top of the silicon oxide layer 102. Referring to FIG.
参考图4，采用化学机械研磨的方法，使得铝材料层104’（参考图3）的顶部与氧化硅层102的顶部相平，形成铝栅极104。Referring to FIG. 4 , the top of the aluminum material layer 104' (refer to FIG. 3 ) is flush with the top of the silicon oxide layer 102 by using a chemical mechanical polishing method to form an aluminum gate 104 .
采用现有技术的方法形成的金属栅极性能不好，严重时，金属栅极无法正常工作。The performance of the metal grid formed by the method of the prior art is not good, and in severe cases, the metal grid cannot work normally.
发明内容Contents of the invention
本发明解决的问题是采用现有技术的方法形成的金属栅极性能不好，严重时，金属栅极无法正常工作。The problem solved by the invention is that the performance of the metal grid formed by the method of the prior art is not good, and in severe cases, the metal grid cannot work normally.
为解决上述问题，本发明提供一种金属栅极的形成方法，包括：In order to solve the above problems, the present invention provides a method for forming a metal gate, including:
提供半导体衬底，在所述衬底表面形成伪栅极，在衬底上形成层间介质层，所述层间介质层顶部与所述伪栅极顶部相平；A semiconductor substrate is provided, a dummy gate is formed on the surface of the substrate, an interlayer dielectric layer is formed on the substrate, and the top of the interlayer dielectric layer is level with the top of the dummy gate;
利用外延生长形成至少覆盖所述伪栅极顶部的第一牺牲层；forming a first sacrificial layer covering at least the top of the dummy gate by epitaxial growth;
在层间介质层上形成第二牺牲层，所述第二牺牲层顶部与所述第一牺牲层顶部相平；forming a second sacrificial layer on the interlayer dielectric layer, the top of the second sacrificial layer being level with the top of the first sacrificial layer;
去除所述第一牺牲层，在所述第二牺牲层内形成开口，所述开口底部露出所述伪栅极顶部；removing the first sacrificial layer, forming an opening in the second sacrificial layer, the bottom of the opening exposing the top of the dummy gate;
去除所述第一牺牲层后，去除所述伪栅极，在所述层间介质层内形成栅极凹槽；After removing the first sacrificial layer, removing the dummy gate, forming a gate groove in the interlayer dielectric layer;
去除第二牺牲层，在所述栅极凹槽内填充金属层形成金属栅极。The second sacrificial layer is removed, and a metal layer is filled in the gate groove to form a metal gate.
可选的，在层间介质层上形成第二牺牲层的方法包括：Optionally, the method for forming the second sacrificial layer on the interlayer dielectric layer includes:
形成第二牺牲材料层，覆盖所述层间介质层和第一牺牲层；forming a second sacrificial material layer to cover the interlayer dielectric layer and the first sacrificial layer;
去除高于第一牺牲层顶部的第二牺牲材料层。The second layer of sacrificial material above the top of the first sacrificial layer is removed.
可选的，所述第二牺牲层的材料为非晶碳、第一聚合物或底部抗反射层，所述第一聚合物包括碳元素或者氟、溴、氯元素中的一种或它们的任意组合。Optionally, the material of the second sacrificial layer is amorphous carbon, the first polymer or the bottom anti-reflection layer, and the first polymer includes carbon or one of fluorine, bromine, chlorine or their random combination.
可选的，形成所述第二牺牲材料层的方法为沉积或涂抹；Optionally, the method of forming the second sacrificial material layer is deposition or smearing;
去除高于第一牺牲层顶部的第二牺牲材料层的方法为化学机械研磨或刻蚀。The method of removing the second sacrificial material layer above the top of the first sacrificial layer is chemical mechanical grinding or etching.
可选的，去除第二牺牲层的方法为灰化。Optionally, the method for removing the second sacrificial layer is ashing.
可选的，所述第一牺牲层还覆盖部分层间介质层，去除第一牺牲层后，去除所述伪栅极的步骤之前，还包括步骤：在所述开口侧壁形成牺牲侧墙；Optionally, the first sacrificial layer also covers part of the interlayer dielectric layer, and after removing the first sacrificial layer, before the step of removing the dummy gate, further includes the step of: forming a sacrificial sidewall on the sidewall of the opening;
去除所述伪栅极的步骤之后，去除第二牺牲层的步骤之前，还包括步骤：去除所述牺牲侧墙。After the step of removing the dummy gate and before the step of removing the second sacrificial layer, a step is further included: removing the sacrificial sidewall.
可选的，所述牺牲侧墙的形成方法包括：Optionally, the method for forming the sacrificial sidewall includes:
形成牺牲侧墙材料层，填充所述开口并覆盖所述第二牺牲层；forming a layer of sacrificial sidewall material filling the opening and covering the second sacrificial layer;
刻蚀所述牺牲侧墙材料层，在所述开口侧壁形成牺牲侧墙。Etching the material layer of the sacrificial sidewall to form a sacrificial sidewall on the sidewall of the opening.
可选的，所述牺牲侧墙的材料为第二聚合物，所述第二聚合物由烃类气体制备。Optionally, the material of the sacrificial sidewall is a second polymer, and the second polymer is prepared from hydrocarbon gas.
可选的，去除所述牺牲侧墙的方法为灰化。Optionally, the method for removing the sacrificial sidewall is ashing.
可选的，所述第一牺牲层的材料与所述伪栅极的材料相同。Optionally, the material of the first sacrificial layer is the same as that of the dummy gate.
可选的，所述伪栅极的材料为多晶硅，所述第一牺牲层的材料为多晶硅。Optionally, the material of the dummy gate is polysilicon, and the material of the first sacrificial layer is polysilicon.
可选的，去除第一牺牲层的方法为湿法腐蚀或者干法刻蚀。Optionally, the method for removing the first sacrificial layer is wet etching or dry etching.
可选的，在所述衬底表面形成伪栅极的步骤之后，在衬底上形成层间介质层的步骤之前，还包括：Optionally, after the step of forming a dummy gate on the surface of the substrate and before the step of forming an interlayer dielectric layer on the substrate, the method further includes:
在所述伪栅极周围形成侧墙。A spacer is formed around the dummy gate.
可选的，所述层间介质层的材料为氧化硅。Optionally, the material of the interlayer dielectric layer is silicon oxide.
可选的，在所述衬底和所述伪栅极之间还包括栅介质层，所述栅极凹槽底部露出所述栅介质层，所述栅介质层为高k栅介质层。Optionally, a gate dielectric layer is further included between the substrate and the dummy gate, the gate dielectric layer is exposed at the bottom of the gate groove, and the gate dielectric layer is a high-k gate dielectric layer.
可选的，在所述衬底和所述伪栅极之间还包括栅介质层，所述栅极凹槽底部露出所述栅介质层，所述栅介质层为氧化硅层，去除第二牺牲层之后，在所述栅极凹槽内填充金属层的步骤之前，还包括：去除所述氧化硅层，在所述栅极凹槽的底部和侧壁形成高k栅介质层。Optionally, a gate dielectric layer is further included between the substrate and the dummy gate, the gate dielectric layer is exposed at the bottom of the gate groove, the gate dielectric layer is a silicon oxide layer, and the second After the sacrificial layer, before the step of filling the metal layer in the gate groove, the method further includes: removing the silicon oxide layer, and forming a high-k gate dielectric layer on the bottom and side walls of the gate groove.
与现有技术相比，本发明的技术方案具有以下优点：Compared with the prior art, the technical solution of the present invention has the following advantages:
采用外延生长的方法形成至少覆盖伪栅极顶部的第一牺牲层，第一牺牲层能够将伪栅极全部覆盖，而且，第一牺牲层的位置决定了第二牺牲层内的开口的位置，从而使得第二牺牲层能够准确的将伪栅极顶部露出。此时，第二牺牲层将伪栅极周围的层间介质层进行覆盖，从而在去除伪栅极的过程中，第二牺牲层会对层间介质层进行保护，防止层间介质层也被刻蚀到，防止层间介质层的高度减小。这个过程是自对准过程，在刻蚀去除伪栅极前，形成的第二牺牲层能够精确的将伪栅极露出。与在层间介质层上形成只露出伪栅极顶部的光刻胶方法相比，能够避免对准精度差的问题。因此采用自对准的方法可以很好的保护层间介质层在去除伪栅极的过程中不受损伤，从而使栅极凹槽的深度不会减小，进而使后续形成的金属栅极的高度不会减小。保证了后续在该栅极凹槽内形成的金属栅极的高度，提高了金属栅极的性能。The epitaxial growth method is used to form a first sacrificial layer covering at least the top of the dummy gate, the first sacrificial layer can completely cover the dummy gate, and the position of the first sacrificial layer determines the position of the opening in the second sacrificial layer, Therefore, the second sacrificial layer can accurately expose the top of the dummy gate. At this time, the second sacrificial layer covers the interlayer dielectric layer around the dummy gate, so that in the process of removing the dummy gate, the second sacrificial layer will protect the interlayer dielectric layer and prevent the interlayer dielectric layer from being destroyed. etch to prevent the height reduction of the interlayer dielectric layer. This process is a self-alignment process, and before the dummy gate is etched away, the formed second sacrificial layer can accurately expose the dummy gate. Compared with the method of forming photoresist on the interlayer dielectric layer that only exposes the top of the dummy gate, the problem of poor alignment accuracy can be avoided. Therefore, the self-alignment method can well protect the interlayer dielectric layer from damage during the process of removing the dummy gate, so that the depth of the gate groove will not be reduced, and the subsequent formation of the metal gate will not be damaged. The height will not decrease. The height of the metal gate subsequently formed in the gate groove is ensured, and the performance of the metal gate is improved.
附图说明Description of drawings
图1至图4是现有技术中金属栅极的形成方法的剖面结构示意图；1 to 4 are schematic cross-sectional structure diagrams of a method for forming a metal gate in the prior art;
图5至图12是本发明具体实施例中的金属栅极的形成方法的剖面结构示意图。5 to 12 are schematic cross-sectional structure diagrams of a method for forming a metal gate in a specific embodiment of the present invention.
具体实施方式Detailed ways
采用现有技术的方法形成的金属栅极性能不好，严重时，金属栅极无法正常工作的原因如下：The performance of the metal grid formed by the method of the prior art is not good. In severe cases, the reasons why the metal grid cannot work normally are as follows:
参考图2，采用刻蚀的方法去除伪栅极101（参考图1）时，即使氧化硅层102与伪栅极101之间的刻蚀选择比相差很大，也会造成氧化硅层102的损失，使得氧化硅层102的厚度有所减小，相应的使栅极凹槽103的深度也有所减小。Referring to FIG. 2, when the dummy gate 101 is removed by etching (refer to FIG. 1), even if the etching selection ratio between the silicon oxide layer 102 and the dummy gate 101 is very different, it will cause the silicon oxide layer 102 The loss reduces the thickness of the silicon oxide layer 102 and correspondingly reduces the depth of the gate groove 103 .
参考图4，采用化学机械研磨的方法，使得铝材料层104’（参考图3）的顶部与氧化硅层102的顶部相平时，受化学研磨设备条件限制，为了确保不在氧化硅层102表面残留铝材料，会多研磨一些氧化硅层102，从而使得氧化硅层102的高度继续降低，相应的使后续形成的铝栅极104的高度也进一步降低。Referring to FIG. 4, when the top of the aluminum material layer 104' (refer to FIG. 3) is equal to the top of the silicon oxide layer 102 by chemical mechanical polishing, it is limited by the conditions of the chemical polishing equipment. In order to ensure that no For aluminum materials, more silicon oxide layer 102 will be ground, so that the height of silicon oxide layer 102 will continue to decrease, and the height of aluminum gate 104 formed subsequently will be further reduced accordingly.
铝栅极104的高度如果太低，影响栅极阻值，进而影响栅极控制沟道电流的能力，因此，铝栅极104的性能不好，严重时，无法正常工作。If the height of the aluminum grid 104 is too low, the resistance of the grid will be affected, thereby affecting the ability of the grid to control the channel current. Therefore, the performance of the aluminum grid 104 is not good, and in serious cases, it cannot work normally.
为了避免上述技术问题，发明人做过以下尝试来解决该技术问题，第一种尝试具体为：参考图1，在形成氧化硅层102时，采用增加氧化硅层102厚度的方法，但是，参考图2，在形成栅极凹槽103后，栅极凹槽103的深度会增加，从而在栅极凹槽103内填充铝材料层104’的步骤中，由于栅极凹槽103的深宽比太大，从而会使填充在栅极凹槽103内的铝材料层104’（参考图3）内部具有缝隙，从而影响后续形成的铝栅极的性能。因此，在形成氧化硅层102时，可以采用增加氧化硅层102厚度的方法不适用。In order to avoid the above-mentioned technical problem, the inventor has made the following attempts to solve this technical problem. The first attempt is specifically: referring to FIG. 2, after forming the gate groove 103, the depth of the gate groove 103 will increase, so that in the step of filling the gate groove 103 with the aluminum material layer 104', due to the aspect ratio of the gate groove 103 If it is too large, there will be gaps inside the aluminum material layer 104 ′ (refer to FIG. 3 ) filled in the gate groove 103 , thereby affecting the performance of the subsequently formed aluminum gate. Therefore, when forming the silicon oxide layer 102 , the method of increasing the thickness of the silicon oxide layer 102 is not applicable.
第二种尝试具体为：参考图1和图2，在刻蚀去除伪栅极101的过程中，为了减小氧化硅层102的损失，可以在氧化硅层102的上面形成图案化的光刻胶层（图未示），所述图案化的光刻胶覆盖氧化硅层102，同时露出伪栅极101。然后以图案化的光刻胶为掩膜对伪栅极101进行刻蚀，在氧化硅层102内形成栅极凹槽103。这种方法也很难减小氧化硅层102的损失，原因如下：伪栅极101的CD尺寸太小，再加上光刻工艺的对准精度的限制，很难将图案化的光刻胶正好露出伪栅极101，同时也会或多或少的露出氧化硅层102，因此，没有被图案化的光刻胶覆盖的氧化硅层102也会被刻蚀，接着，形成铝材料层104’（参考图3）的过程中，被刻蚀的氧化硅层102处也会填充铝材料层104’，然后，参考图4，采用化学机械抛光工艺将高于氧化硅层102上的铝材料层104’去除的过程中，为了去除被刻蚀的氧化硅层102处填充的铝材料层104’，会使氧化硅层102的整体高度大幅度下降，从而使栅极凹槽103的深度下降，进而使形成金属栅极高度减小。因此，采用图案化的光刻胶覆盖氧化硅层102的方法不适用。The second attempt is specifically: referring to FIG. 1 and FIG. 2 , in order to reduce the loss of the silicon oxide layer 102 during the process of etching and removing the dummy gate 101 , a patterned photolithographic pattern can be formed on the silicon oxide layer 102 . A glue layer (not shown in the figure), the patterned photoresist covers the silicon oxide layer 102 and exposes the dummy gate 101 at the same time. Then, the dummy gate 101 is etched using the patterned photoresist as a mask to form a gate groove 103 in the silicon oxide layer 102 . This method is also difficult to reduce the loss of the silicon oxide layer 102, the reasons are as follows: the CD size of the dummy gate 101 is too small, coupled with the limitation of the alignment accuracy of the photolithography process, it is difficult to make the patterned photoresist The dummy gate 101 is just exposed, and the silicon oxide layer 102 is more or less exposed at the same time. Therefore, the silicon oxide layer 102 not covered by the patterned photoresist will also be etched, and then the aluminum material layer 104 is formed. '(refer to FIG. 3), the etched silicon oxide layer 102 will also be filled with an aluminum material layer 104', and then, referring to FIG. In the process of removing the layer 104', in order to remove the aluminum material layer 104' filled in the etched silicon oxide layer 102, the overall height of the silicon oxide layer 102 will be greatly reduced, thereby reducing the depth of the gate groove 103 , thereby reducing the height of the formed metal gate. Therefore, the method of covering the silicon oxide layer 102 with a patterned photoresist is not applicable.
因此，为了解决本发明的技术问题，本发明提供了一种金属栅极的形成方法，采用本发明的方法形成的金属栅极，可以提高后续形成的金属栅极的性能。Therefore, in order to solve the technical problem of the present invention, the present invention provides a method for forming a metal gate. The metal gate formed by the method of the present invention can improve the performance of the subsequently formed metal gate.
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
首先，参考图5，执行步骤S11，提供半导体衬底200，在所述衬底200表面形成伪栅极201，在衬底上形成层间介质层204，所述层间介质层204顶部与所述伪栅极201顶部相平。First, referring to FIG. 5, step S11 is performed to provide a semiconductor substrate 200, a dummy gate 201 is formed on the surface of the substrate 200, an interlayer dielectric layer 204 is formed on the substrate, and the top of the interlayer dielectric layer 204 is connected to the The top of the dummy gate 201 is flat.
半导体衬底200材料可以是硅衬底、锗硅衬底、Ⅲ-Ⅴ族元素化合物衬底、碳化硅衬底或其叠层结构，或绝缘体上硅结构，或金刚石衬底，或本领域技术人员公知的其他半导体材料衬底。本实施例中，所述半导体衬底200为硅衬底，其中还形成有隔离结构，所述隔离结构可以是浅沟槽隔离结构，或本领域技术人员公知的其他用于器件隔离或有源区隔离的隔离结构。The material of the semiconductor substrate 200 may be a silicon substrate, a silicon germanium substrate, a III-V group element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or a diamond substrate, or a technology in the art Other semiconductor material substrates known to the person. In this embodiment, the semiconductor substrate 200 is a silicon substrate, and an isolation structure is formed therein, and the isolation structure may be a shallow trench isolation structure, or other devices known to those skilled in the art for device isolation or active Isolation structure for zone isolation.
在所述衬底200表面形成栅介质层和覆盖该栅介质层的伪栅极材料层，在伪栅极材料层上形成图形化的光刻胶，以图形化的光刻胶为模板，刻蚀伪栅极材料层和栅介质层，形成伪栅极201、位于衬底200和伪栅极201之间的栅介质层（图未示）。本实施例中，栅介质层为高k栅介质层。所述高k栅介质层的材料为HfO2、Al2O3、ZrO2、HfSiO、HfSiON、HfTaO和HfZrO。其他实施例中，栅介质层也可以为氧化硅层。Form a gate dielectric layer and a dummy gate material layer covering the gate dielectric layer on the surface of the substrate 200, form a patterned photoresist on the dummy gate material layer, use the patterned photoresist as a template, etch The dummy gate material layer and the gate dielectric layer are etched to form a dummy gate 201 and a gate dielectric layer (not shown) between the substrate 200 and the dummy gate 201 . In this embodiment, the gate dielectric layer is a high-k gate dielectric layer. The material of the high-k gate dielectric layer is HfO2 , Al2 O3 , ZrO2 , HfSiO, HfSiON, HfTaO and HfZrO. In other embodiments, the gate dielectric layer may also be a silicon oxide layer.
本实施例中，伪栅极201周围形成有侧墙202。侧墙202的材料可以为氧化硅、氮化硅或者氧化硅-氮化硅-氧化硅等多层材料。其他实施例中，伪栅极周围不形成侧墙，也属于本发明的保护范围。In this embodiment, spacers 202 are formed around the dummy gate 201 . The material of the sidewall 202 may be multilayer materials such as silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide. In other embodiments, no spacer is formed around the dummy gate, which also belongs to the protection scope of the present invention.
形成刻蚀停止层203，刻蚀停止层203覆盖衬底200表面和侧墙202侧壁。刻蚀停止层203的作用为：后续刻蚀形成源极导电插塞通孔或漏极导电插塞通孔时，一方面使得源极导电插塞通孔和漏极导电插塞通孔都停止在刻蚀停止层203上，刻蚀停止层203可以保护刻蚀停止层203下面的衬底200不受损伤，另一方面，源极导电插塞通孔和漏极导电插塞通孔都停止在刻蚀停止层203上，都不会对刻蚀停止层203形成过刻蚀，从而能够形成深度相同的源极导电插塞通孔或漏极导电插塞通孔。本实施例中，刻蚀停止层203的材料为氮化硅。形成刻蚀停止层的方法为沉积。其他实施例中，不形成刻蚀停止层，也属于本发明的保护范围。An etch stop layer 203 is formed, and the etch stop layer 203 covers the surface of the substrate 200 and the sidewalls of the sidewalls 202 . The function of the etching stop layer 203 is: when subsequent etching forms the source conductive plug via hole or the drain electrode conductive plug via hole, on the one hand, both the source conductive plug via hole and the drain electrode conductive plug via hole are stopped. On the etch stop layer 203, the etch stop layer 203 can protect the substrate 200 below the etch stop layer 203 from damage. On the other hand, the source conductive plug via hole and the drain electrode conductive plug via hole all stop On the etching stop layer 203 , the etching stop layer 203 will not be over-etched, so that the source conductive plug via hole or the drain electrode conductive plug via hole with the same depth can be formed. In this embodiment, the material of the etching stop layer 203 is silicon nitride. The method of forming the etch stop layer is deposition. In other embodiments, no etching stop layer is formed, which also belongs to the protection scope of the present invention.
本实施例中，形成层间介质材料层，覆盖刻蚀停止层203、侧墙202和伪栅极201。然后采用化学机械研磨或刻蚀的方法去除高于伪栅极201的层间介质材料层，形成层间介质层204。层间介质层204顶部与伪栅极201顶部相平。其中，形成层间介质材料层的方法为化学气相沉积或高纵深比填沟工艺（HARP,High Aspect Ratio Process）。In this embodiment, an interlayer dielectric material layer is formed to cover the etching stop layer 203 , the sidewall 202 and the dummy gate 201 . Then chemical mechanical grinding or etching is used to remove the interlayer dielectric material layer higher than the dummy gate 201 to form the interlayer dielectric layer 204 . The top of the interlayer dielectric layer 204 is even with the top of the dummy gate 201 . Wherein, the method of forming the interlayer dielectric material layer is chemical vapor deposition or high aspect ratio trench filling process (HARP, High Aspect Ratio Process).
接着，参考图6，执行步骤S12，利用外延生长形成至少覆盖所述伪栅极201顶部的第一牺牲层205。Next, referring to FIG. 6 , step S12 is performed to form a first sacrificial layer 205 covering at least the top of the dummy gate 201 by epitaxial growth.
本实施例中，第一牺牲层205的材料为多晶硅。第一牺牲层205不仅覆盖伪栅极201的顶部，还覆盖侧墙202顶部、刻蚀停止层203顶部和部分层间介质层204。所述外延生长为减压外延，具体形成工艺如下：硅源气体为硅烷或二氯二氢硅烷，外延压力为20～100Torr。当硅源气体为硅烷时，外延生长温度为600～950℃；当硅源气体为二氯二氢硅烷时，外延生长温度为1000～1100℃。其他实施例中，所述外延生长也可以为常压外延（压力为760Torr左右）生长或者选择性外延生长。In this embodiment, the material of the first sacrificial layer 205 is polysilicon. The first sacrificial layer 205 not only covers the top of the dummy gate 201 , but also covers the top of the spacer 202 , the top of the etching stop layer 203 and part of the interlayer dielectric layer 204 . The epitaxy growth is decompression epitaxy, and the specific formation process is as follows: the silicon source gas is silane or dichlorodihydrosilane, and the epitaxy pressure is 20-100 Torr. When the silicon source gas is silane, the epitaxial growth temperature is 600-950°C; when the silicon source gas is dichlorodihydrosilane, the epitaxial growth temperature is 1000-1100°C. In other embodiments, the epitaxial growth may also be normal pressure epitaxial growth (with a pressure of about 760 Torr) or selective epitaxial growth.
接着，参考图7，执行步骤S13，在层间介质层204上形成第二牺牲层206，所述第二牺牲层206顶部与所述第一牺牲层205顶部相平。Next, referring to FIG. 7 , step S13 is performed to form a second sacrificial layer 206 on the interlayer dielectric layer 204 , the top of the second sacrificial layer 206 is even with the top of the first sacrificial layer 205 .
本实施例中，第二牺牲层206的材料为非晶碳。其他实施例中，第二牺牲层206的材料也可以为第一聚合物或底部抗反射涂层（BARC，Bottom Anti-Reflective Coating）。所述第一聚合物包括碳元素或者氟、溴、氯元素中的一种或它们的任意组合。形成第二牺牲层206的方法具体为：采用沉积或者涂抹的方法形成第二牺牲材料层，所述第二牺牲材料层覆盖层间介质层204和第一牺牲层205。接着，采用刻蚀或者化学机械研磨或刻蚀的方法去除高于第一牺牲层205顶部的第二牺牲材料层，形成第二牺牲层206。第二牺牲层206顶部与第一牺牲层205顶部相平。In this embodiment, the material of the second sacrificial layer 206 is amorphous carbon. In other embodiments, the material of the second sacrificial layer 206 may also be the first polymer or Bottom Anti-Reflective Coating (BARC, Bottom Anti-Reflective Coating). The first polymer includes carbon or one of fluorine, bromine and chlorine or any combination thereof. The method for forming the second sacrificial layer 206 specifically includes: forming a second sacrificial material layer by depositing or coating, and the second sacrificial material layer covers the interlayer dielectric layer 204 and the first sacrificial layer 205 . Next, the second sacrificial material layer higher than the top of the first sacrificial layer 205 is removed by etching or chemical mechanical grinding or etching to form the second sacrificial layer 206 . The top of the second sacrificial layer 206 is even with the top of the first sacrificial layer 205 .
其中，当第二牺牲层206为第一聚合物时，形成第二牺牲材料层的具体工艺为：为沉积气体的流量为100sccm～1000sccm，沉积压强为3mTorr～30mTorr，激发功率为300W～1500W，偏置功率为2MHz～60MHz，处理时间为8s～60s。所述沉积气体包括碳元素和氟、溴、氯元素中的一种或它们的任意组合。Wherein, when the second sacrificial layer 206 is the first polymer, the specific process of forming the second sacrificial material layer is as follows: the flow rate of the deposition gas is 100sccm-1000sccm, the deposition pressure is 3mTorr-30mTorr, and the excitation power is 300W-1500W, The bias power is 2MHz~60MHz, and the processing time is 8s~60s. The deposition gas includes carbon and one of fluorine, bromine and chlorine or any combination thereof.
接着，参考图8，执行步骤S14，去除所述第一牺牲层205（参考图7），在所述第二牺牲层206内形成开口207，所述开口207底部露出所述伪栅极201顶部。Next, referring to FIG. 8 , step S14 is performed to remove the first sacrificial layer 205 (refer to FIG. 7 ), and form an opening 207 in the second sacrificial layer 206 , the bottom of the opening 207 exposes the top of the dummy gate 201 .
本实施例中，去除第一牺牲层205的方法为干法刻蚀或湿法腐蚀。其中干法刻蚀的具体工艺如下：刻蚀气体包括HBr和Cl2中的一种或两种，以O2作为稀释气体，其中刻蚀气体与稀释气体的比例为100:1～1:100。湿法腐蚀剂为浓度是10～50%四甲基氢氧化铵（TMAH）溶液，湿法腐蚀的温度为10～100℃。In this embodiment, the method for removing the first sacrificial layer 205 is dry etching or wet etching. The specific process of dry etching is as follows: the etching gas includes one or both of HBr and Cl2 , and O2 is used as the dilution gas, and the ratio of the etching gas to the dilution gas is 100:1 to 1:100 . The wet etching agent is a tetramethylammonium hydroxide (TMAH) solution with a concentration of 10-50%, and the wet etching temperature is 10-100°C.
本实施例中，由于第一牺牲层205不仅覆盖了伪栅极201的顶部，还覆盖侧墙202顶部、刻蚀停止层203顶部和部分层间介质层204，因此，去除第一牺牲层205后，开口207的底部还露出了侧墙202顶部、刻蚀停止层203顶部和部分层间介质层204。In this embodiment, since the first sacrificial layer 205 not only covers the top of the dummy gate 201, but also covers the top of the spacer 202, the top of the etching stop layer 203 and part of the interlayer dielectric layer 204, therefore, the first sacrificial layer 205 is removed Finally, the bottom of the opening 207 also exposes the top of the spacer 202 , the top of the etch stop layer 203 and part of the interlayer dielectric layer 204 .
需要说明的是，刻蚀第一牺牲层205时，虽然对开口207底部的伪栅极201顶部、侧墙202顶部、刻蚀停止层203顶部和露出的层间介质层204都会有略小的损伤，与现有技术相比，该略小的损伤可以忽略不计。It should be noted that, when etching the first sacrificial layer 205, although the top of the dummy gate 201 at the bottom of the opening 207, the top of the sidewall 202, the top of the etch stop layer 203 and the exposed interlayer dielectric layer 204 will all have a slightly smaller Damage, compared with the prior art, this slightly small damage is negligible.
接着，参考图9，在所述开口207的侧壁形成牺牲侧墙208。Next, referring to FIG. 9 , a sacrificial sidewall 208 is formed on the sidewall of the opening 207 .
本实施例中，牺牲侧墙208的材料为第二聚合物，由烃类气体制备。形成牺牲侧墙208的方法具体如下：在开口207的底部、侧壁和第二牺牲层206上沉积牺牲侧墙材料层，然后采用回刻的方法在开口207的侧壁形成牺牲侧墙208。相邻的两个牺牲侧墙208之间露出伪栅极201的顶部。采用化学式为CxHyFx的沉积气体沉积形成牺牲侧墙材料层，具体工艺如下：化学式为CH3F,CH2F2，C3HF3的沉积气体中的一种、两种或三种，沉积气体的总流量100～2000sccm。本实施例中，回刻形成牺牲侧墙208的激发功率100～2000W，偏置功率0～50W。In this embodiment, the material of the sacrificial sidewall 208 is the second polymer prepared from hydrocarbon gas. The method for forming the sacrificial sidewall 208 is as follows: deposit a sacrificial sidewall material layer on the bottom, sidewall and second sacrificial layer 206 of the opening 207 , and then form the sacrificial sidewall 208 on the sidewall of the opening 207 by etching back. The top of the dummy gate 201 is exposed between two adjacent sacrificial spacers 208 . The sacrificialsidewall material layeris formed by depositing a deposition gas with a chemical formula ofCxHyFx , and the specificprocess is as follows: one,two, or Three kinds, the total flow rate of the deposition gas is 100-2000 sccm. In this embodiment, the excitation power for etching back to form the sacrificial sidewall 208 is 100-2000W, and the bias power is 0-50W.
接着，参考图10，执行步骤S15，去除所述伪栅极201（参考图9），在所述层间介质层204内形成栅极凹槽209。Next, referring to FIG. 10 , step S15 is performed to remove the dummy gate 201 (refer to FIG. 9 ), and form a gate groove 209 in the interlayer dielectric layer 204 .
形成牺牲侧墙208后，以牺牲侧墙208为掩膜，去除伪栅极201。去除伪栅极201的方法为干法刻蚀或者是湿法腐蚀。属于本领域技术人员熟知工艺，在此不再赘述。去除伪栅极201的过程中，由于牺牲侧墙208和第二牺牲层206对层间介质层204、侧墙202和刻蚀停止层203的保护，使层间介质层204、侧墙202和刻蚀停止层203没有损伤，从而不会引起层间介质层204、侧墙202、刻蚀停止层203的高度下降，进而不会引起形成的栅极凹槽209的深度减小，保证了后续在栅极凹槽209内形成的金属栅极的高度。After the sacrificial spacer 208 is formed, the dummy gate 201 is removed by using the sacrificial spacer 208 as a mask. The method of removing the dummy gate 201 is dry etching or wet etching. It is a process well-known to those skilled in the art, and will not be repeated here. In the process of removing dummy gate 201, due to the protection of interlayer dielectric layer 204, sidewall 202 and etch stop layer 203 by sacrificial spacer 208 and second sacrificial layer 206, interlayer dielectric layer 204, sidewall 202 and The etch stop layer 203 is not damaged, so that the height of the interlayer dielectric layer 204, the sidewall 202, and the etch stop layer 203 will not be reduced, and the depth of the formed gate groove 209 will not be reduced, ensuring that the subsequent The height of the metal gate formed in the gate recess 209 .
需要说明的是：形成牺牲侧墙208与刻蚀去除伪栅极201的工艺是在同一个腔室进行的。之所以在同一个腔室进行，理由如下：（1）如果在第一反应腔室内形成牺牲侧墙208，在第二反应腔室进行刻蚀去除伪栅极201的工艺，那么将衬底移出第一反应腔室的过程中，衬底表面会在空气中发生氧化，不利于后续工艺的进行或者后续形成器件的性能不佳。（2）可以节省工艺步骤和工艺设备。It should be noted that the processes of forming the sacrificial spacer 208 and etching and removing the dummy gate 201 are performed in the same chamber. The reason why it is performed in the same chamber is as follows: (1) If the sacrificial sidewall 208 is formed in the first reaction chamber, and the process of etching and removing the dummy gate 201 is performed in the second reaction chamber, then the substrate is removed During the process in the first reaction chamber, the surface of the substrate will be oxidized in the air, which is not conducive to the progress of the subsequent process or the performance of the subsequently formed device is not good. (2) Process steps and process equipment can be saved.
需要再次说明的是：刻蚀去除伪栅极201的过程中，在牺牲侧墙208的外侧壁会覆盖刻蚀副产物，该刻蚀副产物也为第二聚合物，以便在刻蚀去除伪栅极201的过程中，牺牲侧墙208和刻蚀副产物可以更好的保护侧墙202顶部、刻蚀停止层203顶部和部分层间介质层204不受损伤。It needs to be explained again that during the process of etching and removing the dummy gate 201, the outer sidewall of the sacrificial spacer 208 will be covered with etching by-products, which are also the second polymer, so that the dummy gate 201 can be removed by etching. During the gate 201 process, the sacrificial spacer 208 and the etching by-products can better protect the top of the spacer 202 , the top of the etch stop layer 203 and part of the interlayer dielectric layer 204 from damage.
本实施例中，形成栅极凹槽209后，栅极凹槽209的底部会露出高k栅介质层。其他实施例中，如果栅介质层的材料为氧化硅，栅极凹槽209底部露出氧化硅栅介质层。In this embodiment, after the gate groove 209 is formed, the bottom of the gate groove 209 will expose the high-k gate dielectric layer. In other embodiments, if the material of the gate dielectric layer is silicon oxide, the gate dielectric layer of silicon oxide is exposed at the bottom of the gate groove 209 .
接着，参考图11，去除牺牲侧墙208（参考图10）。Next, referring to FIG. 11 , the sacrificial sidewall 208 (refer to FIG. 10 ) is removed.
本实施例中，去除牺牲侧墙208的方法为灰化或湿法腐蚀。In this embodiment, the method of removing the sacrificial sidewall 208 is ashing or wet etching.
需要说明的是：牺牲侧墙208的材料之所以不能使用氧化硅或氮化硅。是因为，后续去除牺牲侧墙208时，同样会将层间介质层204、侧墙202和刻蚀停止层203部分去除。It should be noted that silicon oxide or silicon nitride cannot be used as the material of the sacrificial sidewall 208 . This is because, when the sacrificial spacer 208 is subsequently removed, the interlayer dielectric layer 204 , the spacer 202 and the etch stop layer 203 will also be partially removed.
接着，继续参考图11和图12，执行步骤S16，去除第二牺牲层206，在所述栅极凹槽209内填充金属材料层210’形成金属栅极210。Next, continue referring to FIG. 11 and FIG. 12 , step S16 is performed, the second sacrificial layer 206 is removed, and the metal material layer 210' is filled in the gate groove 209 to form a metal gate 210 .
本实施例中，第二牺牲层206的材料为非晶碳时，可以采用灰化的方法去除。当第二牺牲层206的材料为第一聚合物时，可以采用灰化或湿法腐蚀的方法去除。所述湿法腐蚀剂为含氢氟酸溶液。In this embodiment, when the material of the second sacrificial layer 206 is amorphous carbon, it can be removed by ashing. When the material of the second sacrificial layer 206 is the first polymer, it can be removed by ashing or wet etching. The wet etching agent is a solution containing hydrofluoric acid.
本实施例中，为了节省工艺步骤，同时去除第二牺牲层206和牺牲侧墙208。其他实施例中也可以分步骤去除第二牺牲层206和牺牲侧墙208。In this embodiment, in order to save process steps, the second sacrificial layer 206 and the sacrificial sidewalls 208 are removed at the same time. In other embodiments, the second sacrificial layer 206 and the sacrificial sidewalls 208 may also be removed in steps.
在去除第二牺牲层206和牺牲侧墙208后，形成金属材料层，填充栅极凹槽209并且覆盖侧墙202顶部、刻蚀停止层203顶部和层间介质层204。然后，参考图12，去除高于层间介质层204顶部的金属材料层，形成金属栅极210。After removing the second sacrificial layer 206 and the sacrificial spacer 208 , a metal material layer is formed to fill the gate groove 209 and cover the top of the spacer 202 , the top of the etch stop layer 203 and the interlayer dielectric layer 204 . Then, referring to FIG. 12 , the metal material layer above the top of the interlayer dielectric layer 204 is removed to form a metal gate 210 .
在其他实施例中，如果栅极凹槽底部为氧化硅栅介质层，去除第二牺牲层和牺牲侧墙的步骤之后，形成金属材料层的步骤之前，需要去除氧化硅栅介质层，然后在栅极凹槽的底部和侧壁形成高k栅介质层。In other embodiments, if the bottom of the gate groove is a silicon oxide gate dielectric layer, after the step of removing the second sacrificial layer and the sacrificial sidewall, and before the step of forming the metal material layer, the silicon oxide gate dielectric layer needs to be removed, and then The bottom and sidewalls of the gate groove form a high-k gate dielectric layer.
本实施例中，外延生长形成的第一牺牲层不仅覆盖了伪栅极的顶部，还覆盖侧墙顶部、刻蚀停止层顶部和部分层间介质层。接着，在层间介质层上形成第二牺牲层，所述第二牺牲层顶部与所述第一牺牲层顶部相平。去除第一牺牲层后，在第二牺牲层内形成的开口底部不仅露出了伪栅极的顶部，还露出了侧墙顶部、刻蚀停止层顶部和部分层间介质层。因此，需要在开口的侧壁形成牺牲侧墙，相邻的两个牺牲侧墙之间只露出伪栅极。这样，刻蚀去除伪栅极的过程中，牺牲侧墙和第二牺牲层共同保护侧墙顶部、刻蚀停止层顶部和部分层间介质层不受损伤，因此，刻蚀去除伪栅极的过程中，不会引起层间介质层、侧墙和刻蚀停止层的高度下降。从而使形成的栅极凹槽的深度不会减小，保证了后续在栅极凹槽内形成的金属栅极的高度，提高了金属栅极的性能。In this embodiment, the first sacrificial layer formed by epitaxial growth not only covers the top of the dummy gate, but also covers the top of the spacer, the top of the etching stop layer and part of the interlayer dielectric layer. Next, a second sacrificial layer is formed on the interlayer dielectric layer, and the top of the second sacrificial layer is level with the top of the first sacrificial layer. After removing the first sacrificial layer, the bottom of the opening formed in the second sacrificial layer not only exposes the top of the dummy gate, but also exposes the top of the sidewall, the top of the etching stop layer and part of the interlayer dielectric layer. Therefore, sacrificial sidewalls need to be formed on the sidewalls of the opening, and only dummy gates are exposed between two adjacent sacrificial sidewalls. In this way, in the process of etching and removing the dummy gate, the sacrificial spacer and the second sacrificial layer jointly protect the top of the spacer, the top of the etch stop layer and part of the interlayer dielectric layer from damage, so the etching removes the dummy gate. During the process, the height of the interlayer dielectric layer, sidewall and etch stop layer will not be reduced. Therefore, the depth of the gate groove formed will not be reduced, which ensures the height of the metal gate subsequently formed in the gate groove, and improves the performance of the metal gate.
之所以采用外延生长的方法形成至少覆盖伪栅极顶部的第一牺牲层，理由如下：采用外延生长的方法形成第一牺牲层，第一牺牲层能够将伪栅极全部覆盖，而且，第一牺牲层的位置决定了第二牺牲层内的开口的位置，从而使得第二牺牲层和开口侧壁的牺牲侧墙能够准确的将伪栅极的顶部露出。进而能够准确的将伪栅极去除，同时，避免侧墙、刻蚀停止层和层间介质层受损伤。这个过程是自对准过程，在刻蚀去除伪栅极前，形成的第二牺牲层和牺牲侧墙能够精确的将伪栅极露出。The reason why the epitaxial growth method is used to form the first sacrificial layer covering at least the top of the dummy gate is as follows: the first sacrificial layer is formed by the epitaxial growth method, and the first sacrificial layer can completely cover the dummy gate, and the first The position of the sacrificial layer determines the position of the opening in the second sacrificial layer, so that the sacrificial sidewalls of the second sacrificial layer and the sidewalls of the opening can accurately expose the top of the dummy gate. Therefore, the dummy gate can be removed accurately, and at the same time, damage to the side wall, the etching stop layer and the interlayer dielectric layer can be avoided. This process is a self-alignment process, and before the dummy gate is etched away, the formed second sacrificial layer and sacrificial sidewalls can accurately expose the dummy gate.
而背景技术中的第二种尝试中提到：如果直接在层间介质层顶部形成图案化的光刻胶，理想情况下希望该图案化的光刻胶只露出伪栅极的顶部。然而，伪栅极的CD尺寸和光刻工艺的对准精度的限制，使得图案化的光刻胶无法准确的只露出伪栅极，同时也会或多或少的露出侧墙、刻蚀停止层和层间介质层中一种、两种或三种。因此，在刻蚀去除伪栅极的过程中，会使侧墙、刻蚀停止层和层间介质层受损。However, it is mentioned in the second attempt in the background art that if the patterned photoresist is directly formed on the top of the interlayer dielectric layer, it is ideally hoped that the patterned photoresist only exposes the top of the dummy gate. However, due to the limitations of the CD size of the dummy gate and the alignment accuracy of the photolithography process, the patterned photoresist cannot accurately expose only the dummy gate, and at the same time more or less expose the sidewall and stop the etching. One, two or three of layers and interlayer dielectric layers. Therefore, in the process of etching and removing the dummy gate, the sidewall, the etching stop layer and the interlayer dielectric layer will be damaged.
因此，采用本实施例的方法能够避免所述第二种尝试遇到的对准精度差的问题，采用自对准的方法可以很好的保护层间介质层、侧墙顶部和刻蚀停止层顶部在去除伪栅极的过程中不受损伤，从而使栅极凹槽的深度不会减小，进而使后续形成的金属栅极的高度不会减小。Therefore, the method of this embodiment can avoid the problem of poor alignment accuracy encountered in the second attempt, and the self-alignment method can well protect the interlayer dielectric layer, the top of the sidewall and the etch stop layer The top is not damaged during the process of removing the dummy gate, so that the depth of the gate groove will not be reduced, and thus the height of the subsequently formed metal gate will not be reduced.
其他实施例中，利用外延生长形成的第一牺牲层只覆盖伪栅极顶部和侧墙顶部也属于本发明的保护范围之内。In other embodiments, the first sacrificial layer formed by epitaxial growth only covers the top of the dummy gate and the top of the spacer wall, which also falls within the protection scope of the present invention.
其他实施例中，第一牺牲层只覆盖伪栅极顶部、侧墙顶部和刻蚀停止层顶部也属于本发明的保护范围之内。In other embodiments, the first sacrificial layer only covers the top of the dummy gate, the top of the sidewall and the top of the etch stop layer, which also falls within the protection scope of the present invention.
其他实施例中，第一牺牲层只覆盖伪栅极顶部，也属于本发明的保护范围之内。需要说明的是，去除第一牺牲层后，在第二牺牲层形成的开口底部只露出了伪栅极顶部，因此，不需要在第二牺牲层的开口侧壁形成牺牲侧墙的步骤。去除第一牺牲层后，可以直接去除伪栅极。接着去除第二牺牲层形成栅极凹槽。In other embodiments, the first sacrificial layer only covers the top of the dummy gate, which also falls within the protection scope of the present invention. It should be noted that after removing the first sacrificial layer, only the top of the dummy gate is exposed at the bottom of the opening formed in the second sacrificial layer, therefore, the step of forming sacrificial sidewalls on the sidewalls of the opening in the second sacrificial layer is unnecessary. After removing the first sacrificial layer, the dummy gate can be removed directly. Then the second sacrificial layer is removed to form a gate groove.
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310754250.XACN104752185B (en) | 2013-12-31 | 2013-12-31 | The forming method of metal gates |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310754250.XACN104752185B (en) | 2013-12-31 | 2013-12-31 | The forming method of metal gates |
| Publication Number | Publication Date |
|---|---|
| CN104752185A CN104752185A (en) | 2015-07-01 |
| CN104752185Btrue CN104752185B (en) | 2018-06-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310754250.XAActiveCN104752185B (en) | 2013-12-31 | 2013-12-31 | The forming method of metal gates |
| Country | Link |
|---|---|
| CN (1) | CN104752185B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161408A (en)* | 2015-09-22 | 2015-12-16 | 上海华力微电子有限公司 | Method for manufacturing high-K metal gate structure |
| CN109917503B (en)* | 2019-03-18 | 2021-04-23 | 京东方科技集团股份有限公司 | A grating device, its manufacturing method, and a display device |
| CN112951760B (en)* | 2019-11-26 | 2022-06-24 | 长鑫存储技术有限公司 | Memory and forming method thereof |
| CN112151386B (en)* | 2020-09-27 | 2023-01-06 | 中国科学院微电子研究所 | Stacked nanowire ring gate device and manufacturing method thereof |
| CN112141999B (en)* | 2020-09-27 | 2024-01-02 | 地球山(苏州)微电子科技有限公司 | Manufacturing method of MEMS device and MEMS device |
| CN114334654A (en)* | 2020-09-30 | 2022-04-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method of forming the same |
| CN114314499B (en)* | 2020-09-30 | 2025-08-05 | 中芯集成电路（宁波）有限公司 | Semiconductor device manufacturing method and electronic device |
| CN112670172A (en)* | 2020-12-29 | 2021-04-16 | 上海集成电路装备材料产业创新中心有限公司 | Preparation method of metal gate device |
| CN115332061B (en)* | 2022-10-13 | 2022-12-16 | 合肥晶合集成电路股份有限公司 | Manufacturing method of grid structure |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101203947A (en)* | 2005-06-21 | 2008-06-18 | 英特尔公司 | Complementary Metal-Oxide-Semiconductor Integrated Circuits Using Raised Source-Drain and Alternative Metal Gates |
| CN102737974A (en)* | 2011-04-12 | 2012-10-17 | 台湾积体电路制造股份有限公司 | Method of fabricating a plurality of gate structures |
| CN103035712A (en)* | 2011-10-09 | 2013-04-10 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN103187257A (en)* | 2011-12-29 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal grid electrode |
| CN103325826A (en)* | 2012-03-20 | 2013-09-25 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013120831A (en)* | 2011-12-07 | 2013-06-17 | Renesas Electronics Corp | Manufacturing method of semiconductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101203947A (en)* | 2005-06-21 | 2008-06-18 | 英特尔公司 | Complementary Metal-Oxide-Semiconductor Integrated Circuits Using Raised Source-Drain and Alternative Metal Gates |
| CN102737974A (en)* | 2011-04-12 | 2012-10-17 | 台湾积体电路制造股份有限公司 | Method of fabricating a plurality of gate structures |
| CN103035712A (en)* | 2011-10-09 | 2013-04-10 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN103187257A (en)* | 2011-12-29 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal grid electrode |
| CN103325826A (en)* | 2012-03-20 | 2013-09-25 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| Publication number | Publication date |
|---|---|
| CN104752185A (en) | 2015-07-01 |
| Publication | Publication Date | Title |
|---|---|---|
| CN104752185B (en) | The forming method of metal gates | |
| CN107799462B (en) | Method of forming a semiconductor structure | |
| CN107039272B (en) | Method for forming fin type transistor | |
| CN107346759B (en) | Semiconductor structure and manufacturing method thereof | |
| US10658489B2 (en) | Semiconductor structure and fabrication method thereof | |
| CN107785315B (en) | Method of forming a semiconductor structure | |
| CN107039335B (en) | Formation method of semiconductor structure | |
| CN111029302A (en) | Semiconductor device and method of forming the same | |
| CN104217954A (en) | Formation method of transistors | |
| JP4834304B2 (en) | Manufacturing method of semiconductor device | |
| CN113903808B (en) | Semiconductor structure and forming method thereof | |
| CN106952815A (en) | Method for forming fin transistors | |
| CN112151382B (en) | Semiconductor structure and forming method thereof | |
| CN105826364A (en) | Transistor and formation method thereof | |
| CN101339902A (en) | Method for manufacturing semiconductor high voltage device | |
| CN109003899A (en) | The forming method of semiconductor structure and forming method thereof, fin formula field effect transistor | |
| CN104701262B (en) | A kind of forming method of semiconductor devices | |
| TWI848502B (en) | Semiconductor device and method of forming the same | |
| CN103855074A (en) | Method for manufacturing semiconductor device | |
| CN107919287A (en) | The forming method of semiconductor devices | |
| CN113838934B (en) | Semiconductor structure and forming method thereof | |
| CN112928024B (en) | Semiconductor structures and methods of forming them | |
| CN105161414B (en) | The minimizing technology of gate hard mask layer | |
| CN112117192B (en) | Method for forming semiconductor structure | |
| CN111446286B (en) | Semiconductor structures and methods of forming them |
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |