Background technology
Internet of Things is considered as next " important productivity " for pushing world's high speed development, is another after relay communication networkOne tera-scale market.As perception center --- the sensor of Internet of Things, especially MEMS (miro-electro-Mechanical system, microelectromechanical systems) sensor has become the important layout field of major semiconductor company.
For MEMS sensor, in addition to design, the difficult point of manufacture, encapsulation is the another of MEMS sensor scale applicationOne difficult point.Due to the particularity of MEMS sensor working environment, many MEMS sensors are required for carrying out Vacuum Package, causeThe proportion that encapsulation overhead accounts for MEMS sensor chip cost is very high.
As the common encapsulation of other integrated circuit device, the Vacuum Package of MEMS sensor can also be divided into chip-scaleVacuum Package and wafer scale Vacuum Package.The step of chip-scale Vacuum Package includes mainly：By Wafer Dicing at singleBare chip；Bare chip is placed in bonding, routing, seam weld in encapsulating package；Helium leak test；It vacuumizes；Pin forming.
The main problem of above-mentioned this traditional MEMS sensor chip level vacuum encapsulating method is that chip needs one oneIt is packaged, is then vacuumized again.Also, since the period vacuumized is long, cause packaging cost higher.
Since wafer-level vacuum packaged can efficiently solve the cost control problem encountered in chip-scale Vacuum Package,Therefore, MEMS package industry has begun gradually to turn to wafer-level vacuum packaged.
~Fig. 2 is please referred to Fig.1, Fig. 1~Fig. 2 is the schematic diagram of traditional MEMS device wafers level vacuum encapsulating method.Such as Fig. 1It is shown, it is in the prior art, general brilliant using a block with 103 structure of groove to the wafer-level vacuum packaged of MEMS deviceCircle 104 is first aligned with the wafer to be wrapped 101 for having prepared MEMS device 102.Then, as shown in Fig. 2, under vacuum willBlock wafer 104 is bonded with wafer to be wrapped 101 downwards, and the package cavity of MEMS device 102 is made up of groove 103,Complete the wafer-level vacuum packaged to the MEMS device 102.And then independent packaged MEMS cores are formed by scribingPiece.
However, when carrying out wafer-level vacuum packaged to MEMS device using the above method, bonding apparatus is needed to have trueGood alignment ability under sky.This can increase the complexity and cost of bonding apparatus, finally can also improve the cost of MEMS chip.
Invention content
It is an object of the invention to overcome drawbacks described above of the existing technology, a kind of wafer-level vacuum packaged side is providedMethod, to solve the problems, such as to need bonding apparatus that there is good vacuum alignment ability in existing vacuum sealing technique, to reduction pairThe requirement of sealed in unit, the final cost for reducing MEMS chip Vacuum Package.
To achieve the above object, technical scheme is as follows：
A kind of wafer-level vacuum encapsulating method, including：
Step S01：One silicon chip substrate is provided, forms MEMS device over the substrate；
Step S02：Column material layer is enclosed in deposit over the substrate, encloses column material using described in photoetching, etching technics etchingLayer, to be correspondingly formed with cavity and the groove for enclosing column on the substrate around each MEMS device；The groove enclosesColumn is between the MEMS device and dicing lane；
Step S03：The cap material that one plane is provided, without being patterned to cap material, without under vacuumCap material and silicon substrate are strictly aligned, the cap material and the groove are enclosed to the upper end vacuum bonding of column,Wafer-level vacuum packaged is imposed to the MEMS device in the groove.
Preferably, the groove encloses the upper end of column higher than the MEMS device upper surface.
Preferably, the groove encloses the upper end of column higher than 5~30 microns of the MEMS device upper surface.
Preferably, in step S03, before carrying out vacuum bonding, the upper end that column is enclosed in the groove selectively deposits bondingSolder.
Preferably, the cap material is silicon chip, germanium wafer, potsherd, sheet metal or plastic sheet.
Preferably, in step S01, prepared by the cmos circuit for first completing the MEMS device over the substrate, then againThe MEMS device is formed over the substrate.
Preferably, in step S01 and S02, prepared by the structure for first completing to remain with the MEMS device of sacrificial layer, thenAfter forming the groove, release process is recycled to etch away the sacrificial layer of the MEMS device, forms hanging structure, finallyComplete the preparation of the MEMS device.
It can be seen from the above technical proposal that the present invention formed in the silicon chip substrate around MEMS device by elder generation it is recessedThen slot carries out vacuum bonding with cap material and groove again and completes wafer-level vacuum packaged, because without to cap material withSilicon chip substrate is strictly aligned, and is patterned without to cap material, to reduce the requirement of para-linkage equipment, togetherWhen also reduce the machinability requirement of cap material, therefore flexibility when significantly improving Vacuum Package, and can reducingThe cost of MEMS chip Vacuum Package.
Specific implementation mode
Below in conjunction with the accompanying drawings, the specific implementation mode of the present invention is described in further detail.
It should be noted that in following specific implementation modes, when embodiments of the present invention are described in detail, in order to clearGround indicates the structure of the present invention in order to illustrate, spy does not draw to the structure in attached drawing according to general proportion, and has carried out partAmplification, deformation and simplified processing, therefore, should avoid in this, as limitation of the invention to understand.
In specific implementation mode of the invention below, referring to Fig. 3, Fig. 3 is a kind of wafer-level vacuum packaged of the present inventionThe flow chart of method.Meanwhile Fig. 4~Fig. 9 is please referred to, Fig. 4~Fig. 9 is the method in a preferred embodiment of the present invention according to fig. 3Carry out the process structure schematic diagram of wafer-level vacuum packaged.As shown in figure 3, a kind of wafer-level vacuum encapsulating method of the present invention,Including：
As shown in frame 1, step S01：One silicon chip substrate is provided, forms MEMS device over the substrate.
Referring to Fig. 4, forming MEMS device 302 on the substrate 301.As a specific embodiment of the invention, can adoptUse such as one 8 inch silicon wafers 301 as silicon substrate.When making MEMS device 302 on silicon substrate 301, post- can be usedCMOS schemes are integrated, i.e., on silicon substrate 301 first complete with MEMS device it is relevant such as sense processing circuit, otherThe cmos circuits such as function IC prepare (not shown), then, then are further made on silicon substrate 301 and form MEMS device302, such as MEMS sensor.
As an optional embodiment of the invention, when making MEMS device 302, can complete complete to MEMS device 302The preparation of portion's process structure can also complete the preparation of 302 major part structure of MEMS device.In the present embodiment, it selects firstComplete the preparation method of 302 major part structure of MEMS device.For example, first being completed on 8 inch substrates silicon chips 301 relevantPrepared by cmos circuit, then, then further complete on silicon substrate 301 preparation of 302 major part structure of MEMS device, onlyRetain last release process step, i.e. MEMS device 302 remains subsequent step and handled again temporarily without hanging structure.
As shown in frame 2, step S02：It is correspondingly formed to have on the substrate around each MEMS device and encloses columnGroove.
Fig. 5 and Fig. 6 are please referred to, the method for forming groove includes：
As shown in figure 5, step S021：Column material layer 303 is enclosed in deposit on the substrate 301.
As shown in fig. 6, step S022：Column material layer 303 is enclosed using described in photoetching, etching technics etching, with each described302 surrounding of MEMS device forms the groove for having cavity 305 and enclosing column 304.
Please refer to Fig. 6.304 upper end of column of enclosing of the groove formed using the above method is higher than the MEMS device 302Upper surface, so as to subsequently use plane cap material be packaged.As a preferred embodiment, column material is enclosed by etchingThe groove is fabricated to and encloses height of the upper end of column 304 higher than 5~30 microns of 302 upper surface of the MEMS device by layer 303,Thinking the different cap materials that subsequently use, there are certain deformation spaces, and will not touch the upper surface of MEMS device 302.
Please continue to refer to Fig. 6.Meanwhile it is follow-up after packaging to MEMS chip progress scribing for convenience, described in formationWhen groove, it can make to enclose column 304 by etching and be located at the MEMS device 302 and dicing lane (figure omits, positioned at the centre of such as diagramTwo adjacent positions between enclosing column 304) between.It is located at the MEMS device 302 it is further preferred that can make to enclose column 304 and drawsThe centre of film channel.
In a specific embodiment of the invention, it can prepare and (retain most in above-mentioned 302 major part structure of completion MEMS deviceRelease process step afterwards) 8 inch substrates silicon chips 301 on deposit such as SiN, SiO successively2Layer, which is used as, encloses column material layer 303(please referring to Fig. 5).Wherein, the thickness of SiN layer can be 1000 angstroms, SiO2The thickness of layer can be 10 microns.Then, use is generalThang-kng is carved, etching technics is sequentially etched SiN layer and SiO2Layer 303, i.e., by SiN layer and SiO2Layer 303 is etched to MEMS device 302Surface leaves cavity 305 and by remaining SiN layer and SiO2The groove that layer is constituted encloses column 304, forms groove (please referring to Fig. 6).By etching technics, 304 top of column of enclosing of groove is made to be higher by 8 microns than 302 upper surface highest point of MEMS device.And then profitWith release process, the sacrificial layer of MEMS device 302 is etched away, forms MEMS hanging structures.For example, when sacrificial layer is silicon,Then using XeF2Release process removes sacrificial silicon layer, and is finally completed the preparation of MEMS device 302.
In a specific embodiment of the invention, the planar structure after groove is formed sees Fig. 7.By etching, can be formedSuch as diagram is around the groove structure with cavity 305 and rectangle column 304 of MEMS device 302.Two MEMS device 302It encloses and gives over to dicing lane between column 304.As optional embodiment, groove can also have round, polygon or other to be applicable inShape and structure, i.e., groove encloses column can form round, polygon or other applicable shapes around MEMS device, in embodimentNo longer enumerate.
As shown in frame 3, step S03：A cap material is provided, the upper end that the cap material is enclosed to column with the groove is trueDead key closes, and wafer-level vacuum packaged is imposed to the MEMS device in the groove.
Referring to Fig. 8, using a cap material 306, for the cap material 306 and the groove are enclosed column 304Upper end carries out vacuum bonding, and wafer-level vacuum packaged is carried out to the MEMS device 302 in the groove cavities 305.AsOne alternative embodiment, the cap material 306 can select silicon chip, germanium wafer, potsherd, sheet metal or plastic sheet.In order to ensureBonding effect before carrying out vacuum bonding, can deposit bonding solder with corresponding to bonding regioselectivity in the cap material 306307.The upper end that column 304 can also be enclosed in the groove selectively deposits bonding solder (figure omits).
In a specific embodiment of the invention, 8 inches of silicon chip 306 may be selected and be used as cap material, then, in block materialBonding solder 307 is deposited on material silicon chip 306 again.As an example, bonding solder 307 can select scolding tin (Sn), scolding tin 307Thickness is, for example, 5 microns.
Referring to Fig. 9, the cap material 306 for being deposited with bonding solder 307 and the groove are enclosed between the upper end of column 304It is sealed by vacuum bonding mode.In a specific embodiment of the invention, 8 inches of cap material silicon chips 306 can be putIt is placed on the objective table of bonding apparatus (figure omit), then, then 302 face of MEMS device of 8 inch substrates silicon chips 301 is inverted in lid306 top (opposite with the direction of diagram) of cap material silicon chip.Then, under vacuum conditions by cap material silicon chip 306 and substrateThe groove of silicon chip 301 is bonded.When bonding, heated under vacuum conditions, make on cap material silicon chip 306 (or grooveEnclose 304 upper end of column) bonding solder Sn307 fusing, be then cooled to solidify again, you can by cap material silicon chip 306 and liningBottom silicon chip 301 (i.e. groove encloses 304 upper end of column) is bonded together, and MEMS device 302 is made to be dissolved in cavity 305, realizes to MEMSThe wafer-level vacuum packaged of device 302.Finally, between enclosing column 304 there are dicing lane position, obtained by scribing packagedIndividual MEMS chip.
In conclusion in a kind of wafer-level vacuum encapsulating method provided by the invention, by being formed on silicon substrateThen groove carries out vacuum bonding with cap material and silicon substrate again and completes wafer-level vacuum packaged.Using the present invention, it is not necessarily toCap material is patterned so that cap material selection is more flexible；Meanwhile without under vacuum to cap material andSilicon substrate is strictly aligned, therefore reduces the requirement of para-linkage equipment, eventually reduces packaging cost.
Above-described to be merely a preferred embodiment of the present invention, the embodiment is not to be protected to limit the patent of the present inventionRange, therefore equivalent structure variation made by every specification and accompanying drawing content with the present invention are protected, similarly should be included inIn protection scope of the present invention.