技术领域technical field
本发明是有关于一种存储器控制方法，且特别是有关于可复写式非易失性存储器模块的存储器控制方法、存储器存储装置与存储器控制电路单元。The present invention relates to a memory control method, and in particular to a memory control method of a rewritable non-volatile memory module, a memory storage device and a memory control circuit unit.
背景技术Background technique
数码相机、移动电话与MP3播放器在这几年来的成长十分迅速，使得消费者对存储媒体的需求也急速增加。由于可复写式非易失性存储器模块（例如，快闪存储器）具有数据非易失性、省电、体积小，以及无机械结构等特性，所以非常适合内建于上述所举例的各种便携式多媒体装置中。Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (such as flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable devices such as the above examples. in the multimedia device.
一般来说，可复写式非易失性存储器模块是由一个存储器控制电路单元来控制。此存储器控制电路单元会提供时脉信号给可复写式非易失性存储器模块，藉此可复写式非易失性存储器模块会根据此时脉信号来运作。若时脉信号的频率越高，则可复写式非易失性存储器模块运作的速度会越快，但进行一些操作(例如，写入)时发生错误的机率也会提升，因而可能产生不可回复的错误。然而，若时脉信号的频率越低，则可复写式非易失性存储器模块执行这些操作的速度会降低。因此，如何在提升速度的情况下，又降低一些操作发生错误的机率，为此领域技术人员所关心的议题。Generally, the rewritable non-volatile memory module is controlled by a memory control circuit unit. The memory control circuit unit provides a clock signal to the rewritable non-volatile memory module, so that the rewritable non-volatile memory module operates according to the clock signal. If the frequency of the clock signal is higher, the operation speed of the rewritable non-volatile memory module will be faster, but the probability of errors during some operations (such as writing) will also increase, which may cause non-recovery mistake. However, if the frequency of the clock signal is lower, the speed at which the rewritable non-volatile memory module performs these operations will decrease. Therefore, how to reduce the probability of errors in some operations while increasing the speed is a topic of concern to those skilled in the art.
发明内容Contents of the invention
本发明提供一种存储器控制方法、存储器存储装置与存储器控制电路单元，可以提升可复写式非易失性存储器模块的操作速度，且可降低一些操作发生错误的机率。The invention provides a memory control method, a memory storage device and a memory control circuit unit, which can increase the operation speed of a rewritable non-volatile memory module and reduce the probability of some operation errors.
本发明一范例实施例提出一种存储器控制方法，用于一可复写式非易失性存储器模块。此方法包括：提供第一时脉信号给可复写式非易失性存储器模块，并根据第一时脉信号读取可复写式非易失性存储器模块中的第一数据；提供第二时脉信号给可复写式非易失性存储器模块，并根据第二时脉信号将第二数据写入至可复写式非易失性存储器模块中。其中第二时脉信号的频率不同于第一时脉信号的频率。An exemplary embodiment of the present invention provides a memory control method for a rewritable non-volatile memory module. The method includes: providing a first clock signal to the rewritable non-volatile memory module, and reading the first data in the rewritable non-volatile memory module according to the first clock signal; providing a second clock The signal is sent to the rewritable non-volatile memory module, and the second data is written into the rewritable non-volatile memory module according to the second clock signal. Wherein the frequency of the second clock signal is different from the frequency of the first clock signal.
在一范例实施例中，上述第二时脉信号的频率小于第一时脉信号的频率。In an exemplary embodiment, the frequency of the second clock signal is lower than the frequency of the first clock signal.
在一范例实施例中，上述的存储器控制方法还包括：接收来自主机系统的第一指令；若第一指令为读取指令，执行所述提供第一时脉信号的步骤；以及若第一指令为写入指令，执行所述提供第二时脉信号的步骤。In an exemplary embodiment, the above memory control method further includes: receiving a first command from the host system; if the first command is a read command, performing the step of providing the first clock signal; and if the first command For writing commands, the step of providing the second clock signal is performed.
在一范例实施例中，上述的可复写式非易失性存储器模块包括多个实体抹除单元。这些实体抹除单元至少被分为数据区与系统区，上述的第一数据是存储于数据区。此存储器控制方法还包括：提供第二时脉信号给可复写式非易失性存储器模块，并根据第二时脉信号读取系统区中的第三数据。In an exemplary embodiment, the above-mentioned rewritable non-volatile memory module includes a plurality of physical erasing units. These physical erasing units are at least divided into a data area and a system area, and the above-mentioned first data is stored in the data area. The memory control method further includes: providing a second clock signal to the rewritable non-volatile memory module, and reading third data in the system area according to the second clock signal.
在一范例实施例中，上述的存储器控制方法还包括：根据一错误更正码或一错误检查码判断第一数据是否有错误，并且判断一读取错误次数是否符合临界条件；若第一数据有错误且读取错误次数不符合临界条件，根据第一时脉信号重新读取第一数据并且更新读取错误次数；若第一数据有错误且读取错误次数符合临界条件，提供第二时脉信号给可复写式非易失性存储器模块，并且根据第二时脉信号读取第一数据。In an exemplary embodiment, the above-mentioned memory control method further includes: judging whether the first data has an error according to an error correction code or an error checking code, and judging whether a reading error count meets a critical condition; if the first data has Error and the number of read errors does not meet the critical condition, re-read the first data according to the first clock signal and update the number of read errors; if the first data has errors and the number of read errors meets the critical condition, provide the second clock The signal is sent to the rewritable non-volatile memory module, and the first data is read according to the second clock signal.
在一范例实施例中，上述根据错误更正码或错误检查码判断第一数据是否有错误的步骤包括：根据错误更正码判断第一数据是否有错误；以及若根据错误更正码判断第一数据没有错误，根据错误检查码来判断第一数据是否有错误。In an exemplary embodiment, the step of judging whether the first data has an error according to the error correction code or the error check code includes: judging whether the first data has an error according to the error correction code; Error, judging whether the first data has an error according to the error check code.
在一范例实施例中，上述可复写式非易失性存储器模块是电性连接至多个通道。上述的存储器控制方法还包括：对于每一个通道，记录对应的读取错误次数。In an exemplary embodiment, the above-mentioned rewritable non-volatile memory module is electrically connected to a plurality of channels. The above memory control method further includes: for each channel, recording the corresponding number of reading errors.
本发明一范例实施例提出一种存储器存储装置，包括连接接口单元、上述的可复写式非易失性存储器模块、与存储器控制电路单元。连接接口单元是用以电性连接至主机系统。存储器控制电路单元是电性连接至连接接口单元与可复写式非易失性存储器模块，用以提供第一时脉信号给可复写式非易失性存储器模块，并根据第一时脉信号读取可复写式非易失性存储器模块中的第一数据。存储器控制电路单元也用以提供第二时脉信号给可复写式非易失性存储器模块，并根据第二时脉信号将第二数据写入至可复写式非易失性存储器模块中。第二时脉信号的频率不同于第一时脉信号的频率。An exemplary embodiment of the present invention provides a memory storage device, including a connection interface unit, the above-mentioned rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module, and is used to provide the first clock signal to the rewritable non-volatile memory module, and read the memory module according to the first clock signal. The first data in the rewritable non-volatile memory module is fetched. The memory control circuit unit is also used for providing a second clock signal to the rewritable non-volatile memory module, and writing second data into the rewritable non-volatile memory module according to the second clock signal. The frequency of the second clock signal is different from that of the first clock signal.
在一范例实施例中，上述的存储器控制电路单元还用以接收来自主机系统的第一指令。若第一指令为读取指令，存储器控制电路单元用以提供第一时脉信号。若第一指令为写入指令，存储器控制电路单元用以提供第二时脉信号。In an exemplary embodiment, the above-mentioned memory control circuit unit is further configured to receive a first command from a host system. If the first command is a read command, the memory control circuit unit is used for providing a first clock signal. If the first command is a write command, the memory control circuit unit is used for providing a second clock signal.
在一范例实施例中，上述的实体抹除单元至少被分为数据区与系统区，并且第一数据是存储于数据区。存储器控制电路单元还用以提供第二时脉信号给可复写式非易失性存储器模块，并根据第二时脉信号读取系统区中的第三数据。In an exemplary embodiment, the above-mentioned physical erasing unit is at least divided into a data area and a system area, and the first data is stored in the data area. The memory control circuit unit is also used for providing a second clock signal to the rewritable non-volatile memory module, and reading third data in the system area according to the second clock signal.
在一范例实施例中，上述的存储器控制电路单元还用以根据错误更正码或错误检查码判断第一数据是否有错误，并且判断一读取错误次数是否符合临界条件。若第一数据有错误且读取错误次数不符合临界条件，存储器控制电路单元用以根据第一时脉信号重新读取第一数据并且更新读取错误次数。若第一数据有错误且读取错误次数符合临界条件，存储器控制电路单元用以提供第二时脉信号给可复写式非易失性存储器模块，并且根据第二时脉信号读取第一数据。In an exemplary embodiment, the above-mentioned memory control circuit unit is further configured to determine whether the first data has an error according to the error correction code or the error check code, and determine whether a read error count meets a critical condition. If the first data has an error and the number of read errors does not meet the critical condition, the memory control circuit unit is used to re-read the first data according to the first clock signal and update the number of read errors. If the first data has an error and the number of read errors meets a critical condition, the memory control circuit unit is used to provide a second clock signal to the rewritable non-volatile memory module, and read the first data according to the second clock signal .
在一范例实施例中，上述存储器控制电路单元根据错误更正码或错误检查码判断第一数据是否有错误的操作包括以下操作。存储器控制电路单元根据错误更正码判断第一数据是否有错误。若根据错误更正码判断第一数据没有错误，存储器控制电路单元根据错误检查码来判断第一数据是否有错误。In an exemplary embodiment, the operation of the memory control circuit unit determining whether the first data has an error according to the error correction code or the error check code includes the following operations. The memory control circuit unit judges whether there is an error in the first data according to the error correction code. If it is judged according to the error correction code that the first data has no error, the memory control circuit unit judges whether the first data has an error according to the error check code.
在一范例实施例中，上述的可复写式非易失性存储器模块是通过多个通道电性连接至存储器控制电路单元。存储器控制电路单元还用以对于每一个通道，记录对应的读取错误次数。In an exemplary embodiment, the above-mentioned rewritable non-volatile memory module is electrically connected to the memory control circuit unit through a plurality of channels. The memory control circuit unit is also used for recording the corresponding number of read errors for each channel.
本发明一范例实施例提出一种存储器控制电路单元，用于控制上述的可复写式非易失性存储器模块。此存储器控制电路单元包括主机接口、存储器接口、存储器管理电路与时脉产生电路。主机接口是用以电性连接至主机系统。存储器接口是用以电性连接至可复写式非易失性存储器模块。存储器管理电路是电性连接至主机接口与存储器接口。时脉产生电路是用以提供第一时脉信号或第二时脉信号给可复写式非易失性存储器模块。存储器管理电路用以根据第一时脉信号读取可复写式非易失性存储器模块中的第一数据。存储器管理电路也用以根据第二时脉信号将第二数据写入至可复写式非易失性存储器模块中。其中第二时脉信号的频率不同于第一时脉信号的频率。An exemplary embodiment of the present invention provides a memory control circuit unit for controlling the above-mentioned rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, a memory management circuit and a clock generation circuit. The host interface is used to electrically connect to the host system. The memory interface is used to electrically connect to the rewritable non-volatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The clock generating circuit is used to provide the first clock signal or the second clock signal to the rewritable non-volatile memory module. The memory management circuit is used for reading the first data in the rewritable non-volatile memory module according to the first clock signal. The memory management circuit is also used for writing the second data into the rewritable non-volatile memory module according to the second clock signal. Wherein the frequency of the second clock signal is different from the frequency of the first clock signal.
在一范例实施例中，上述的存储器管理电路还用以接收来自主机系统的第一指令。若第一指令为读取指令，时脉产生电路用以提供第一时脉信号。若第一指令为写入指令，时脉产生电路用以提供第二时脉信号。In an exemplary embodiment, the above-mentioned memory management circuit is further configured to receive a first command from the host system. If the first command is a read command, the clock generating circuit is used for providing a first clock signal. If the first command is a write command, the clock generating circuit is used to provide a second clock signal.
在一范例实施例中，上述的实体抹除单元至少被分为数据区与系统区，并且第一数据是存储于数据区。存储器管理电路还用以根据第二时脉信号读取系统区中的第三数据。In an exemplary embodiment, the above-mentioned physical erasing unit is at least divided into a data area and a system area, and the first data is stored in the data area. The memory management circuit is also used for reading third data in the system area according to the second clock signal.
在一范例实施例中，上述的存储器管理电路还用以根据错误更正码或错误检查码判断第一数据是否有错误，并且判断一读取错误次数是否符合临界条件。若第一数据有错误且读取错误次数不符合临界条件，存储器管理电路用以根据第一时脉信号重新读取第一数据并且更新读取错误次数。若第一数据有错误且读取错误次数符合临界条件，存储器管理电路用以根据第二时脉信号读取第一数据。In an exemplary embodiment, the above-mentioned memory management circuit is further used for judging whether the first data has an error according to the error correction code or the error check code, and judging whether a read error count meets a critical condition. If the first data has an error and the number of read errors does not meet the critical condition, the memory management circuit is used to re-read the first data according to the first clock signal and update the number of read errors. If the first data has errors and the number of reading errors meets the critical condition, the memory management circuit is used to read the first data according to the second clock signal.
在一范例实施例中，上述的存储器管理电路根据错误更正码或错误检查码判断第一数据是否有错误的操作包括以下操作。存储器管理电路根据错误更正码判断第一数据是否有错误。若根据错误更正码判断第一数据没有错误，存储器管理电路根据错误检查码来判断第一数据是否有错误。In an exemplary embodiment, the operation of the memory management circuit determining whether the first data has an error according to the error correction code or the error check code includes the following operations. The memory management circuit judges whether there is an error in the first data according to the error correction code. If it is judged according to the error correction code that the first data has no error, the memory management circuit judges whether the first data has an error according to the error check code.
在一范例实施例中，上述的可复写式非易失性存储器模块是通过多个通道电性连接至存储器控制电路单元。存储器管理电路还用以对于每一个通道，记录对应的读取错误次数。In an exemplary embodiment, the above-mentioned rewritable non-volatile memory module is electrically connected to the memory control circuit unit through a plurality of channels. The memory management circuit is also used for recording the corresponding number of read errors for each channel.
本发明一范例实施例提出一种存储器控制方法，用于可复写式非易失性存储器模块。可复写式非易失性存储器模块中的实体程序化单元被分为数据区、闲置区与系统区。此存储器控制方法包括：提供第一时脉信号给可复写式非易失性存储器模块，并应用第一时脉信号对可复写式非易失性存储器模块的数据区或闲置区执行第一操作。提供第二时脉信号给可复写式非易失性存储器模块，并应用第二时脉信号对可复写式非易失性存储器模块的数据区或闲置区执行第二操作。其中第一时脉信号的频率不同于第二时脉信号的频率。An exemplary embodiment of the present invention provides a memory control method for a rewritable non-volatile memory module. The physical programming unit in the rewritable non-volatile memory module is divided into a data area, an idle area and a system area. The memory control method includes: providing a first clock signal to the rewritable non-volatile memory module, and applying the first clock signal to perform a first operation on the data area or idle area of the rewritable non-volatile memory module . The second clock signal is provided to the rewritable non-volatile memory module, and the second operation is performed on the data area or the idle area of the rewritable non-volatile memory module by using the second clock signal. The frequency of the first clock signal is different from the frequency of the second clock signal.
在一范例实施例中，上述第二时脉信号的频率小于第一时脉信号的频率，第一操作为读取操作，并且第二操作为写入操作。In an exemplary embodiment, the frequency of the second clock signal is lower than the frequency of the first clock signal, the first operation is a read operation, and the second operation is a write operation.
在一范例实施例中，上述第二时脉信号的频率小于第一时脉信号的频率，第一操作是用以读取使用者数据，第二操作是用以读取实体地址映射表。In an exemplary embodiment, the frequency of the second clock signal is lower than the frequency of the first clock signal, the first operation is used to read user data, and the second operation is used to read the physical address mapping table.
在一范例实施例中，上述第二时脉信号的频率小于第一时脉信号的频率，第一操作是用以读取第一数据，并且第二操作是用以在第一数据有错误时重读第一数据。In an exemplary embodiment, the frequency of the second clock signal is lower than the frequency of the first clock signal, the first operation is used to read the first data, and the second operation is used when the first data has an error Reread the first data.
在一范例实施例中，可复写式非易失性存储器模块的系统数据非存储于数据区或闲置区，且系统区中的实体程序化单元无映射至存储器存储装置的实体地址映射表中的逻辑地址。In an exemplary embodiment, the system data of the rewritable non-volatile memory module is not stored in the data area or idle area, and the physical programming unit in the system area is not mapped to the physical address mapping table of the memory storage device. logical address.
本发明一范例实施例提出一种存储器存储装置，包括连接接口单元、上述的可复写式非易失性存储器模块与存储器控制电路单元。连接接口单元是用以电性连接至主机系统。存储器控制电路单元是电性连接至连接接口单元与可复写式非易失性存储器模块，用以提供第一时脉信号给可复写式非易失性存储器模块，并应用第一时脉信号对可复写式非易失性存储器模块的数据区或闲置区执行第一操作。存储器控制电路单元也用以提供第二时脉信号给可复写式非易失性存储器模块，并应用第二时脉信号对可复写式非易失性存储器模块的数据区或闲置区执行第二操作。其中第一时脉信号的频率不同于第二时脉信号的频率。An exemplary embodiment of the present invention provides a memory storage device, including a connection interface unit, the above-mentioned rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to electrically connect to the host system. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module to provide the first clock signal to the rewritable non-volatile memory module, and apply the first clock signal to the rewritable non-volatile memory module. The data area or idle area of the rewritable non-volatile memory module performs the first operation. The memory control circuit unit is also used to provide the second clock signal to the rewritable non-volatile memory module, and apply the second clock signal to execute the second operate. The frequency of the first clock signal is different from the frequency of the second clock signal.
基于上述，本发明范例实施例提出的存储器控制方法、存储器存储装置与存储器控制电路单元，可以提供不同频率的时脉信号给可复写式非易失性存储器模块。藉此，在一些情况下可以提升可复写式非易失性存储器模块的操作速度，而在另一些情况下可以降低操作发生错误的机率。Based on the above, the memory control method, memory storage device and memory control circuit unit proposed by the exemplary embodiments of the present invention can provide clock signals of different frequencies to the rewritable non-volatile memory module. Thereby, the operation speed of the rewritable non-volatile memory module can be improved in some cases, and the probability of operation errors can be reduced in other cases.
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所示附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
附图说明Description of drawings
图1A是根据一范例实施例所示出的主机系统与存储器存储装置；FIG. 1A shows a host system and a memory storage device according to an exemplary embodiment;
图1B是根据一范例实施例所示出的电脑、输入/输出装置与存储器存储装置的示意图；FIG. 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment;
图1C是根据一范例实施例所示出的主机系统与存储器存储装置的示意图；FIG. 1C is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment;
图2示出图1A所示的存储器存储装置的概要示意图；FIG. 2 shows a schematic diagram of the memory storage device shown in FIG. 1A;
图3是根据一范例实施例所示出存储器控制电路单元的概要示意图；FIG. 3 is a schematic diagram illustrating a memory control circuit unit according to an exemplary embodiment;
图4是根据一范例实施例所示出管理可复写式非易失性存储器模块的范例示意图；FIG. 4 is an example schematic diagram showing management of a rewritable non-volatile memory module according to an example embodiment;
图5是根据一范例实施例示出判断使用第一时脉信号或第二时脉信号的流程图。FIG. 5 is a flowchart illustrating determining whether to use the first clock signal or the second clock signal according to an exemplary embodiment.
附图标记说明：Explanation of reference signs:
1000：主机系统；1000: host system;
1100：电脑；1100: computer;
1102：微处理器；1102: microprocessor;
1104：随机存取存储器；1104: random access memory;
1106：输入/输出装置；1106: input/output device;
1108：系统串行总线；1108: system serial bus;
1110：数据传输接口；1110: data transmission interface;
1202：鼠标；1202: mouse;
1204：键盘；1204: keyboard;
1206：显示器；1206: display;
1208：打印机；1208: printer;
1212：随身盘；1212: pen drive;
1214：存储卡；1214: memory card;
1216：固态硬盘；1216: SSD;
1310：数码相机；1310: digital camera;
1312：SD卡；1312: SD card;
1314：MMC卡；1314: MMC card;
1316：记忆棒；1316: memory stick;
1318：CF卡；1318: CF card;
1320：嵌入式存储装置；1320: embedded storage device;
100：存储器存储装置；100: memory storage device;
102：连接接口单元；102: connect the interface unit;
104：存储器控制电路单元；104: memory control circuit unit;
106：可复写式非易失性存储器模块；106: a rewritable non-volatile memory module;
304(0)～304(R)：实体抹除单元；304(0)～304(R): Entity erasing unit;
202：存储器管理电路；202: memory management circuit;
204：主机接口；204: host interface;
206：存储器接口；206: memory interface;
252：缓冲存储器；252: buffer memory;
254：电源管理电路；254: power management circuit;
256：错误检查与校正电路；256: error checking and correction circuit;
258：时脉产生电路；258: Clock generating circuit;
402：数据区；402: data area;
404：闲置区；404: idle area;
406：系统区；406: system area;
410(0)～410(D)：逻辑地址；410(0)～410(D): logical address;
S501～S505：步骤。S501-S505: steps.
具体实施方式Detailed ways
[第一范例实施例][First Exemplary Embodiment]
一般而言，存储器存储装置(也称，存储器存储系统)包括可复写式非易失性存储器模块与控制器(也称，控制电路)。通常存储器存储装置是与主机系统一起使用，以使主机系统可将数据写入至存储器存储装置或从存储器存储装置中读取数据。Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.
图1A是根据一范例实施例所示出的主机系统与存储器存储装置。图1B是根据一范例实施例所示出的电脑、输入/输出装置与存储器存储装置的示意图。图1C是根据一范例实施例所示出的主机系统与存储器存储装置的示意图。FIG. 1A shows a host system and a memory storage device according to an exemplary embodiment. FIG. 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment. FIG. 1C is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment.
请参照图1A，主机系统1000一般包括电脑1100与输入/输出(input/output,简称：I/O)装置1106。电脑1100包括微处理器1102、随机存取存储器(randomaccess memory,简称：RAM)1104、系统串行总线1108与数据传输接口1110。输入/输出装置1106包括如图1B的鼠标1202、键盘1204、显示器1206与打印机1208。必须了解的是，图1B所示的装置非限制输入/输出装置1106，输入/输出装置1106可还包括其他装置。Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (input/output, I/O for short) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM for short) 1104 , a system serial bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.
在本发明实施例中，存储器存储装置100是通过数据传输接口1110与主机系统1000的其他元件电性连接。通过微处理器1102、随机存取存储器1104与输入/输出装置1106的运作可将数据写入至存储器存储装置100或从存储器存储装置100中读取数据。例如，存储器存储装置100可以是如图1B所示的随身盘1212、存储卡1214或固态硬盘(Solid State Drive,简称：SSD)1216等的可复写式非易失性存储器存储装置。In the embodiment of the present invention, the memory storage device 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into or read from the memory storage device 100 through the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a flash drive 1212, a memory card 1214, or a solid state drive (Solid State Drive, referred to as: SSD) 1216 as shown in FIG. 1B.
一般而言，主机系统1000为可实质地与存储器存储装置100配合以存储数据的任意系统。虽然在本范例实施例中，主机系统1000是以电脑系统来作说明，然而，在本发明另一范例实施例中主机系统1000可以是数码相机、摄像机、通信装置、音频播放器或视频播放器等系统。例如，在主机系统为数码相机(摄像机)1310时，可复写式非易失性存储器存储装置则为其所使用的SD卡1312、MMC卡1314、记忆棒(memory stick)1316、CF卡1318或嵌入式存储装置1320(如图1C所示)。嵌入式存储装置1320包括嵌入式多媒体卡(Embedded MMC,简称：eMMC)。值得一提的是，嵌入式多媒体卡是直接电性连接于主机系统的基板上。In general, host system 1000 is any system that can cooperate substantially with memory storage device 100 to store data. Although in this exemplary embodiment, the host system 1000 is described as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the rewritable non-volatile memory storage device is an SD card 1312, an MMC card 1314, a memory stick (memory stick) 1316, a CF card 1318 or The embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC for short). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.
图2示出图1A所示的存储器存储装置的概要示意图。FIG. 2 shows a schematic diagram of the memory storage device shown in FIG. 1A .
请参照图2，存储器存储装置100包括连接接口单元102、存储器控制电路单元104与可复写式非易失性存储器模块106。Referring to FIG. 2 , the memory storage device 100 includes a connection interface unit 102 , a memory control circuit unit 104 and a rewritable non-volatile memory module 106 .
在本范例实施例中，连接接口单元102是串行高级技术附件(SerialAdvanced Technology Attachment,简称：SATA)标准。然而，必须了解的是，本发明不限于此，连接接口单元102也可以是符合并行高级技术附件(ParallelAdvanced Technology Attachment,简称：PATA)标准、电气和电子工程师学会(Institute of Electrical and Electronic Engineers,简称：IEEE)1394标准、高速外设互联接口(Peripheral Component Interconnect Express,简称：PCI Express)标准、通用串行总线(Universal Serial Bus,简称：USB)标准、安全数码(SecureDigital,简称：SD)接口标准、超高速一代(Ultra High Speed-I，简称：UHS-I)接口标准、超高速二代(Ultra High Speed-II，简称：UHS-II)接口标准、记忆棒(Memory Stick,简称：MS)接口标准、多媒体存储卡(Multi Media Card,简称：MMC)接口标准、崁入式多媒体存储卡(Embedded Multimedia Card，简称：eMMC)接口标准、通用快闪存储器(Universal Flash Storage，简称：UFS)接口标准、小型快闪(Compact Flash,简称：CF)接口标准、电子集成驱动器接口(Integrated Device Electronics,简称：IDE)标准或其他适合的标准。连接接口单元102可与存储器控制电路单元104封装在一个芯片中，或者连接接口单元102是布设于一包含存储器控制电路单元104芯片外。In this exemplary embodiment, the connection interface unit 102 is a Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA for short) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 102 may also be in compliance with the Parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, referred to as: PATA) standard, Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, referred to as : IEEE) 1394 standard, high-speed peripheral interconnection interface (Peripheral Component Interconnect Express, referred to as: PCI Express) standard, Universal Serial Bus (Universal Serial Bus, referred to as: USB) standard, secure digital (SecureDigital, referred to as: SD) interface standard , Ultra High Speed-I (abbreviation: UHS-I) interface standard, Ultra High Speed-II (abbreviation: UHS-II) interface standard, Memory Stick (Memory Stick, abbreviation: MS) Interface standard, Multi Media Card (Multi Media Card, MMC for short) interface standard, Embedded Multimedia Card (eMMC for short) interface standard, Universal Flash Storage (UFS for short) interface Standard, Compact Flash (CF for short) interface standard, Integrated Device Electronics (IDE for short) standard, or other suitable standards. The connection interface unit 102 can be packaged with the memory control circuit unit 104 in one chip, or the connection interface unit 102 can be arranged outside a chip including the memory control circuit unit 104 .
存储器控制电路单元104用以执行以硬件形式或固件形式实作的多个逻辑门或控制指令，并且根据主机系统1000的指令在可复写式非易失性存储器模块106中进行数据的写入、读取与抹除等运作。The memory control circuit unit 104 is used to execute a plurality of logic gates or control instructions implemented in the form of hardware or firmware, and write data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000, Operations such as reading and erasing.
可复写式非易失性存储器模块106是电性连接至存储器控制电路单元104，并且用以存储主机系统1000所写入的数据。可复写式非易失性存储器模块106具有实体抹除单元304(0)～304(R)。例如，实体抹除单元304(0)～304(R)可属于同一个存储器晶粒(die)或者属于不同的存储器晶粒。每一实体抹除单元分别具有复数个实体程序化单元，并且属于同一个实体抹除单元的实体程序化单元可被独立地写入且被同时地抹除。例如，每一实体抹除单元是由128个实体程序化单元所组成。然而，必须了解的是，本发明不限于此，每一实体抹除单元是可由64个实体程序化单元、256个实体程序化单元或其他任意个实体程序化单元所组成。The rewritable non-volatile memory module 106 is electrically connected to the memory control circuit unit 104 and used for storing data written by the host system 1000 . The rewritable non-volatile memory module 106 has physical erasing units 304 ( 0 )˜ 304 (R). For example, the physical erasing units 304(0)˜304(R) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has a plurality of physical programming units, and the physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. For example, each physical erasing unit is composed of 128 physical programming units. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.
更具体来说，每一个实体抹除单元包括多条字元线与多条比特线，每一条字元线与每一比特线交叉处配置有一个记忆胞。每一个记忆胞可存储一或多个比特。在同一个实体抹除单元中，所有的记忆胞会一起被抹除。在此范例实施例中，实体抹除单元为抹除的最小单位。亦即，每一实体抹除单元含有最小数目之一并被抹除的记忆胞。例如，实体抹除单元为实体区块。另一方面，同一个字元线上的记忆胞会组成一或多个实体程序化单元。若每一个记忆胞可存储2个以上的比特，则同一个字元线上的实体程序化单元可被分类为下实体程序化单元与上实体程序化单元。一般来说，下实体程序化单元的写入速度会大于上实体程序化单元的写入速度。在此范例实施例中，实体程序化单元为程序化的最小单元。即，实体程序化单元为写入数据的最小单元。例如，实体程序化单元为实体页面或是实体扇(sector)。若实体程序化单元为实体页面，则每一个实体程序化单元通常包括数据比特区与冗余比特区。数据比特区包含多个实体扇，用以存储使用者的数据，而冗余比特区用以存储系统的数据（例如，错误更正码）。在本范例实施例中，每一个数据比特区包含32个实体扇，且一个实体扇的大小为512字节(byte,B)。然而，在其他范例实施例中，数据比特区中也可包含8个、16个或数目更多或更少的实体扇，本发明并不限制实体扇的大小以及个数。More specifically, each physical erasing unit includes multiple word lines and multiple bit lines, and a memory cell is arranged at the intersection of each word line and each bit line. Each memory cell can store one or more bits. In the same physical erase unit, all memory cells will be erased together. In this exemplary embodiment, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. For example, the physical erasing unit is a physical block. On the other hand, memory cells on the same word line form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into lower physical programming units and upper physical programming units. Generally speaking, the writing speed of the lower physical programming unit is greater than that of the upper physical programming unit. In this exemplary embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page or an entity sector. If the physical programming unit is a physical page, each physical programming unit usually includes a data bit area and a redundant bit area. The data bit area contains multiple physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, error correction code). In this exemplary embodiment, each data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the present invention does not limit the size and number of physical sectors.
在本范例实施例中，可复写式非易失性存储器模块106为多层记忆胞(Multi Level Cell,简称：MLC)NAND型快闪存储器模块，即一个记忆胞中可存储至少2个比特。然而，本发明不限于此，可复写式非易失性存储器模块106也可是单层记忆胞(Single Level Cell,简称：SLC)NAND型快闪存储器模块、复数层记忆胞（Trinary Level Cell,简称：TLC）NAND型快闪存储器模块、其他快闪存储器模块或其他具有相同特性的存储器模块。In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level memory cell (Multi Level Cell, MLC for short) NAND flash memory module, that is, at least 2 bits can be stored in one memory cell. However, the present invention is not limited thereto, and the rewritable non-volatile memory module 106 may also be a single-level memory cell (Single Level Cell, referred to as: SLC) NAND flash memory module, a multi-layer memory cell (Trinary Level Cell, referred to as SLC) : TLC) NAND-type flash memory modules, other flash memory modules, or other memory modules with the same characteristics.
在此范例实施例中，存储器控制电路单元104是通过多个通道(channel)电性连接至可复写式非易失性存储器模块106。每一个通道是电性连接至部分的实体抹除单元304(0)～304(R)。这些通道上的操作是彼此独立的。举例来说，存储器控制电路单元104在一个通道上执行写入操作时，可以同时在另一个通道上执行读取操作。然而，本发明并不限制通道的个数，也不限制每一个通道是电性连接至哪些实体抹除单元。在另一范例实施例中，存储器控制电路单元104与可复写式非易失性存储器模块106之间只有一个通道，本发明并不在此限。In this exemplary embodiment, the memory control circuit unit 104 is electrically connected to the rewritable non-volatile memory module 106 through a plurality of channels. Each channel is electrically connected to some of the physical erasing units 304(0)˜304(R). Operations on these channels are independent of each other. For example, when the memory control circuit unit 104 performs a write operation on one channel, it can simultaneously perform a read operation on another channel. However, the present invention does not limit the number of channels, nor does it limit which physical erasing units each channel is electrically connected to. In another exemplary embodiment, there is only one channel between the memory control circuit unit 104 and the rewritable non-volatile memory module 106 , but the invention is not limited thereto.
图3是根据一范例实施例所示出存储器控制电路单元的概要示意图。FIG. 3 is a schematic diagram illustrating a memory control circuit unit according to an exemplary embodiment.
请参照图3，存储器控制电路单元104包括存储器管理电路202、主机接口204与存储器接口206。Referring to FIG. 3 , the memory control circuit unit 104 includes a memory management circuit 202 , a host interface 204 and a memory interface 206 .
存储器管理电路202用以控制存储器控制电路单元104的整体运作。具体来说，存储器管理电路202具有多个控制指令，并且在存储器存储装置100运作时，此些控制指令会被执行以进行数据的写入、读取与抹除等运作。以下说明存储器管理电路202的操作时，等同于说明存储器控制电路单元104的操作，以下并不再赘述。The memory management circuit 202 is used to control the overall operation of the memory control circuit unit 104 . Specifically, the memory management circuit 202 has a plurality of control instructions, and when the memory storage device 100 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 202 is equivalent to the description of the operation of the memory control circuit unit 104 , which will not be repeated below.
在本范例实施例中，存储器管理电路202的控制指令是以固件形式来实作。例如，存储器管理电路202具有微处理器单元(未示出)与只读存储器(未示出)，并且此些控制指令是被烧录至此只读存储器中。当存储器存储装置100运作时，此些控制指令会由微处理器单元来执行以进行数据的写入、读取与抹除等运作。In this exemplary embodiment, the control commands of the memory management circuit 202 are implemented in the form of firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 100 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading and erasing data.
在本发明另一范例实施例中，存储器管理电路202的控制指令也可以程序码形式储存于可复写式非易失性存储器模块106的特定区域(例如，存储器模块中专用于存放系统数据的系统区)中。此外，存储器管理电路202具有微处理器单元(未示出)、只读存储器(未示出)及随机存取存储器(未示出)。特别是，此只读存储器具有开机码(boot code)，并且当存储器控制电路单元104被致能时，微处理器单元会先执行此开机码来将存储于可复写式非易失性存储器模块106中的控制指令载入至存储器管理电路202的随机存取存储器中。之后，微处理器单元会运转此些控制指令以进行数据的写入、读取与抹除等运作。In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be stored in a specific area of the rewritable non-volatile memory module 106 in the form of program code (for example, a system dedicated to storing system data in the memory module) area). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit unit 104 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory module The control instructions in 106 are loaded into the random access memory of the memory management circuit 202 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.
此外，在本发明另一范例实施例中，存储器管理电路202的控制指令也可以一硬件形式来实作。例如，存储器管理电路202包括微控制器、存储器管理单元、存储器写入单元、存储器读取单元、存储器抹除单元与数据处理单元。存储器管理单元、存储器写入单元、存储器读取单元、存储器抹除单元与数据处理单元是电性连接至微控制器。其中，存储器管理单元用以管理可复写式非易失性存储器模块106的实体抹除单元；存储器写入单元用以对可复写式非易失性存储器模块106下达写入指令以将数据写入至可复写式非易失性存储器模块106中；存储器读取单元用以对可复写式非易失性存储器模块106下达读取指令以从可复写式非易失性存储器模块106中读取数据；存储器抹除单元用以对可复写式非易失性存储器模块106下达抹除指令以将数据从可复写式非易失性存储器模块106中抹除；而数据处理单元用以处理欲写入至可复写式非易失性存储器模块106的数据以及从可复写式非易失性存储器模块106中读取的数据。In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be implemented in a hardware form. For example, the memory management circuit 202 includes a microcontroller, a memory management unit, a memory writing unit, a memory reading unit, a memory erasing unit and a data processing unit. The memory management unit, the memory writing unit, the memory reading unit, the memory erasing unit and the data processing unit are electrically connected to the microcontroller. Wherein, the memory management unit is used to manage the physical erasing unit of the rewritable non-volatile memory module 106; the memory write unit is used to issue a write command to the rewritable non-volatile memory module 106 to write data In the rewritable non-volatile memory module 106; the memory reading unit is used to issue a read instruction to the rewritable non-volatile memory module 106 to read data from the rewritable non-volatile memory module 106 ; The memory erasing unit is used to issue an erase command to the rewritable non-volatile memory module 106 to erase data from the rewritable non-volatile memory module 106; and the data processing unit is used to process the write-in Data to the rewritable nonvolatile memory module 106 and data read from the rewritable nonvolatile memory module 106 .
主机接口204是电性连接至存储器管理电路202并且用以接收与识别主机系统1000所传送的指令与数据。也就是说，主机系统1000所传送的指令与数据会通过主机接口204来传送至存储器管理电路202。在本范例实施例中，主机接口204是兼容于SATA标准。然而，必须了解的是本发明不限于此，主机接口204也可以是兼容于PATA标准、IEEE1394标准、PCI Express标准、USB标准、SD标准、UHS-I标准、UHS-II标准、MS标准、MMC标准、eMMC标准、UFS标准、CF标准、IDE标准或其他适合的数据传输标准。The host interface 204 is electrically connected to the memory management circuit 202 and used for receiving and identifying commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this exemplary embodiment, the host interface 204 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 can also be compatible with PATA standard, IEEE1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.
存储器接口206是电性连接至存储器管理电路202并且用以存取可复写式非易失性存储器模块106。也就是说，欲写入至可复写式非易失性存储器模块106的数据会经由存储器接口206转换为可复写式非易失性存储器模块106所能接受的格式。The memory interface 206 is electrically connected to the memory management circuit 202 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 will be converted into a format acceptable to the rewritable nonvolatile memory module 106 via the memory interface 206 .
在本发明一范例实施例中，存储器控制电路单元104还包括缓冲存储器252、电源管理电路254、错误检查与校正电路256与时脉产生电路258。In an exemplary embodiment of the present invention, the memory control circuit unit 104 further includes a buffer memory 252 , a power management circuit 254 , an error checking and correction circuit 256 and a clock generation circuit 258 .
缓冲存储器252是电性连接至存储器管理电路202并且用以暂存来自于主机系统1000的数据与指令或来自于可复写式非易失性存储器模块106的数据。The buffer memory 252 is electrically connected to the memory management circuit 202 and used for temporarily storing data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106 .
电源管理电路254是电性连接至存储器管理电路202并且用以控制存储器存储装置100的电源。The power management circuit 254 is electrically connected to the memory management circuit 202 and used to control the power of the memory storage device 100 .
错误检查与校正电路256是电性连接至存储器管理电路202并且用以执行错误检查与校正程序以确保数据的正确性。具体来说，当存储器管理电路202从主机系统1000中接收到写入指令时，错误检查与校正电路256会为对应此写入指令的数据产生对应的错误更正码(error correcting code,简称：ECC)，并且存储器管理电路202会将对应此写入指令的数据与对应的错误更正码写入至可复写式非易失性存储器模块106中。之后，当存储器管理电路202从可复写式非易失性存储器模块106中读取数据时会同时读取此数据对应的错误更正码，并且错误检查与校正电路256会依据此错误更正码对所读取的数据执行错误检查与校正程序。The error checking and correcting circuit 256 is electrically connected to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correction circuit 256 will generate a corresponding error correcting code (ECC for short) for the data corresponding to the write command. ), and the memory management circuit 202 writes the data corresponding to the write command and the corresponding error correction code into the rewritable non-volatile memory module 106 . Afterwards, when the memory management circuit 202 reads data from the rewritable non-volatile memory module 106, it will read the error correction code corresponding to the data at the same time, and the error checking and correction circuit 256 will check all the data according to the error correction code. The read data is subjected to error checking and correction procedures.
时脉产生电路258是用以产生时脉信号以让存储器管理电路202来存取可复写式非易失性存储器模块106。具体来说，时脉产生电路258所产生的时脉信号会提供给可复写式非易失性存储器模块106，并且可复写式非易失性存储器模块106会根据此时脉信号来执行读取、写入或是其他操作。当所提供的时脉信号的频率越大时，可复写式非易失性存储器模块106的运作速度也会越快。在一范例实施例中，时脉产生电路258所产生的时脉信号也可以提供给存储器控制电路单元104中的其他电路，藉此这些电路也是根据所提供的时脉信号来运作。在此范例实施例中，时脉产生电路258可提供两个以上不同频率的时脉信号。例如，时脉产生电路258中包括了一或多个振荡器，而这些振荡器可以是哈特利(Hartley)振荡器、柯比兹(Colpitts)振荡器、克拉普(Clapp)振荡器、相移(phase-shift)振荡器、RC振荡器、LC振荡器或其他种类的振荡器，本发明并不在此限。The clock generating circuit 258 is used to generate a clock signal for the memory management circuit 202 to access the rewritable non-volatile memory module 106 . Specifically, the clock signal generated by the clock generating circuit 258 will be provided to the rewritable non-volatile memory module 106, and the rewritable non-volatile memory module 106 will perform reading according to this clock signal. , write or other operations. When the frequency of the provided clock signal is higher, the operation speed of the rewritable non-volatile memory module 106 is also faster. In an exemplary embodiment, the clock signal generated by the clock generating circuit 258 can also be provided to other circuits in the memory control circuit unit 104, whereby these circuits also operate according to the provided clock signal. In this exemplary embodiment, the clock generating circuit 258 can provide more than two clock signals with different frequencies. For example, the clock generating circuit 258 includes one or more oscillators, and these oscillators can be Hartley oscillators, Colpitts oscillators, Clapp oscillators, phase oscillators, Phase-shift oscillators, RC oscillators, LC oscillators or other types of oscillators, the invention is not limited thereto.
图4是根据一范例实施例所示出管理可复写式非易失性存储器模块的范例示意图。FIG. 4 is an exemplary schematic diagram showing management of a rewritable non-volatile memory module according to an exemplary embodiment.
必须了解的是，在此描述可复写式非易失性存储器模块106的实体抹除单元的运作时，以“提取”、“划分”、“关联”等词来操作实体抹除单元是逻辑上的概念。也就是说，可复写式非易失性存储器模块的实体抹除单元的实际位置并未更动，而是逻辑上对可复写式非易失性存储器模块的实体抹除单元进行操作。It must be understood that when describing the operation of the physical erasing unit of the rewritable non-volatile memory module 106 here, it is logical to operate the physical erasing unit with words such as "extract", "divide", and "associate". the concept of. That is to say, the actual position of the physical erasing unit of the rewritable non-volatile memory module is not changed, but the physical erasing unit of the rewritable non-volatile memory module is logically operated.
请参照图4，存储器管理电路202可将可复写式非易失性存储器模块的实体抹除单元304(0)～304(R)逻辑地划分为多个区域，例如为数据区402、闲置区404与系统区406。亦即，实体抹除单元304(0)～304(R)中的实体程序化单元也被分为数据区402、闲置区404与系统区406。Referring to FIG. 4, the memory management circuit 202 can logically divide the physical erasing units 304(0)-304(R) of the rewritable non-volatile memory module into multiple areas, such as the data area 402, the idle area 404 and system area 406 . That is, the physical programming units in the physical erasing units 304 ( 0 )˜ 304 (R) are also divided into a data area 402 , an idle area 404 and a system area 406 .
数据区402的实体抹除单元是用以存储来自主机系统1000的数据。闲置区404的实体抹除单元是用以作为数据区402的暂存区。举例来说，若主机系统1000要更新数据区402中的数据，则此数据会先被写入至闲置区404中，之后这些数据会被搬移至数据区402中或与数据区402中的数据合并。或者，闲置区404的实体抹除单元也可用来替换数据区402与系统区406的实体抹除单元。也就是说，当数据区402与系统区406中的实体抹除单元损毁(即，成为坏实体抹除单元(bad physical erasing unit))时，闲置区404的实体抹除单元可用来替换此坏实体抹除单元。倘若闲置区404中无正常的实体抹除单元且有实体抹除单元损毁时，则存储器控制器104会将整个存储器存储装置100宣告为写入保护(write protect)状态，而无法再写入数据。在另一范例实施例中，存储器管理电路202可再划分出一个取代区，专门存放用来替换坏实体抹除单元的实体抹除单元，本发明并不在此限。The physical erase unit of the data area 402 is used to store data from the host system 1000 . The physical erasing unit of the spare area 404 is used as a temporary storage area for the data area 402 . For example, if the host system 1000 wants to update the data in the data area 402, the data will be written into the idle area 404 first, and then the data will be moved to the data area 402 or be combined with the data in the data area 402 merge. Alternatively, the physical erasing units in the spare area 404 can also be used to replace the physical erasing units in the data area 402 and the system area 406 . That is to say, when the physical erasing unit in the data area 402 and the system area 406 is damaged (that is, becomes a bad physical erasing unit (bad physical erasing unit)), the physical erasing unit in the spare area 404 can be used to replace the bad physical erasing unit. Physical erasing unit. If there is no normal physical erasing unit in the spare area 404 and a physical erasing unit is damaged, the memory controller 104 will declare the entire memory storage device 100 as a write protect state, and data cannot be written any more. . In another exemplary embodiment, the memory management circuit 202 may further divide a replacement area to specifically store the physical erasing unit used to replace the bad physical erasing unit, and the invention is not limited thereto.
系统区406的实体抹除单元是用以记录系统数据，其中此系统数据包括可复写式非易失性存储器模块106的识别码，关于存储器芯片的制造商与型号、存储器芯片的容量(实体抹除单元数)、制造商信息、每一实体抹除单元的实体程序化单元数、或存储器存储装置100在连接上主机系统1000时提供主机系统1000用以辨识存储器存储装置100的身份与规格的相关信息等。值得注意的是，这些系统数据不会存储在数据区402或闲置区404。The physical erase unit of the system area 406 is used to record system data, wherein the system data includes the identification code of the rewritable non-volatile memory module 106, the manufacturer and model of the memory chip, the capacity of the memory chip (physical erase number of divided units), manufacturer information, the number of physical programming units of each physical erasing unit, or the memory storage device 100 provides the host system 1000 with the identity and specification of the memory storage device 100 when it is connected to the host system 1000 related information etc. It should be noted that these system data will not be stored in the data area 402 or the spare area 404 .
数据区402、闲置区404与系统区406的实体抹除单元的数量会依据不同的存储器规格而有所不同。此外，必须了解的是，在存储器存储装置100的运作中，实体抹除单元关联至数据区402、闲置区404与系统区406的分组关系会动态地变动。例如，当数据区402中的实体抹除单元损坏而被闲置区404的实体抹除单元取代时，则原本闲置区404的实体抹除单元会被关联至数据区402。The numbers of physical erasing units in the data area 402 , the free area 404 and the system area 406 are different according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 100 , the grouping relationship of the physical erasing unit associated with the data area 402 , the idle area 404 and the system area 406 will change dynamically. For example, when the physical erasing unit in the data area 402 is damaged and replaced by the physical erasing unit in the spare area 404 , the original physical erasing unit in the spare area 404 will be associated with the data area 402 .
存储器管理电路202会配置逻辑地址410(0)～410(D)以映射至数据区402中的实体抹除单元304(0)～304(A)。主机系统1000是通过逻辑地址410(0)～410(D)来存取数据区402中的数据。在此范例实施例中，一个逻辑地址是映射至一个实体存储单元(一个实体存储单元代表一个实体地址，例如实体扇)，多个逻辑地址会组成一个逻辑程序化单元，并且多个逻辑程序化单元会组成一个逻辑抹除单元。一个逻辑程序化单元是映射至一或多个实体程序化单元，而一个逻辑抹除单元是映射至一或多个实体抹除单元。The memory management circuit 202 configures the logical addresses 410(0)˜410(D) to be mapped to the physical erasing units 304(0)˜304(A) in the data area 402 . The host system 1000 accesses the data in the data area 402 through logical addresses 410(0)˜410(D). In this exemplary embodiment, a logical address is mapped to a physical storage unit (a physical storage unit represents a physical address, such as a physical sector), multiple logical addresses will form a logical programming unit, and multiple logical programming The cells will form a logical erase unit. A logical programming unit is mapped to one or more physical programming units, and a logical erasing unit is mapped to one or more physical erasing units.
在此范例实施例中，存储器管理电路202是以逻辑抹除单元来管理可复写式非易失性存储器模块106，因此存储器管理电路202会建立一个实体地址映射表以记录逻辑抹除单元与实体抹除单元之间的映射关系。在另一范例实施例中，存储器管理电路202是以逻辑程序化单元来管理可复写式非易失性存储器模块106，因此存储器管理电路202会建立一个实体地址映射表以记录逻辑程序化单元与实体程序化单元之间的映射关系。上述的实体地址映射表可以存储在系统区406之中或是之外，本发明并不在此限。In this exemplary embodiment, the memory management circuit 202 manages the rewritable non-volatile memory module 106 with a logical erasing unit, so the memory management circuit 202 will create a physical address mapping table to record the logical erasing unit and the physical Erase the mapping relationship between units. In another exemplary embodiment, the memory management circuit 202 manages the rewritable non-volatile memory module 106 by logic programming unit, so the memory management circuit 202 will create a physical address mapping table to record the logic programming unit and The mapping relationship between entity programmatic units. The physical address mapping table mentioned above can be stored in or outside the system area 406, and the present invention is not limited thereto.
逻辑地址410(0)～410(D)可能会映射至数据区402或是闲置区404中的实体存储单元，但不会映射至系统区406中的实体存储单元。以另外一个角度来说，在本范例实施例中，系统区406中的实体程序化单元不会映射至主机系统1000传送的一写入指令中的逻辑地址，亦即系统区406中的实体程序化单元不会映射至存储器存储装置100所提供给主机系统1000使用的逻辑地址410(0)～410(D)，逻辑地址410(0)～410(D)可为存储器存储装置100中的实体地址映射表中的逻辑地址。Logical addresses 410 ( 0 )˜410 (D) may be mapped to physical storage units in the data area 402 or spare area 404 , but not mapped to physical storage units in the system area 406 . From another point of view, in this exemplary embodiment, the entity programming unit in the system area 406 is not mapped to the logical address in a write command sent by the host system 1000, that is, the entity program in the system area 406 The logical addresses 410(0)-410(D) provided by the memory storage device 100 to the host system 1000 are not mapped to the logical addresses 410(0)-410(D), which may be entities in the memory storage device 100 Logical address in the address mapping table.
当主机系统1000要存取可复写式非易失性存储器模块106中的数据时，主机系统1000可下达读取指令或是写入指令给存储器控制电路单元104。存储器控制电路单元104会根据此读取指令从可复写式非易失性存储器模块106中读取数据或者是把数据写入至可复写式非易失性存储器模块106中。此外，在主机系统1000没有下达指令的情况下，存储器控制电路单元104也可存取可复写式非易失性存储器模块106，例如执行垃圾收集(garbagecollection)、或是存取系统区406中的数据。特别的是，在不同的情况下，存储器控制电路单元104会提供不同频率的时脉信号给可复写式非易失性存储器模块106。When the host system 1000 wants to access the data in the rewritable non-volatile memory module 106 , the host system 1000 can issue a read command or a write command to the memory control circuit unit 104 . The memory control circuit unit 104 reads data from the rewritable non-volatile memory module 106 or writes data into the rewritable non-volatile memory module 106 according to the read instruction. In addition, when the host system 1000 does not issue an instruction, the memory control circuit unit 104 can also access the rewritable non-volatile memory module 106, such as performing garbage collection (garbage collection), or accessing the memory in the system area 406 data. In particular, under different circumstances, the memory control circuit unit 104 provides clock signals of different frequencies to the rewritable non-volatile memory module 106 .
举例来说，当存储器管理电路202要读取可复写式非易失性存储器模块106时，时脉产生电路258会提供第一时脉信号给可复写式非易失性存储器模块106与存储器管理电路202，并且存储器管理电路202会根据第一时脉信号读取可复写式非易失性存储器模块106中的第一数据。当存储器管理电路202要把一第二数据写入可复写式非易失性存储器模块106时，时脉产生电路258会提供第二时脉信号给可复写式非易失性存储器模块106与存储器管理电路202，并且存储器管理电路202会根据第二时脉信号将第二数据写入至可复写式非易失性存储器模块106中。其中第二时脉信号的频率不同于第一时脉信号的频率。例如，第二时脉信号的频率是小于第一时脉信号的频率。因此，在读取第一数据时，可复写式非易失性存储器模块106是操作在较高的频率，藉此可以增加读取速度。另一方面，在写入第二数据时，可复写式非易失性存储器模块106是操作在较低的频率，藉此可以降低在写入的过程中第二数据发生错误的机率。然而，在另一范例实施例中，第二时脉信号的频率也可是大于第一时脉信号的频率，本发明并不在此限。For example, when the memory management circuit 202 wants to read the rewritable non-volatile memory module 106, the clock generator circuit 258 will provide the first clock signal to the rewritable non-volatile memory module 106 and the memory management The circuit 202, and the memory management circuit 202 reads the first data in the rewritable non-volatile memory module 106 according to the first clock signal. When the memory management circuit 202 is about to write a second data into the rewritable nonvolatile memory module 106, the clock generator circuit 258 will provide a second clock signal to the rewritable nonvolatile memory module 106 and the memory The management circuit 202, and the memory management circuit 202 writes the second data into the rewritable non-volatile memory module 106 according to the second clock signal. Wherein the frequency of the second clock signal is different from the frequency of the first clock signal. For example, the frequency of the second clock signal is smaller than the frequency of the first clock signal. Therefore, when reading the first data, the rewritable non-volatile memory module 106 operates at a higher frequency, thereby increasing the reading speed. On the other hand, when writing the second data, the rewritable non-volatile memory module 106 operates at a lower frequency, thereby reducing the probability of errors in the second data during the writing process. However, in another exemplary embodiment, the frequency of the second clock signal may also be greater than the frequency of the first clock signal, and the invention is not limited thereto.
在一范例实施例中，上述的读取或写入操作是由主机系统1000所指示。具体来说，存储器管理电路202会接收来自主机系统1000的一第一指令。存储器管理电路202会判断此第一指令的类别。若第一指令为读取指令，则时脉产生电路258会提供第一时脉信号，并且存储器管理电路202会根据第一时脉信号读取第一数据。若第一指令为写入指令，则时脉产生电路258会提供第二时脉信号，并且存储器管理电路202会根据第二时脉信号将第二数据写入至可复写式非易失性存储器模块106。然而，在另一范例实施例中，上述的读取或写入操作并不是由主机系统1000所指示。例如，在执行垃圾收集时(并不是由主机系统1000所指示)，存储器管理电路202也会读取或写入若干数据。本发明并不限制上述读取或写入操作是否由主机系统1000所指示，也不限制第一数据与第二数据的来源与内容。In an exemplary embodiment, the above-mentioned read or write operation is instructed by the host system 1000 . Specifically, the memory management circuit 202 receives a first command from the host system 1000 . The memory management circuit 202 determines the type of the first instruction. If the first command is a read command, the clock generating circuit 258 will provide the first clock signal, and the memory management circuit 202 will read the first data according to the first clock signal. If the first command is a write command, the clock generating circuit 258 will provide a second clock signal, and the memory management circuit 202 will write the second data into the rewritable non-volatile memory according to the second clock signal Module 106. However, in another exemplary embodiment, the above-mentioned read or write operation is not instructed by the host system 1000 . For example, when performing garbage collection (not directed by the host system 1000), the memory management circuit 202 also reads or writes some data. The present invention does not limit whether the above read or write operation is instructed by the host system 1000, nor does it limit the source and content of the first data and the second data.
在一范例实施例中，要读取重要的数据时，会使用频率较低的第二时脉信号；而读取相对较不重要的数据时，会使用频率较高的第一时脉信号。举例来说，存储在系统区406的数据是相对地比存储在数据区402中的数据重要。在一范例实施例中，上述的第一数据可存储在数据区402，而存储器管理电路202要读取数据区402中的第一数据时，存储器管理电路202会使用频率较高的第一时脉信号来读取数据。然而，当存储器管理电路202要读取存储在系统区406中的一第三数据(例如，实体地址映射表)时，时脉产生电路258会提供第二时脉信号给可复写式非易失性存储器模块106，并且存储器管理电路202会根据第二时脉信号读取系统区406中的第三数据。藉此，可以降低读取重要数据时发生错误的机率。In an exemplary embodiment, when important data is to be read, the second clock signal with a lower frequency is used; and when relatively less important data is read, the first clock signal with a higher frequency is used. For example, the data stored in the system area 406 is relatively more important than the data stored in the data area 402 . In an exemplary embodiment, the above-mentioned first data can be stored in the data area 402, and when the memory management circuit 202 wants to read the first data in the data area 402, the memory management circuit 202 will use the first time with a higher frequency Pulse signal to read data. However, when the memory management circuit 202 wants to read a third data (for example, physical address mapping table) stored in the system area 406, the clock generator circuit 258 will provide the second clock signal to the rewritable non-volatile The permanent memory module 106, and the memory management circuit 202 reads the third data in the system area 406 according to the second clock signal. In this way, the probability of errors when reading important data can be reduced.
在一范例实施例中，在发生读取错误时，存储器管理电路202会重复执行读取的操作。在使用频率较高的第一时脉信号来读取第一数据时，存储器管理电路202还会计算一个读取错误次数，并且根据此读取错误次数判断是否要改用频率较低的第二时脉信号来读取第一数据。具体来说，在第一数据被写入至可复写式非易失性存储器模块106时，错误检查与校正电路256会产生对应的错误更正码或错误检查码(error detection code，简称：EDC)。这些错误更正码或是错误检查码可以是汉明码(hamming code)、低密度奇偶检查码(low density parity check code，简称：LDPC code)、涡轮码(turbo code)或里德-所罗门码(Reed-solomon code，简称：RS code)、BCH码、或是使用其他演算法的码，本发明并不在此限。存储器管理电路202会将对应的错误更正码或错误检查码写入至可复写式非易失性存储器模块106中。当读取第一数据时，存储器管理电路202也会一并读取对应的错误更正码或错误检查码。错误检查与校正电路256会根据此错误更正码或错误检查码判断第一数据是否有错误。例如，错误检查与校正电路256会先根据错误更正码判断第一数据是否有错误。若根据错误更正码判断第一数据没有错误，错误检查与校正电路256还会根据错误检查码来判断第一数据是否有错误。若第一数据有错误，存储器管理电路202会判断读取错误次数是否符合一个临界条件(例如，大于一个临界值)。若第一数据有错误且读取错误次数不符合该临界条件(例如，小于临界值)，存储器管理电路202会根据第一时脉信号重新读取第一数据并且更新读取错误次数(例如，加上1)。亦即，读取错误次数也可以表示重复读取第一数据的次数。若第一数据有错误且读取错误次数符合临界条件，时脉产生电路258会提供频率较低的第二时脉信号给可复写式非易失性存储器模块106，并且存储器管理电路202会根据第二时脉信号读取第一数据，藉此降低读取错误的机率。In an exemplary embodiment, when a read error occurs, the memory management circuit 202 repeats the read operation. When using the first clock signal with a higher frequency to read the first data, the memory management circuit 202 will also calculate a number of read errors, and judge whether to use the second clock signal with a lower frequency according to the number of read errors. clock signal to read the first data. Specifically, when the first data is written into the rewritable non-volatile memory module 106, the error detection and correction circuit 256 will generate a corresponding error correction code or error detection code (error detection code, EDC for short). . These error correction codes or error check codes can be Hamming codes (hamming codes), low density parity check codes (low density parity check codes, referred to as: LDPC codes), turbo codes (turbo codes) or Reed-Solomon codes (Reed-Solomon codes). -solomon code, referred to as: RS code), BCH code, or a code using other algorithms, the present invention is not limited thereto. The memory management circuit 202 writes the corresponding error correction code or error check code into the rewritable non-volatile memory module 106 . When reading the first data, the memory management circuit 202 also reads the corresponding error correction code or error check code. The error checking and correcting circuit 256 judges whether the first data has an error according to the error correction code or the error check code. For example, the error checking and correcting circuit 256 first determines whether the first data has an error according to the error correction code. If it is determined that the first data has no error according to the error correction code, the error checking and correction circuit 256 will also determine whether the first data has an error according to the error checking code. If there is an error in the first data, the memory management circuit 202 will determine whether the number of read errors meets a critical condition (for example, greater than a critical value). If the first data has an error and the number of read errors does not meet the critical condition (for example, less than the critical value), the memory management circuit 202 will re-read the first data according to the first clock signal and update the number of read errors (for example, plus 1). That is, the number of read errors may also represent the number of times the first data is repeatedly read. If the first data has an error and the number of read errors meets the critical condition, the clock generator circuit 258 will provide a second clock signal with a lower frequency to the rewritable non-volatile memory module 106, and the memory management circuit 202 will follow the The second clock signal reads the first data, thereby reducing the probability of reading errors.
在一范例实施例中，对于每一个电性连接在可复写式非易失性存储器模块106与存储器控制电路单元104之间的通道，存储器管理电路都会记录对应的读取错误次数。因此，读取错误次数也可以表示对应的通道是否容易发生读取错误。在容易发生读取错误的通道上，存储器控制电路单元104可使用频率较低的第二时脉信号来读取数据，同时在其他通道上可能会使用频率较高的第一时脉信号来读取数据。In an exemplary embodiment, for each channel electrically connected between the rewritable non-volatile memory module 106 and the memory control circuit unit 104 , the memory management circuit records the corresponding number of read errors. Therefore, the number of read errors may also indicate whether the corresponding channel is prone to read errors. On channels prone to read errors, the memory control circuit unit 104 may use the second clock signal with a lower frequency to read data, while other channels may use the first clock signal with a higher frequency to read data. fetch data.
上述判断使用第一时脉信号或第二时脉信号的步骤也可以任意地结合。例如，图5是根据一范例实施例示出判断使用第一时脉信号或第二时脉信号的流程图。请参照图5，在步骤S501中，判断读取错误次数是否符合临界条件。若读取错误次数符合临界条件，进行步骤S505。若读取错误次数不符合临界条件，在步骤S502中，判断要存取的数据是否在系统区406。若要存取的数据是在系统区406，进行步骤S505。若要存取的数据不在系统区406，在步骤S503中，判断所要执行的是否为写入操作。若所要执行的是写入操作，进行步骤S505。若所要执行的不是写入操作，进行步骤S504，提供频率较低的时脉信号给可复写式非易失性存储器模块106。在步骤S505中，提供频率较高的时脉信号给可复写式非易失性存储器模块106。然而，本发明并不限制如何结合步骤S501～503。The above step of determining whether to use the first clock signal or the second clock signal may also be combined arbitrarily. For example, FIG. 5 is a flowchart illustrating determining whether to use the first clock signal or the second clock signal according to an exemplary embodiment. Referring to FIG. 5 , in step S501 , it is determined whether the number of read errors meets a critical condition. If the number of reading errors meets the critical condition, go to step S505. If the number of reading errors does not meet the critical condition, in step S502, it is determined whether the data to be accessed is in the system area 406. The data to be accessed is in the system area 406, go to step S505. If the data to be accessed is not in the system area 406, in step S503, it is determined whether the to-be-executed is a write operation. If the write operation is to be performed, go to step S505. If the operation to be performed is not a write operation, proceed to step S504 , providing a clock signal with a lower frequency to the rewritable non-volatile memory module 106 . In step S505 , a clock signal with a higher frequency is provided to the rewritable non-volatile memory module 106 . However, the present invention does not limit how to combine steps S501-503.
[第二范例实施例][Second Exemplary Embodiment]
在此仅说明第二范例实施例与第一范例实施例不同之处。请参照图4，在第二范例实施例中，时脉产生电路258会提供第一时脉信号或是第二时脉信号给可复写式非易失性存储器模块106。然而，存储器管理电路202会应用第一时脉信号对数据区402或是闲置区404执行第一操作，并且会应用第二时脉信号对数据区402或是闲置区404执行第二操作。第一操作与第二操作可以相同或是不相同。此外，第一操作与第二操作可以是根据主机系统1000所下达的指令所执行，也可以是存储器管理电路202本身所执行，本发明并不在此限。然而，第一时脉信号的频率不同于第二时脉信号的频率。举例来说，第二时脉信号的频率小于该第一时脉信号的频率。Only the differences between the second exemplary embodiment and the first exemplary embodiment are described here. Please refer to FIG. 4 , in the second exemplary embodiment, the clock generating circuit 258 provides the first clock signal or the second clock signal to the rewritable non-volatile memory module 106 . However, the memory management circuit 202 performs a first operation on the data area 402 or the idle area 404 using the first clock signal, and performs a second operation on the data area 402 or the idle area 404 using the second clock signal. The first operation and the second operation may be the same or different. In addition, the first operation and the second operation may be executed according to an instruction issued by the host system 1000 , or may be executed by the memory management circuit 202 itself, and the present invention is not limited thereto. However, the frequency of the first clock signal is different from the frequency of the second clock signal. For example, the frequency of the second clock signal is lower than the frequency of the first clock signal.
在一范例实施例中，第一操作为读取操作，并且第二操作为写入操作。在另一范例实施例中，上述的实体地址映射表是存储在闲置区404中的实体抹除单元，第一操作是用以读取数据区402或是闲置区404中的使用者数据，而第二操作是用以读取闲置区404中的实体地址映射表。In an exemplary embodiment, the first operation is a read operation, and the second operation is a write operation. In another exemplary embodiment, the above physical address mapping table is a physical erasing unit stored in the idle area 404, the first operation is to read the user data in the data area 402 or the idle area 404, and The second operation is to read the physical address mapping table in the spare area 404 .
在一范例实施例中，第一操作是用以读取数据区402或是闲置区404中的第一数据，而第二操作是用以在第一数据有错误时重读第一数据。具体来说，在应用第一时脉信号读取第一数据以后，存储器管理电路202会根据错误更正码或是错误检查码来判断第一数据是否有错误。若根据错误更正码或是错误检查码判断第一数据有错误，则存储器管理电路会执行第二操作，以应用第二时脉信号来重新读取第一数据。In an exemplary embodiment, the first operation is used to read the first data in the data area 402 or the idle area 404 , and the second operation is used to re-read the first data when the first data has an error. Specifically, after reading the first data by using the first clock signal, the memory management circuit 202 determines whether the first data has an error according to the error correction code or the error check code. If it is judged that the first data has an error according to the error correction code or the error check code, the memory management circuit executes a second operation to read the first data again by using the second clock signal.
综上所述，本发明范例实施例提出的存储器控制方法，存储器存储装置与存储器控制电路单元，可以依照不同的情况提供不同频率的时脉信号给可复写式非易失性存储器模块。藉此，可以提升可复写式非易失性存储器模块运作的速度，或者是降低一些操作发生错误的机率。To sum up, the memory control method, the memory storage device and the memory control circuit unit proposed by the exemplary embodiments of the present invention can provide clock signals of different frequencies to the rewritable non-volatile memory module according to different situations. In this way, the operation speed of the rewritable non-volatile memory module can be improved, or the probability of errors in some operations can be reduced.
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.
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| CN201310558040.3ACN104636267B (en) | 2013-11-11 | 2013-11-11 | Memory control method, memory storage device and memory control circuit unit |
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