技术领域technical field
本发明涉及显示技术领域，尤其涉及一种双栅线阵列基板和显示装置。The invention relates to the field of display technology, in particular to a double grid line array substrate and a display device.
背景技术Background technique
TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器)作为目前主流的显示器件，广泛的应用于手机、监控器、电视机等显示产品中。TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-Liquid Crystal Display), as the current mainstream display device, is widely used in mobile phones, monitors, televisions and other display products.
TFT-LCD本身的像素结构使其不可避免的存在因栅极电压由高至低而造成的跳变电压，跳变电压的产生会对TFT-LCD的显示品质产生直接的影响。The pixel structure of the TFT-LCD itself makes it inevitable that there will be a jump voltage caused by the gate voltage changing from high to low. The generation of the jump voltage will have a direct impact on the display quality of the TFT-LCD.
基于此，通过降低跳变电压以获得高品质的TFT-LCD，对于提高市场竞争力和获得良好的用户体验至关重要。Based on this, it is very important to improve market competitiveness and obtain a good user experience by reducing the jump voltage to obtain high-quality TFT-LCD.
发明内容Contents of the invention
本发明的实施例提供一种双栅线阵列基板和显示装置，可增大显示装置的存储电容，从而降低跳变电压，改善显示品质。Embodiments of the present invention provide a double grid line array substrate and a display device, which can increase the storage capacitance of the display device, thereby reducing the jump voltage and improving the display quality.
为达到上述目的，本发明的实施例采用如下技术方案：In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:
一方面，提供一种双栅线阵列基板，包括横纵交错的多个栅线组和多条数据线，以及阵列排布的多个像素单元；所述栅线组包括第一栅线和第二栅线；所述阵列基板还包括：位于所述像素单元内部的第一公共电极线，以及与所述第一栅线和所述第二栅线之间的间隙对应的第二公共电极线；位于所述像素单元内部的像素电极，以及与所述像素电极电连接的辅助电极；其中，所述第一公共电极线与所述像素电极之间具有交叠区域，所述第二公共电极线与所述辅助电极之间具有交叠区域。On the one hand, there is provided a double grid line array substrate, including a plurality of grid line groups and a plurality of data lines criss-crossing, and a plurality of pixel units arranged in an array; the gate line group includes a first gate line and a second Two gate lines; the array substrate further includes: a first common electrode line located inside the pixel unit, and a second common electrode line corresponding to the gap between the first gate line and the second gate line ; a pixel electrode located inside the pixel unit, and an auxiliary electrode electrically connected to the pixel electrode; wherein, there is an overlapping area between the first common electrode line and the pixel electrode, and the second common electrode There is an overlapping area between the wire and the auxiliary electrode.
优选的，所述像素电极与所述辅助电极具有一体化结构。Preferably, the pixel electrode and the auxiliary electrode have an integrated structure.
进一步优选的，所述辅助电极包括与所述第二公共电极线相互交叠的条状部和与所述像素电极相连的连接部；其中，沿平行于所述栅线组的方向，所述连接部的尺寸小于所述条状部的尺寸。Further preferably, the auxiliary electrode includes a strip portion overlapping with the second common electrode line and a connection portion connected to the pixel electrode; wherein, along a direction parallel to the gate line group, the The size of the connecting portion is smaller than that of the strip portion.
优选的，所述第一公共电极线与所述第二公共电极线电连接。Preferably, the first common electrode line is electrically connected to the second common electrode line.
可选的，所述第一公共电极线与所述第二公共电极线通过连接桥进行电连接；其中，所述连接桥与所述像素电极同层形成。Optionally, the first common electrode line is electrically connected to the second common electrode line through a connecting bridge; wherein, the connecting bridge is formed in the same layer as the pixel electrode.
优选的，所述第一公共电极线与所述栅线组同层形成；所述第二公共电极线与所述数据线同层形成，且与所述数据线之间相互绝缘。Preferably, the first common electrode lines are formed in the same layer as the gate line group; the second common electrode lines are formed in the same layer as the data lines, and are insulated from the data lines.
可选的，所述像素单元内部还设置有薄膜晶体管；其中，相邻两个像素单元的薄膜晶体管分别与所述第一栅线和所述第二栅线相连。Optionally, thin film transistors are further arranged inside the pixel unit; wherein, the thin film transistors of two adjacent pixel units are respectively connected to the first gate line and the second gate line.
另一方面，提供一种显示装置，包括上述的阵列基板。In another aspect, a display device is provided, including the above-mentioned array substrate.
本发明的实施例提供一种双栅线阵列基板和显示装置。Embodiments of the present invention provide a dual grid line array substrate and a display device.
现有技术中，所述第一公共电极线与所述像素电极之间存在交叠区域，因此可在二者之间形成存储电容；但是，该存储电容形成在像素单元的内部，若要增大存储电容，则需增加所述第一公共电极线与所述像素电极之间的相对面积，这样必然导致像素单元的开口率有所下降。In the prior art, there is an overlapping area between the first common electrode line and the pixel electrode, so a storage capacitor can be formed between the two; however, the storage capacitor is formed inside the pixel unit. If the storage capacitor is large, the relative area between the first common electrode line and the pixel electrode needs to be increased, which will inevitably lead to a decrease in the aperture ratio of the pixel unit.
本发明的实施例中，通过在所述像素单元的外部(即，所述第一栅线与所述第二栅线之间)设置相互交叠的第二公共电极线和辅助电极，这样一来，在不影响像素单元开口率的前提下，即可在所述第二公共电极线与所述辅助电极之间形成附加存储电容。In an embodiment of the present invention, by arranging mutually overlapping second common electrode lines and auxiliary electrodes outside the pixel unit (that is, between the first gate line and the second gate line), such a Therefore, an additional storage capacitor can be formed between the second common electrode line and the auxiliary electrode without affecting the aperture ratio of the pixel unit.
相比于现有技术，本发明的实施例可在不影响开口率的前提下，有效的提高存储电容的大小。Compared with the prior art, the embodiment of the present invention can effectively increase the size of the storage capacitor without affecting the aperture ratio.
在此基础上，跳变电压的理论公式如下：On this basis, the theoretical formula of the jump voltage is as follows:
其中，△Vp为跳变电压，Vgh、Vgl分别为驱动TFT的栅极高电平电压和栅极低电平电压，Cgs、Clc、Cst分别为寄生电容、液晶电容、存储电容。Among them, △Vp is the jump voltage, Vgh and Vgl are the gate high-level voltage and gate low-level voltage of the driving TFT respectively, and Cgs, Clc and Cst are the parasitic capacitance, liquid crystal capacitance and storage capacitance respectively.
基于此，本发明的实施例通过增大存储电容，可以有效的降低跳变电压，从而改善TFT-LCD的显示品质。Based on this, the embodiments of the present invention can effectively reduce the jump voltage by increasing the storage capacitance, thereby improving the display quality of the TFT-LCD.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明的实施例提供的一种阵列基板的结构示意图一；FIG. 1 is a first structural schematic diagram of an array substrate provided by an embodiment of the present invention;
图2为图1的A-A截面示意图；Fig. 2 is the A-A sectional schematic diagram of Fig. 1;
图3为本发明的实施例提供的一种像素电极和辅助电极的结构示意图一；FIG. 3 is a first structural schematic diagram of a pixel electrode and an auxiliary electrode provided by an embodiment of the present invention;
图4为本发明的实施例提供的一种像素电极和辅助电极的结构示意图二。FIG. 4 is a second structural schematic diagram of a pixel electrode and an auxiliary electrode provided by an embodiment of the present invention.
附图说明：Description of drawings:
10-阵列基板；101-栅线组；102-数据线；103-第一公共电极线；104-第二公共电极线；105-像素电极；106-辅助电极；107-连接桥。10-array substrate; 101-gate line group; 102-data line; 103-first common electrode line; 104-second common electrode line; 105-pixel electrode; 106-auxiliary electrode; 107-connection bridge.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明的实施例提供一种双栅线阵列基板10，如图1所示，包括横纵交错的多个栅线组101和多条数据线102，以及阵列排布的多个像素单元；其中，所述栅线组101包括相互平行的第一栅线1011和第二栅线1012，且所述第一栅线1011和所述第二栅线1012之间相隔预设间距。An embodiment of the present invention provides a double gate line array substrate 10, as shown in FIG. 1 , including a plurality of grid line groups 101 and a plurality of data lines 102 criss-crossing, and a plurality of pixel units arranged in an array; wherein , the gate line group 101 includes a first gate line 1011 and a second gate line 1012 parallel to each other, and the first gate line 1011 and the second gate line 1012 are separated by a preset distance.
在此基础上，所述阵列基板10还包括：位于所述像素单元内部的第一公共电极线103，以及与所述第一栅线1011和所述第二栅线1012之间的间隙对应的第二公共电极线104；位于所述像素单元内部的像素电极105，以及与所述像素电极105电连接的辅助电极106；其中，所述第一公共电极线103与所述像素电极105之间具有交叠区域，所述第二公共电极线104与所述辅助电极106之间具有交叠区域。On this basis, the array substrate 10 further includes: a first common electrode line 103 located inside the pixel unit, and a gap corresponding to the gap between the first gate line 1011 and the second gate line 1012 The second common electrode line 104; the pixel electrode 105 located inside the pixel unit, and the auxiliary electrode 106 electrically connected to the pixel electrode 105; wherein, between the first common electrode line 103 and the pixel electrode 105 There is an overlapping area, and there is an overlapping area between the second common electrode line 104 and the auxiliary electrode 106 .
需要说明的是，第一，在本发明的实施例中，所述像素单元是指由所述栅线组101和所述数据线102限定的区域。在该区域内，除像素电极105外，还设置有薄膜晶体管和公共电极线等其它结构。It should be noted that, firstly, in the embodiment of the present invention, the pixel unit refers to the area defined by the gate line group 101 and the data line 102 . In this area, besides the pixel electrode 105, other structures such as thin film transistors and common electrode lines are also provided.
第二，所述第一公共电极线103在像素单元的内部形成弯折结构，所述像素电极105位于该弯折结构的中心空白处；也就是说，所述第一公共电极线103是沿着所述像素电极105的边缘排列的。Second, the first common electrode line 103 forms a bent structure inside the pixel unit, and the pixel electrode 105 is located in a blank space in the center of the bent structure; that is, the first common electrode line 103 is along the arranged along the edge of the pixel electrode 105.
在此基础上，为了保证所述第一公共电极线103与所述像素电极105之间形成存储电容，需使两电极之间形成相对面积，因此所述第一公共电极线103与所述像素电极105之间具有交叠区域。当然，这里所形成的交叠区域需以能够获得合理的开口率为准。On this basis, in order to ensure that a storage capacitor is formed between the first common electrode line 103 and the pixel electrode 105, it is necessary to form an opposing area between the two electrodes, so the first common electrode line 103 and the pixel electrode 105 There is an overlapping area between the electrodes 105 . Of course, the overlapping area formed here needs to be subject to obtaining a reasonable aperture ratio.
第三，所述第二公共电极线104可与所述第一公共电极线103同层形成，当然也可与其它导电层同层形成，这里只要能够保证所述第二公共电极线104的设置位置与所述第一栅线1011和所述第二栅线1012之间的间隙对应，从而不影响像素单元的开口率即可。Third, the second common electrode lines 104 can be formed on the same layer as the first common electrode lines 103, and of course can also be formed on the same layer as other conductive layers, as long as the arrangement of the second common electrode lines 104 can be guaranteed The position corresponds to the gap between the first gate line 1011 and the second gate line 1012 so as not to affect the aperture ratio of the pixel unit.
第四，所述辅助电极106可与所述像素电极105同层形成，当然也可独立形成，这里只要能够保证二者之间相互电连接、且所述辅助电极106与所述第二公共电极线104之间具有交叠区域即可。Fourth, the auxiliary electrode 106 can be formed in the same layer as the pixel electrode 105, and of course can also be formed independently, as long as the electrical connection between the two can be ensured, and the auxiliary electrode 106 and the second common electrode It is only necessary for the lines 104 to have overlapping areas.
本发明的实施例提供一种双栅线阵列基板10，包括横纵交错的多个栅线组101和多条数据线102，以及阵列排布的多个像素单元；其中，所述栅线组101包括相互平行的第一栅线1011和第二栅线1012，且所述第一栅线1011和所述第二栅线1012之间相隔预设间距。An embodiment of the present invention provides a dual grid line array substrate 10, including a plurality of grid line groups 101 and a plurality of data lines 102 in a criss-cross pattern, and a plurality of pixel units arranged in an array; wherein, the gate line groups 101 includes a first gate line 1011 and a second gate line 1012 parallel to each other, and the first gate line 1011 and the second gate line 1012 are separated by a preset distance.
所述阵列基板10还包括：位于所述像素单元内部的第一公共电极线103，以及与所述第一栅线1011和所述第二栅线1012之间的间隙对应的第二公共电极线104；位于所述像素单元内部的像素电极105，以及与所述像素电极105电连接的辅助电极106；其中，所述第一公共电极线103与所述像素电极105之间具有交叠区域，所述第二公共电极线104与所述辅助电极106之间具有交叠区域。The array substrate 10 further includes: a first common electrode line 103 located inside the pixel unit, and a second common electrode line corresponding to the gap between the first gate line 1011 and the second gate line 1012 104; a pixel electrode 105 located inside the pixel unit, and an auxiliary electrode 106 electrically connected to the pixel electrode 105; wherein, there is an overlapping area between the first common electrode line 103 and the pixel electrode 105, There is an overlapping area between the second common electrode line 104 and the auxiliary electrode 106 .
现有技术中，所述第一公共电极线103与所述像素电极105之间存在交叠区域，因此可在二者之间形成存储电容；但是，该存储电容形成在像素单元的内部，若要增大存储电容，则需增加所述第一公共电极线103与所述像素电极105之间的相对面积，这样必然导致像素单元的开口率有所下降。In the prior art, there is an overlapping area between the first common electrode line 103 and the pixel electrode 105, so a storage capacitor can be formed between the two; however, the storage capacitor is formed inside the pixel unit, if To increase the storage capacitance, it is necessary to increase the relative area between the first common electrode line 103 and the pixel electrode 105 , which will inevitably lead to a decrease in the aperture ratio of the pixel unit.
本发明的实施例中，如图2所示，通过在所述像素单元的外部(即，所述第一栅线1011与所述第二栅线1012之间)设置相互交叠的第二公共电极线104和辅助电极106，这样一来，在不影响像素单元开口率的前提下，即可在所述第二公共电极线104与所述辅助电极106之间形成附加存储电容。In the embodiment of the present invention, as shown in FIG. 2 , the overlapping second common The electrode line 104 and the auxiliary electrode 106, in this way, an additional storage capacitor can be formed between the second common electrode line 104 and the auxiliary electrode 106 without affecting the aperture ratio of the pixel unit.
相比于现有技术，本发明的实施例可在不影响开口率的前提下，有效的提高存储电容的大小。Compared with the prior art, the embodiment of the present invention can effectively increase the size of the storage capacitor without affecting the aperture ratio.
在此基础上，跳变电压的理论公式如下：On this basis, the theoretical formula of the jump voltage is as follows:
其中，△Vp为跳变电压，Vgh、Vgl分别为驱动TFT的栅极高电平电压和栅极低电平电压，Cgs、Clc、Cst分别为寄生电容、液晶电容、存储电容。Among them, △Vp is the jump voltage, Vgh and Vgl are the gate high-level voltage and gate low-level voltage of the driving TFT respectively, and Cgs, Clc and Cst are the parasitic capacitance, liquid crystal capacitance and storage capacitance respectively.
基于此，本发明的实施例通过增大存储电容，可以有效的降低跳变电压，从而改善TFT-LCD的显示品质。Based on this, the embodiments of the present invention can effectively reduce the jump voltage by increasing the storage capacitance, thereby improving the display quality of the TFT-LCD.
基于上述描述可知，本发明的实施例通过在像素单元的外部设置第二公共电极线和辅助电极，从而增大电极的相对面积，进而达到增大存储电容的目的。基于此，需要说明的是，在所述阵列基板中，通过上述方式而增大的电极相对面积是有限的，为了获得更好的显示效果，本发明的实施例更适用于小尺寸的显示装置，这样可以保证所增大的电极相对面积占像素总面积的比例相对较大，由此便可获得更佳的显示效果。Based on the above description, it can be seen that in the embodiment of the present invention, the second common electrode line and the auxiliary electrode are arranged outside the pixel unit, thereby increasing the relative area of the electrodes, thereby achieving the purpose of increasing the storage capacitance. Based on this, it should be noted that, in the array substrate, the electrode facing area increased by the above method is limited. In order to obtain better display effect, the embodiments of the present invention are more suitable for small-sized display devices. , so as to ensure that the ratio of the increased relative area of the electrode to the total area of the pixel is relatively large, thereby obtaining a better display effect.
优选的，如图3所示，所述像素电极105与所述辅助电极106具有一体化结构。Preferably, as shown in FIG. 3 , the pixel electrode 105 and the auxiliary electrode 106 have an integrated structure.
在此情况下，所述像素电极105和所述辅助电极106具有相同的材质，且通过同一次构图工艺形成。这里所述的同一次构图工艺是指同一次成膜和曝光工艺；也就是说，所述像素电极105和所述辅助电极106是由相同的膜层经过同一次曝光而形成的一体化结构。In this case, the pixel electrode 105 and the auxiliary electrode 106 have the same material and are formed by the same patterning process. The same patterning process mentioned here refers to the same film forming and exposure process; that is, the pixel electrode 105 and the auxiliary electrode 106 are an integrated structure formed by the same film layer through the same exposure.
本发明的实施例通过一次构图工艺即可形成一体结构的像素电极105和辅助电极106，这样可以有效的简化阵列基板的制程，从而降低成本。In the embodiment of the present invention, the integrated structure of the pixel electrode 105 and the auxiliary electrode 106 can be formed through one patterning process, which can effectively simplify the manufacturing process of the array substrate and reduce the cost.
在此基础上，所述辅助电极106可以包括与所述第二公共电极线104相互交叠的条状部和与所述像素电极105相连的连接部。On this basis, the auxiliary electrode 106 may include a strip portion overlapping with the second common electrode line 104 and a connection portion connected to the pixel electrode 105 .
具体的，所述条状部用于与所述第二公共电极线104形成交叠区域，以便于产生存储电容；所述连接部用于与所述像素电极105进行电连接。Specifically, the strip portion is used to form an overlapping area with the second common electrode line 104 so as to generate storage capacitance; the connecting portion is used to electrically connect with the pixel electrode 105 .
为了在有限的区域内获得相对较大的存储电容，所述条状部沿数据线102方向的尺寸优选与所述第二公共电极线104的尺寸一致，所述条状部沿栅线组101方向的尺寸优选与所述像素电极105的尺寸一致，这样可以获得较大的相对面积，从而产生较大的存储电容。In order to obtain a relatively large storage capacitance in a limited area, the size of the strip-shaped portion along the direction of the data line 102 is preferably consistent with the size of the second common electrode line 104, and the size of the strip-shaped portion along the gate line group 101 The size of the direction is preferably consistent with the size of the pixel electrode 105, so that a larger relative area can be obtained, thereby generating a larger storage capacitance.
进一步的，由于所述辅助电极106在与所述像素电极105相连时，所述辅助电极106的连接部需要横跨在其中一条栅线的上方；也就是说，所述辅助电极106的连接部与所述栅线组101中的一条栅线之间会形成交叠区域，这样便会在该栅线与所述连接部之间产生寄生电容。考虑到以上因素，所述连接部沿栅线组101方向的尺寸优选小于所述条状部的尺寸。这里，在保证所述像素电极105与所述辅助电极106电连接的前提下，所述连接部沿栅线组101方向的尺寸越小越好。Further, since the auxiliary electrode 106 is connected to the pixel electrode 105, the connecting portion of the auxiliary electrode 106 needs to cross over one of the gate lines; that is, the connecting portion of the auxiliary electrode 106 An overlapping area is formed with a gate line in the gate line group 101 , so that a parasitic capacitance is generated between the gate line and the connecting portion. Considering the above factors, the size of the connection portion along the direction of the grid line group 101 is preferably smaller than the size of the strip portion. Here, under the premise of ensuring the electrical connection between the pixel electrode 105 and the auxiliary electrode 106 , the smaller the size of the connection portion along the direction of the gate line group 101 , the better.
当然，在本发明的实施例中，如图4所示，所述像素电极105和所述辅助电极106也可以为相互独立的结构。例如，所述像素电极105可与现有技术中的结构相同，所述辅助电极106可与其它导电层同层制备、且通过过孔与所述像素电极105保持电连接；这样一来，所述像素电极105和所述辅助电极106便可形成相互独立的结构，并且不影响所述辅助电极106与所述第二公共电极线104之间形成存储电容。Certainly, in the embodiment of the present invention, as shown in FIG. 4 , the pixel electrode 105 and the auxiliary electrode 106 may also be mutually independent structures. For example, the structure of the pixel electrode 105 can be the same as that in the prior art, and the auxiliary electrode 106 can be prepared on the same layer as other conductive layers, and be electrically connected to the pixel electrode 105 through a via hole; in this way, all The pixel electrode 105 and the auxiliary electrode 106 can form independent structures without affecting the storage capacitance formed between the auxiliary electrode 106 and the second common electrode line 104 .
可选的，参考图1所示，所述第一公共电极线103与所述第二公共电极线104相互电连接。Optionally, referring to FIG. 1 , the first common electrode line 103 and the second common electrode line 104 are electrically connected to each other.
具体的，所述第一公共电极线103与所述第二公共电极线104之间可以通过连接桥107进行电连接。Specifically, the first common electrode line 103 and the second common electrode line 104 may be electrically connected through a connecting bridge 107 .
示例的，所述第一公共电极线103可与所述栅线组101同层制备，所述第二公共电极线104可与所述数据线102同层制备。在此情况下，所述连接桥107可与所述像素电极105同层制备，并通过过孔分别与所述第一公共电极线103和所述第二公共电极线104电连接；或者，所述连接桥107也可与所述第二公共电极线104同层制备，此时所述连接桥107与所述第二公共电极线104具有一体结构，并通过过孔与所述第一公共电极线103电连接。For example, the first common electrode lines 103 can be prepared on the same layer as the gate line group 101 , and the second common electrode lines 104 can be prepared on the same layer as the data lines 102 . In this case, the connecting bridge 107 can be prepared on the same layer as the pixel electrode 105, and be electrically connected to the first common electrode line 103 and the second common electrode line 104 through via holes; or, the The connecting bridge 107 can also be prepared on the same layer as the second common electrode line 104, at this time, the connecting bridge 107 and the second common electrode line 104 have an integrated structure, and are connected to the first common electrode through a via hole. Wire 103 is electrically connected.
这样一来，所述第一公共电极线103与所述第二公共电极线104便可具有相同的电压，当其分别与所述像素电极105和所述辅助电极106形成交叠区域时，即可有效的增大存储电容。In this way, the first common electrode line 103 and the second common electrode line 104 can have the same voltage, when they respectively form overlapping regions with the pixel electrode 105 and the auxiliary electrode 106, that is, It can effectively increase the storage capacity.
在此基础上，所述第一公共电极线103与所述第二公共电极线104相互电连接，这可等效于增加了公共电极线的整体截面积，从而使其电阻得以降低。On this basis, the first common electrode line 103 and the second common electrode line 104 are electrically connected to each other, which is equivalent to increasing the overall cross-sectional area of the common electrode line, thereby reducing its resistance.
可选的，所述第一公共电极线103和所述第二公共电极线104均可与所述栅线组101同层形成。Optionally, both the first common electrode lines 103 and the second common electrode lines 104 can be formed in the same layer as the gate line group 101 .
具体的，可在基板上沉积一层金属薄膜，并通过一次构图工艺对该金属薄膜进行构图，从而形成第一栅线和第二栅线、以及第一公共电极线103和第二公共电极线104。Specifically, a metal thin film can be deposited on the substrate, and the metal thin film is patterned through a patterning process, thereby forming the first gate line and the second gate line, as well as the first common electrode line 103 and the second common electrode line 104.
在此情况下，所述第二公共电极线104便可形成在所述第一栅线和所述第二栅线之间；但是，由于所述第一栅线和所述第二栅线之间的间距很小，并且还要保证所述第二公共电极线104与所述第一栅线和所述第二栅线之间相互绝缘，因此便会导致填充在二者之间的第二公共电极线104的线宽很窄，从而使其与所述辅助电极106之间形成的相对面积很小，这样便会造成形成的存储电容十分有限。In this case, the second common electrode line 104 can be formed between the first gate line and the second gate line; however, since the first gate line and the second gate line The distance between them is very small, and it is also necessary to ensure that the second common electrode line 104 is insulated from the first gate line and the second gate line, so the second grid line filled between the two The line width of the common electrode line 104 is very narrow, so that the relative area formed between it and the auxiliary electrode 106 is very small, thus resulting in a very limited storage capacitor.
基于此，优选的，所述第一公共电极线103可与所述栅线组101同层形成；所述第二公共电极线104可与所述数据线102同层形成，且与所述数据线102之间相互绝缘。Based on this, preferably, the first common electrode line 103 can be formed in the same layer as the gate line group 101; the second common electrode line 104 can be formed in the same layer as the data line 102, and can be formed in the same layer as the The wires 102 are insulated from each other.
这样一来，相比于所述第二公共电极线104与所述第一栅线和所述第二栅线同层制备的情况，所述第二公共电极线104的面积可以有所增加，以便于与所述辅助电极106之间形成相对较大的交叠区域，从而提高存储电容的大小。In this way, compared with the case where the second common electrode line 104 is prepared in the same layer as the first gate line and the second gate line, the area of the second common electrode line 104 can be increased, In order to form a relatively large overlapping area with the auxiliary electrode 106, thereby increasing the size of the storage capacitor.
需要说明的是，所述第二公共电极线104的设置应在保证与所述数据线102相互绝缘的前提下越长越好，此时，所述辅助电极106沿所述第二公共电极线104方向的尺寸应在保证不与其它导电层例如连接桥107相互接触的前提下越大越好。It should be noted that the setting of the second common electrode line 104 should be as long as possible under the premise of ensuring mutual insulation with the data line 102 . The size of the direction should be as large as possible under the premise of ensuring that it does not contact with other conductive layers such as the connection bridge 107 .
可选的，参考图1所示，所述像素单元内部还设置有薄膜晶体管108。Optionally, as shown in FIG. 1 , a thin film transistor 108 is further disposed inside the pixel unit.
具体的，所述薄膜晶体管108包括栅极、有源层、源极和漏极；所述栅极与所述第一栅线或者所述第二栅线相连，所述源极与所述数据线102相连，所述漏极与所述像素电极105相连。Specifically, the thin film transistor 108 includes a gate, an active layer, a source and a drain; the gate is connected to the first gate line or the second gate line, and the source is connected to the data The line 102 is connected, and the drain is connected to the pixel electrode 105 .
其中，相邻两个像素单元的薄膜晶体管108分别与所述第一栅线和所述第二栅线相连。Wherein, the thin film transistors 108 of two adjacent pixel units are respectively connected to the first gate line and the second gate line.
本发明的实施例还提供一种显示装置，包括对盒成型的阵列基板和彩膜基板，以及二者之间的液晶层；其中，所述阵列基板为上述的阵列基板。An embodiment of the present invention also provides a display device, including an array substrate and a color filter substrate formed in a cell, and a liquid crystal layer between them; wherein, the array substrate is the above-mentioned array substrate.
这里需要说明的是，所述显示装置可以适用于TN(TwistNematic，扭曲向列型)模式、或ADS(Advanced-super DimensionalSwitching，高级超维场转换型)模式、或IPS(In-Plane Switch，共平面切换型)模式中的任一种。It should be noted here that the display device can be adapted to TN (TwistNematic, twisted nematic) mode, or ADS (Advanced-super Dimensional Switching, advanced super-dimensional field switching type) mode, or IPS (In-Plane Switch, total plane switching type) any of the modes.
在此基础上，所述显示装置可以是液晶显示器、液晶电视、数码相框、手机、平板电脑等具有任何显示功能的产品或者部件。On this basis, the display device may be a liquid crystal display, a liquid crystal TV, a digital photo frame, a mobile phone, a tablet computer, and other products or components with any display function.
基于此，通过采用本发明的实施例提供的阵列基板制备所述显示装置，可在不影响开口率的前提下增大存储电容。从而有效的降低跳变电压，改善TFT-LCD的显示品质。Based on this, by using the array substrate provided by the embodiment of the present invention to prepare the display device, the storage capacitance can be increased without affecting the aperture ratio. Therefore, the jump voltage is effectively reduced, and the display quality of the TFT-LCD is improved.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.
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