技术领域technical field
本发明一般涉及半导体领域，并且更尤指自组装单层(self-assembled monolayer)原位(in-situ)气相沉积的方法。The present invention relates generally to the field of semiconductors, and more particularly to methods of in-situ vapor deposition of self-assembled monolayers.
背景技术Background technique
随着集成电路装置尺寸持续缩减以达到较高的操作频率、较低的功耗、以及整体较高的生产力，制造可靠的互连对于制造及效能两方面已变得日益困难。As integrated circuit device dimensions continue to shrink to achieve higher operating frequencies, lower power consumption, and overall higher productivity, making reliable interconnections has become increasingly difficult, both in terms of manufacturing and performance.
为了制造具有快操作速度的可靠装置，铜(Cu)因为其相较于铝具有较低电阻并且较不易产生电子迁移与应力迁移而正成为选用以形成互联线的材料。In order to manufacture reliable devices with fast operating speeds, copper (Cu) is becoming the material of choice for forming interconnect lines due to its lower electrical resistance and less susceptibility to electromigration and stress migration than aluminum.
然而，Cu有各种缺点。例如，Cu对SiO2及其它介电材料的粘着强度差。因此，需要可靠的扩散阻障件及助粘剂以使铜互连可实现。某些目前所使用的接口阻障层材料包括钽(Ta)、钽氮化物(TaN)以及钛(TiN)。这些层在通过习知方法予以沉积时难以形成为均匀并且连续的层件。这在所要予以沉积的层件厚度小于10纳米时以及此等层件形成如通孔(via)般呈高深宽比(aspect ratio)（例如，深度比宽度）特征时尤其真实。已知Cu/覆盖层接口会促成电子迁移(EM)故障，因此优化Cu/覆盖接口(cap interface)对于EM可靠度效能具有关键性。因此，期望具有用于形成铜助粘剂及扩散阻障件的改良型方法。However, Cu has various disadvantages. For example, Cu has poor adhesion strength toSiO2 and other dielectric materials. Therefore, reliable diffusion barriers and adhesion promoters are needed to make copper interconnections achievable. Some currently used interface barrier layer materials include tantalum (Ta), tantalum nitride (TaN), and titanium (TiN). These layers are difficult to form as uniform and continuous layers when deposited by conventional methods. This is especially true when the layers to be deposited are less than 10 nanometers thick and when the layers form high aspect ratio (eg, depth to width) features such as vias. The Cu/cap interface is known to contribute to electromigration (EM) failures, so optimizing the Cu/cap interface is critical to EM reliability performance. Accordingly, it would be desirable to have improved methods for forming copper adhesion promoters and diffusion barriers.
发明内容Contents of the invention
一般而言，本发明的具体实施例提供用于自组装单层原位气相沉积作为铜助粘剂及扩散阻障件的方法。铜区域在介电层中形成。由自组装单层制成的扩散阻障件沉积在铜区域上方。覆盖层沉积在自组装单层上方。在某些具体实施例中，覆盖层及自组装单层在相同的处理室中予以沉积。本发明的具体实施例相较于先前技术的阻障层材料可提供如制造程序期间降低不希望有的铜区域氧化风险、减少材料浪费、以及改善铜区域与覆盖层之间阻障层的粘着性及有效性等优点。In general, embodiments of the present invention provide methods for in situ vapor deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers. A copper region is formed in the dielectric layer. A diffusion barrier made of self-assembled monolayers is deposited over the copper regions. A capping layer is deposited over the self-assembled monolayer. In some embodiments, the capping layer and the self-assembled monolayer are deposited in the same process chamber. Embodiments of the present invention may provide benefits such as reduced risk of undesired copper region oxidation during the manufacturing process, reduced material waste, and improved barrier layer adhesion between copper regions and capping layers compared to prior art barrier layer materials. Advantages of sex and effectiveness.
本发明的一个态样包括形成半导体结构的方法。本方法包括在介电层中形成通孔；在通孔中形成第一阻障层；在通孔中形成铜区域；在铜区域上方沉积第二阻障层；以及在第二阻障层上方沉积覆盖层。沉积第二阻障层包括在化学气相沉积工具室中沉积自组装单层。One aspect of the invention includes a method of forming a semiconductor structure. The method includes forming a via in the dielectric layer; forming a first barrier layer in the via; forming a copper region in the via; depositing a second barrier layer over the copper region; Deposit the overlay. Depositing the second barrier layer includes depositing a self-assembled monolayer in a chemical vapor deposition tool chamber.
本发明的另一个态样包括形成半导体结构的方法。本方法包括在介电层中形成通孔；在通孔中形成第一阻障层；在通孔中形成铜区域；在铜区域上方沉积第二阻障层；以及在第二阻障层上方沉积覆盖层。沉积第二阻障层包括在原子层沉积工具室中沉积自组装单层。Another aspect of the invention includes a method of forming a semiconductor structure. The method includes forming a via in the dielectric layer; forming a first barrier layer in the via; forming a copper region in the via; depositing a second barrier layer over the copper region; Deposit the overlay. Depositing the second barrier layer includes depositing a self-assembled monolayer in an atomic layer deposition tool chamber.
本发明的另一态样包括形成半导体结构的方法。本方法包括在介电层中形成通孔；在通孔中形成第一阻障层；在通孔中形成铜区域；在铜区域上方沉积第二阻障层；以及在第二阻障层上方沉积覆盖层。沉积第二阻障层包括在等离子增强型化学气相沉积工具室中沉积自组装单层。Another aspect of the invention includes a method of forming a semiconductor structure. The method includes forming a via in the dielectric layer; forming a first barrier layer in the via; forming a copper region in the via; depositing a second barrier layer over the copper region; Deposit the overlay. Depositing the second barrier layer includes depositing a self-assembled monolayer in a plasma enhanced chemical vapor deposition tool chamber.
附图说明Description of drawings
搭配附图经由下文本发明各种态样的详述将得以更轻易地理解本发明的这些及其它特征，其中：These and other features of the present invention will be more easily understood through the following detailed description of various aspects of the invention in conjunction with the accompanying drawings, wherein:
图1表示本发明一具体实施例于起始点(starting point)的半导体结构；Fig. 1 represents the semiconductor structure of a specific embodiment of the present invention at the starting point (starting point);
图2根据描述性具体实施例表示形成通孔的后续处理步骤后的半导体结构；FIG. 2 shows the semiconductor structure after a subsequent processing step of forming vias, according to an illustrative embodiment;
图3根据描述性具体实施例表示形成第一阻障层的后续处理步骤后的半导体结构；FIG. 3 shows the semiconductor structure after a subsequent processing step of forming a first barrier layer, according to an illustrative embodiment;
图4根据描述性具体实施例表示形成铜区域的后续处理步骤后的半导体结构；FIG. 4 shows the semiconductor structure after subsequent processing steps to form copper regions, according to an illustrative embodiment;
图5根据描述性具体实施例表示形成第二阻障层的后续处理步骤后的半导体结构；FIG. 5 shows the semiconductor structure after a subsequent processing step of forming a second barrier layer, according to an illustrative embodiment;
图6根据描述性具体实施例表示形成覆盖层的后续处理步骤后的半导体结构；FIG. 6 shows the semiconductor structure after a subsequent processing step of forming a capping layer, according to an illustrative embodiment;
图7根据描述性具体实施例表示流程图；以及FIG. 7 represents a flowchart, according to an illustrative embodiment; and
图8表示用于实施描述性具体实施例的沉积工具的一部分。Figure 8 shows a portion of a deposition tool used to practice an illustrative embodiment.
图式未必依照比例。图式仅用于表述，用意不在于描绘本发明的特定参数。图式的用意在于仅描绘本发明的一般具体实施例，并且因而不应该予以视为范畴内的限制。在图式中，相称的组件符号代表相称的组件。The drawings are not necessarily to scale. The drawings are for representation only, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention and thus should not be considered as limiting in scope. In the drawings, commensurate component symbols represent commensurate components.
符号说明Symbol Description
100 半导体结构100 semiconductor structures
102 介电层102 dielectric layer
104 通孔104 through holes
106 第一阻障层106 The first barrier layer
108 铜区域108 copper area
110 第二阻障层、SAM层110 Second barrier layer, SAM layer
112 覆盖层112 Overlay
200 半导体结构200 Semiconductor structures
300 半导体结构300 semiconductor structures
400 半导体结构400 Semiconductor structures
500 半导体结构500 semiconductor structures
600 半导体结构600 Semiconductor structures
700 流程图700 flow chart
750、752、754、756、758 程序步骤750, 752, 754, 756, 758 program steps
800 沉积工具800 deposition tools
870 处理室870 processing room
872 晶圆872 wafer
874 基座874 Base
876 入气口876 air inlet
878 调节阀。878 Regulating valve.
具体实施方式Detailed ways
现在将参照附图在本文更完整地说明示例性具体实施例，其中所表示的是示例性具体实施例。本发明的示例性具体实施例提供使用原位气相沉积技术用于沉积自组装单层(SAM)薄膜(film)的方法。在某些具体实施例中，于铜区域上方形成SAM薄膜，并且依次在相同的处理室中于SAM薄膜上方形成覆盖层。这降低在制造程序期间不想要的铜氧化的风险。此外，强接口键结(interfacial bonding)可固化Cu，并且减少Cu注入ILD接口的Cu离子，从而降低时间相依性介电质崩溃(TDDB)的风险。Example embodiments will now be described more fully herein with reference to the accompanying drawings, in which example embodiments are shown. Exemplary embodiments of the present invention provide methods for depositing self-assembled monolayer (SAM) films using in-situ vapor deposition techniques. In some embodiments, a SAM film is formed over the copper region, and a capping layer is sequentially formed over the SAM film in the same process chamber. This reduces the risk of unwanted copper oxidation during the manufacturing process. In addition, strong interfacial bonding solidifies Cu and reduces Cu ions injected into the ILD interface, thereby reducing the risk of time-dependent dielectric breakdown (TDDB).
将了解本揭示可用许多不同形式予以体现并且不应该予以推断为受限于本文所提的示例性具体实施例。反而，这些具体实施例经提供以至于本揭示将透彻并且完整，并且将传达本发明的范畴予所属领域的技术人员。本文所用术语的目的仅在于说明特殊具体实施例并且意图不在于限制本揭示。例如，如本文中所用，单数形式「一」、「一种」、「一个」、以及「该」的用意在于同时包括复数形式，上下文另有所指除外。还有，「一」、「一种」、「一个」等用字未指示数量限制，而是指示存在至少一所引用的项目。将进一步理解的是，用字「包含有」及/或「包含」、或、「包括」及/或「包括有」在用于本说明书时指定所述特征、区域、完整物(integer)、步骤、操作、组件、及/或元件的存在性，而非排除一或多个其它其特征、区域、完整物、步骤、操作、组件、元件、及/或群组的存在或增加。It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these specific embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. For example, as used herein, the singular forms "a", "an", "an", and "the" are intended to include the plural forms as well unless the context dictates otherwise. Also, the terms "a", "an", "an", etc. do not indicate a limitation of quantity, but rather indicate that there is at least one of the referenced item. It will be further understood that the words "comprises" and/or "includes", or, "includes" and/or "includes" when used in this specification designate said features, regions, integers, The presence of steps, operations, components, and/or elements does not preclude the existence or addition of one or more other features, regions, integrity, steps, operations, components, elements, and/or groups thereof.
本说明书全篇对于「一具体实施例」、「一个具体实施例」、「具体实施例」、「示例性具体实施例」、或类似用语意指结合具体实施例所述的特殊特征、结构、或特性含括在本发明的至少一具体实施例中。因此，本说明书全篇的用词表现「在一具体实施例中」、「在一个具体实施例」、「在具体实施例」以及类似用语可，但不一定要，全部意指相同的具体实施例。Throughout this specification, references to "a specific embodiment," "an specific embodiment," "specific embodiment," "exemplary specific embodiment," or similar terms mean particular features, structures, structures, or characteristics are included in at least one embodiment of the invention. Thus, terms throughout this specification such as "in an embodiment," "in an embodiment," "in an embodiment," and similar terms may, but do not necessarily, all mean the same implementation. example.
用字「上覆」或「在顶上」、「置于…上」或「上置于」、「下伏」、「在下方」或「之下」意指如第一结构，例如第一层，的第一组件出现在如第二结构，例如第二层，的第二组件上，其中，如接口结构，例如接口层，的中介组件(intervening element)可出现在第一组件与第二组件之间。The use of the words "overlying" or "on top", "on" or "over", "underlying", "below" or "under" means such as a first structure, such as the first A first component of a layer appears on a second component of a second structure, such as a second layer, where an intervening element such as an interface structure, such as an interface layer, can appear between a first component and a second between components.
请再参阅图标，图1表示本发明一具体实施例于起始点的半导体结构100。半导体结构100包括介电层102。介电层102可为层间介电层(interlevel dielectric layer，ILD)。ILD可包含多个介电层以及随选地包含一或多个蚀刻中止层。Please refer to the drawings again. FIG. 1 shows a semiconductor structure 100 at the starting point of an embodiment of the present invention. The semiconductor structure 100 includes a dielectric layer 102 . The dielectric layer 102 can be an interlevel dielectric layer (ILD). The ILD may include multiple dielectric layers and optionally one or more etch stop layers.
图2表示在介电层102中形成通孔104的后续处理步骤后的半导体结构200。可使用业界标准蚀刻及微影技术形成通孔。FIG. 2 shows semiconductor structure 200 after a subsequent processing step of forming via 104 in dielectric layer 102 . The vias can be formed using industry standard etching and lithography techniques.
图3表示在通孔104内部表面上形成第一阻障层106的后续处理步骤后的半导体结构300。第一阻障层可为金属层，如基于钽的层件。第一阻障层可通过包括但不局限于物理气相沉积(PVD)、化学气相沉积(CVD)、等离子增强型化学气相沉积(PECVD)或原子层沉积(ALD)等任何适用的沉积方法予以形成。FIG. 3 shows the semiconductor structure 300 after a subsequent processing step of forming the first barrier layer 106 on the inner surface of the via 104 . The first barrier layer may be a metal layer, such as a tantalum-based layer. The first barrier layer can be formed by any suitable deposition method including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) .
图4表示形成铜区域108、填充通孔（对照图3的104）的后续处理步骤后的半导体结构400。可通过包括但不局限于电镀等任何适用的沉积方法形成铜区域108。在沉积铜区域108后，退火Cu以稳定晶体结构，并且可接着进行如化学气相抛光(CMP)等平整化程序以令铜区域108与第一阻障层106及介电层102呈平面。FIG. 4 shows semiconductor structure 400 after subsequent processing steps of forming copper regions 108 , filling vias (compare 104 of FIG. 3 ). Copper region 108 may be formed by any suitable deposition method including, but not limited to, electroplating. After the copper region 108 is deposited, the Cu is annealed to stabilize the crystal structure, and a planarization process such as chemical vapor polishing (CMP) may then be performed to make the copper region 108 planar with the first barrier layer 106 and the dielectric layer 102 .
图5表示形成第二阻障层110的后续处理步骤后的半导体结构500。第二阻障层为自组装单层(SAM)，并且经由原位气相沉积技术予以沉积。在一具体实施例中，SAM层110经由化学气相积工具予以沉积。在另一具体实施例中，SAM层110经由等离子增强型化学气相沉积工具予以沉积。在具体实施例中，SAM层110具有范围从大约10埃到大约30埃的厚度T。本发明的具体实施例可利用各种SAM，包括但不局限于氨基硅烷(amino-silane)、巯基硅烷(mercapto-silane)、具有芳香环的有机硅烷(organosilane with aromatic ring)。FIG. 5 shows the semiconductor structure 500 after a subsequent processing step of forming the second barrier layer 110 . The second barrier layer is a self-assembled monolayer (SAM) and is deposited via an in-situ vapor deposition technique. In one embodiment, the SAM layer 110 is deposited via a chemical vapor deposition tool. In another embodiment, the SAM layer 110 is deposited by a plasma enhanced chemical vapor deposition tool. In a particular embodiment, the SAM layer 110 has a thickness T ranging from about 10 Angstroms to about 30 Angstroms. Embodiments of the present invention may utilize a variety of SAMs including, but not limited to, amino-silanes, mercapto-silanes, organosilanes with aromatic rings.
可使用的某些氨基硅烷SAM包括：Some aminosilane SAMs that can be used include:
APTMS：H2NCH2CH2CH2Si(OCH3)3；APTMS: H2NCH2CH2CH2Si(OCH3)3;
APTES：H2NCH2CH2CH2Si(OC2H5)3；APTES: H2NCH2CH2CH2Si(OC2H5)3;
APDMS：(3-氨基丙基)二甲基乙氧基硅烷APDMS: (3-Aminopropyl)dimethylethoxysilane
(3-aminopropyldimethylethoxysilane)；(3-aminopropyldimethylethoxysilane);
N-(2-氨乙基)-3-氨基丙基三甲氧硅烷N-(2-aminoethyl)-3-aminopropyltrimethoxysilane
(EDA)(N-(2-aminoethyl)-3-aminopropyltrimethoxysilane)；(EDA)(N-(2-aminoethyl)-3-aminopropyltrimethoxysilane);
(3-二甲氧基甲硅烷基丙基)二乙撑三氨(3-Dimethoxysilylpropyl)diethylenetriamine
(DETA)((3-trimethoxysilylpropyl)diethylenetriamine)；(DETA)((3-trimethoxysilylpropyl)diethylenetriamine);
4-氨基苯基三甲氧硅烷(4-aminophenyltrimethoxysilane)；以及4-aminophenyltrimethoxysilane (4-aminophenyltrimethoxysilane); and
苯基氨基-甲基三甲氧基硅烷Phenylamino-methyltrimethoxysilane
(phenylamino-methyltrimethoxysilane)。(phenylamino-methyltrimethoxysilane).
可使用的某些巯基硅烷SAM包括：Some mercaptosilane SAMs that can be used include:
MPTMS：3-巯基丙基三甲氧基硅烷MPTMS: 3-Mercaptopropyltrimethoxysilane
(3-mercaptopropyltrimethoxysilane)：HS(CH2)3Si(OCH3)3；(3-mercaptopropyltrimethoxysilane): HS(CH2)3Si(OCH3)3;
MPTES：3-巯基丙基三乙氧硅烷MPTES: 3-Mercaptopropyltriethoxysilane
(3-mercaptopropyltriethoxysilane)：HS(CH2)3Si(OC2H5)3；以及MPMDMS:3-巯基丙基甲基二甲氧基硅烷(3-mercaptopropyltriethoxysilane): HS(CH2)3Si(OC2H5)3; and MPMDMS: 3-mercaptopropylmethyldimethoxysilane
(3-mercaptopropylmethyldimethoxysilane)：(3-mercaptopropylmethyldimethoxysilane):
HS(CH2)3Si(CH3)(OCH3)2。HS(CH2)3Si(CH3)(OCH3)2.
具有芳香环的有机硅烷可包括(CH2)n-Si(OCH3)3。The organosilane having an aromatic ring may include (CH2)n-Si(OCH3)3.
沉积用参数可包括范围为大约摄氏50度到大约摄氏120度的反应温度、范围从大约0.1托到大约10托的硅烷前驱物汽压、以及范围从大约1分钟到大约30分钟的反应时间。Parameters for deposition may include a reaction temperature ranging from about 50 degrees Celsius to about 120 degrees Celsius, a silane precursor vapor pressure ranging from about 0.1 Torr to about 10 Torr, and a reaction time ranging from about 1 minute to about 30 minutes.
图6表示形成覆盖层112的后续处理步骤后的半导体结构600。在具体实施例中，覆盖层112可包括硅碳化物或硅碳化物的氮化物。在具体实施例中，覆盖层112可如第二阻障层110予以在相同的室体中沉积。这由于其限制铜区域108曝露于环境空气而提供防止铜区域108上形成氧化物的优点。其它优点可包括减少产生受污染废液与聚化产物、以及有效涂布高深宽比结构。在其它具体实施例中，第一室体可用于沉积第二阻障层110并且第二室体可用于沉积覆盖层112。转移室可用于在第一与第二室体之间搬运晶圆(wafer)。在这些具体实施例中，第二阻障层110可予以沉积自原子层沉积(ALD)室、或等离子增强型ALD(PEALD)室。FIG. 6 shows the semiconductor structure 600 after a subsequent processing step of forming the capping layer 112 . In particular embodiments, capping layer 112 may include silicon carbide or a nitride of silicon carbide. In a specific embodiment, the capping layer 112 may be deposited in the same chamber as the second barrier layer 110 . This provides the advantage of preventing oxide formation on the copper region 108 as it limits the exposure of the copper region 108 to ambient air. Other advantages may include reduced generation of contaminated effluents and polymerization products, and efficient coating of high aspect ratio structures. In other embodiments, the first chamber body can be used to deposit the second barrier layer 110 and the second chamber body can be used to deposit the capping layer 112 . The transfer chamber can be used to transfer wafers between the first and second chamber bodies. In these embodiments, the second barrier layer 110 may be deposited from an atomic layer deposition (ALD) chamber, or a plasma enhanced ALD (PEALD) chamber.
图7根据描述性具体实施例表示流程图700。在程序步骤750中，形成通孔（请参阅图2的104）。在程序步骤752中，形成第一阻障区（请参阅图3的106）。在某些具体实施例，第一阻障区可为金属或金属化合物，如钽或基于钽的化合物。在其它具体实施例中，第一阻障区可包括自组装单层。在某些具体实施例中，第一阻障区可为与第二阻障区具有相同材料的材料。在程序步骤754中，形成铜区域（请参阅图5的108）。在程序步骤756中，形成第二阻障区（请参阅图5的110）。第二阻障区为自组装单层，并且使用如化学气相沉积(CVD)工具、等离子增强型化学气相沉积(PECVD)工具、ALD工具或PEALD工具之类的工具经由原位气相沉积予以沉积。在程序步骤758中，沉积覆盖层112（请参阅图6的112）。在具体实施例中，覆盖层112可包括硅碳化物或碳化物的氮化物。在具体实施例中，可在后续处理步骤中如第二阻障层110在相同室体中沉积覆盖层112。因此，在沉积第二阻障层110与沉积覆盖层112之间不用令半导体结构（例如晶圆）离开室体即可在半导体结构上沉积第二阻障层110和覆盖层112两者。FIG. 7 shows a flowchart 700 in accordance with an illustrative embodiment. In process step 750 , vias are formed (see 104 of FIG. 2 ). In program step 752 , a first barrier region is formed (see 106 of FIG. 3 ). In some embodiments, the first barrier region can be a metal or a metal compound, such as tantalum or a tantalum-based compound. In other embodiments, the first barrier region may comprise a self-assembled monolayer. In some embodiments, the first barrier region can be the same material as the second barrier region. In program step 754, copper regions are formed (see 108 of FIG. 5). In program step 756 , a second barrier region is formed (see 110 of FIG. 5 ). The second barrier region is a self-assembled monolayer and is deposited via in-situ vapor deposition using tools such as chemical vapor deposition (CVD) tools, plasma enhanced chemical vapor deposition (PECVD) tools, ALD tools or PEALD tools. In program step 758, capping layer 112 is deposited (see 112 of FIG. 6). In particular embodiments, capping layer 112 may include silicon carbide or carbide nitride. In certain embodiments, capping layer 112 may be deposited in the same chamber as second barrier layer 110 in a subsequent processing step. Thus, both the second barrier layer 110 and the capping layer 112 can be deposited on the semiconductor structure without removing the semiconductor structure (eg, wafer) from the chamber between depositing the second barrier layer 110 and depositing the capping layer 112 .
图8表示用于实施描述性具体实施例的沉积工具800的一部分。沉积工具800包括处理室870。在室体870内沉积的是由基座874所支撑的晶圆872。经由入气口876对晶圆872均匀地施加反应气体。经由调节阀878控制处理室870内的压力。通过在室体870中沉积第二阻障层110和覆盖层112两者，得以缓解铜区域108上不希望有的氧化问题（请参阅图6），从而得以改良半导体制造程序。FIG. 8 shows a portion of a deposition tool 800 used to implement an illustrative embodiment. Deposition tool 800 includes a processing chamber 870 . A wafer 872 supported by a susceptor 874 is deposited within chamber body 870 . Reactive gas is uniformly applied to the wafer 872 through the gas inlet 876 . The pressure within the processing chamber 870 is controlled via a regulator valve 878 . By depositing both the second barrier layer 110 and the capping layer 112 in the chamber body 870, the problem of undesired oxidation on the copper region 108 is alleviated (see FIG. 6), thereby improving the semiconductor manufacturing process.
在各个具体实施例中，可提供并且配置设计工具以产生用于图案化如本文所述半导体层的资料集。例如，可产生资料集以产生微影操作期间用以图案化如本文所述结构用层件的光罩。此等设计工具可包括一或多个模块的集合并且也可包括硬件、软件、或其组合。因此，举例而言，工具可为一或多个软件模块、硬件模块、软/硬件模块、或任何其组合或排列的集合。在另一实施例中，工具可为其上执行软件或硬件实现于其中的计算装置或其它器具。如本文所使用，模块可能利用硬件、软件、或其组合的任何形式予以实现。例如，可能实现一或多个处理器、控制器、特殊应用集成电路(ASIC)、可程序化逻辑阵列(PLA)、逻辑元件、软件程序、或其它机制以组成模块。在实现中，本文所述的各种模块可能予以实现成离散模块或功能并且所说明的特征可在一或多个模块之间予以部分或全部共享。换句话说，对于所述领域具有普通技术者在阅读本说明后将明显可知的是，本文所述的各种特征及功能可在任何给定的应用中予以实现并且可在一或多个分离或共享模块中以各种组合及排列予以实现。即使功能的各种特征或组件可予以单独说明或主张为分离模块，所述领域具有普通技术者仍将理解可在一或多个共通软件和硬件组件之间共享功能的这些特征，并且此说明不得需要或暗示分离的硬件或软件组件用于实现此等特征或功能。In various embodiments, a design tool can be provided and configured to generate a data set for patterning a semiconductor layer as described herein. For example, a data set can be generated to generate a reticle used to pattern a layer for a structure as described herein during a lithography operation. Such design tools may include a collection of one or more modules and may also include hardware, software, or a combination thereof. Thus, for example, a means may be a collection of one or more software modules, hardware modules, software/hardware modules, or any combination or permutation thereof. In another embodiment, a tool may be a computing device or other appliance on which software is executed or in which hardware is implemented. As used herein, a module may be implemented in any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, application specific integrated circuits (ASICs), programmable logic arrays (PLAs), logic elements, software routines, or other mechanisms may be implemented to form a module. In implementation, the various modules described herein may be implemented as discrete modules or functions and illustrated features may be shared in part or in whole among one or more modules. In other words, it will be apparent to those of ordinary skill in the art after reading this specification that the various features and functions described herein can be implemented in any given application and can be implemented in one or more separate or in shared modules in various combinations and permutations. Even though various features or components of functionality may be described separately or claimed as separate modules, those of ordinary skill in the art will understand that such features of functionality may be shared between one or more common software and hardware components and that this description No separate hardware or software components should be required or implied to implement such features or functions.
明显得知已提供用于自组装单层原位气相沉积的方法。尽管已搭配示例性具体实施例特别表示并且说明本发明，仍将了解所属领域的技术人员将想到变化及改进。例如，虽然描述性具体实施例在本文说明为一连串动作或事件，将了解本发明不受限于此等动作或事件的所示顺序，除非有明确陈述。根据本发明，某些动作可有别于本文所示及/或所述随其它动作或事件以不同顺序及/或同时出现。另外，不是所有所述步骤都可必需用以实现根据本发明的方法。另外，根据本发明的方法可关联本文所示和所述结构的形成及/或处理以及关联未示的其它结构予以实现。因此，要理解所附权利要求书的用意在于涵盖落于本发明真正精神内的所有此等改进及变更。It is apparent that a method for in situ vapor deposition of self-assembled monolayers has been provided. While the invention has been particularly shown and described with regard to exemplary embodiments thereof, it is to be understood that alterations and modifications will occur to those skilled in the art. For example, although a descriptive embodiment is described herein as a sequence of acts or events, it will be understood that the invention is not limited to the presented order of such acts or events unless expressly stated so. Certain acts may occur in a different order and/or concurrently with other acts or events than shown and/or described herein in accordance with the invention. Furthermore, not all of the described steps may be necessary to carry out the method according to the invention. Additionally, methods according to the invention may be implemented in connection with the formation and/or processing of structures shown and described herein, as well as in connection with other structures not shown. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
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| CN201310455370.XACN104517893A (en) | 2013-09-29 | 2013-09-29 | In-Situ Vapor Deposition of Self-Assembled Monolayers as Copper Adhesion Promoters and Diffusion Barriers |
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| CN201310455370.XACN104517893A (en) | 2013-09-29 | 2013-09-29 | In-Situ Vapor Deposition of Self-Assembled Monolayers as Copper Adhesion Promoters and Diffusion Barriers |
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| CN201910627579.7APendingCN110391177A (en) | 2013-09-29 | 2013-09-29 | In-Situ Vapor Deposition of Self-Assembled Monolayers as Copper Adhesion Promoters and Diffusion Barriers |
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