Bias-voltage generating circuit and liquid crystal display drive circuitTechnical field
The present invention relates to semiconductor integrated circuit, more particularly to a kind of bias-voltage generating circuit；The invention still further relates toA kind of liquid crystal display drive circuit.
Background technology
The species of liquid crystal display is relatively more, the segment encode type liquid crystal display that such as electronic watch and metering instrument field are usedDevice is exactly one kind therein. and this liquid crystal display itself has the features such as low-voltage and low-power dissipation, slab construction, life-span length to obtain extensivelyGeneral application. the low-power consumption MCU application of current metering field is it is desired to the segment encode type liquid crystal display drive circuit of more low-power consumption.
The tow sides of panel of LCD include public electrode and segmented electrode, the drive circuit of liquid crystal displayGenerally provide public (COM) signal and segmentation (SEG) the signal electrode to liquid crystal panel, by common signal to liquid crystal panelEach section has, and block signal is then given to the specific section of liquid crystal panel, is lighted by the difference of common signal and block signalOr the section corresponding to extinguishing liquid crystal panel.
Common signal includes multiple, and the waveform of multiple common signals is identical and postpones a phase bit each other, when publicWhen the number of signal is m, the type of drive of drive circuit drives (1/m Duty mode) for 1/m dutycycle.Common signal and pointThe voltage of segment signal can change, and the number of voltages of change is provided by the bias-voltage generating circuit of liquid crystal display drive circuit, biased electricalPressure generation circuit generally provides multiple equal portions magnitudes of voltage between the supply voltage and ground, and the such as timesharing in liquid crystal panel is driven toWhen carrying out 1/s bias driving (1/s Bias mode), supply voltage is divided into s equal portions, and the difference between each two voltage is electricityThe quantity of the magnitude of voltage that the 1/s of source voltage, each common signal and block signal can take is s+1.
Existing segment encode liquid crystal display drive circuit adopts existing bias-voltage generating circuit as shown in Figure 1；Bias voltage producesCircuit 101 uses a string divider resistance string to produce bias voltage, illustrate in Fig. 14 divider resistances be respectively resistance 100,101st, 102 and 103, can form 3 medium voltages between 4 divider resistances is VLC100, VLC101, VLC102, adds power supplyVoltage VLCD and ground potential can export 5 partial pressures.The switch that PMOS M100 of also having connected on divider resistance string formsPipe, control signal LIPS_B is connected to the grid of PMOS M100 and realizes the control of conducting to divider resistance string and disconnection.The partial pressure of bias-voltage generating circuit 101 is input in bias control circuit 102, and bias control circuit 102 exports common signalAnd block signal, common signal is connected to the public electrode of liquid crystal panel 103, block signal be connected to liquid crystal panel 103 pointSegment electrode.Common signal and block signal can change, thus realizing between the partial pressure of bias-voltage generating circuit 101 outputLighting or extinguish to liquid crystal display screen.There is between public electrode and segmented electrode larger electric capacity between liquid crystal display screen positive and negative,And there is larger resistance and a certain amount of leakage current can be produced, the divider resistance of the bias-voltage generating circuit 101 shown in as Fig. 1The switching rate that each signal is each common signal or block signal can be improved when value is little, driving current is big, but so bringA problem be when each signal is not changed in, the electric current of bias-voltage generating circuit 101 can a direct current it is clear that driving currentIncrease can cause the power consumption of liquid crystal display drive circuit to increase；And although the driving current reducing bias-voltage generating circuit 101 canReduce the power consumption of liquid crystal display drive circuit, but this can increase the switching time that each signal intensity is；So existing bias voltage producesCircuit 101 cannot solve the contradiction between the switching rate improving each signal and the power consumption reducing drive circuit.
Content of the invention
The technical problem to be solved is to provide a kind of bias-voltage generating circuit, enables the drive of output voltageThe change of streaming current, is applied to can to improve switching rate and the energy of each common signal or block signal during liquid crystal display drive circuitReduce the power consumption of drive circuit.For this reason, the present invention also provides a kind of liquid crystal display drive circuit.
For solving above-mentioned technical problem, the bias-voltage generating circuit that the present invention provides includes：
First bias-voltage generating circuit, including the multiple divider resistances being series between supply voltage and ground, described pointThe cascaded structure of piezoresistance carries out partial pressure and forms multiple bias voltages to described supply voltage, and described first bias voltage producesThe outfan of each described bias voltage of circuit is respectively as a bias voltage output of whole bias-voltage generating circuit.
Driving current be more than described first bias-voltage generating circuit the second bias-voltage generating circuit, including with describedThe number identical source follower circuit of bias voltage output, the outfan of each described source follower circuit connects oneDescribed bias voltage output.
Each described source follower circuit includes more than one MOS transistor source follower and more than one firstMos transistor switch；Described source follower is controlled by the break-make that clock signal controls described first mos transistor switchBeing turned on or off of circuit.
The source voltage of each described MOS transistor source follower is as the output of corresponding described source follower circuitTerminal voltage, the voltage of outfan output during each described source follower circuit conducting and described first bias-voltage generating circuitThe voltage exporting in corresponding described bias voltage output is identical；Add in the grid of each described MOS transistor source followerGrid voltage, the gate source voltage of each described MOS transistor source follower determines institute for a threshold voltage and by this gate source voltageThe conducting electric current of corresponding described source follower circuit.
During described source follower circuit conducting, the driving current of corresponding bias voltage output is inclined by described firstPut voltage generation circuit and the driving current superposition of described second bias-voltage generating circuit is formed；Described source follower circuitDuring disconnection, the driving current of corresponding bias voltage output is true by the driving current of described first bias-voltage generating circuitFixed.
Further improvement be, each described source follower circuit include two described MOS transistor source followers andTwo described first mos transistor switches, two described first mos transistor switches are respectively the first PMOS and the 4th NMOSPipe, two described MOS transistor source followers are respectively the 2nd NOMS pipe, the 3rd PMOS；Described first PMOS, described2nd NOMS pipe, described 3rd PMOS and described 4th NMOS tube are connected between the supply voltage and ground, a described PMOSThe source electrode of pipe connects described supply voltage, and the drain electrode of described first PMOS connects the drain electrode of described second NMOS tube, and described theThe source electrode of two NMOS tube is connected with the source electrode of described 3rd PMOS and this link position is as corresponding described source followerThe outfan of circuit；The drain electrode of the drain electrode of described 3rd PMOS and described 4th NMOS tube connects, described 4th NMOS tubeSource ground.
The first clock signal that the grid of described first PMOS connects and the grid of described 4th NMOS tube connect theTwo clock signals are anti-phase each other, and the grid of described second NMOS tube connects primary grid voltage, the grid of described 3rd PMOSConnect second grid voltage, corresponding described source electrode is set by arranging described primary grid voltage and described second grid voltageThe output end voltage of follower circuit.
Further improvement is that the output voltage of the bias voltage output of described bias-voltage generating circuit is input to partiallyPressure control circuit, the outfan of described bias control circuit exports multiple common signals and multiple block signal, each described publicSignal and each described block signal are input to liquid crystal panel and drive described liquid crystal panel work, each described common signal or each instituteState block signal can change between the bias voltage of each bias voltage output of described bias-voltage generating circuit respectively；In each described common signal or each described block signal change, and after each described common signal or each described block signal changeThe described source follower circuit conducting corresponding to the described bias voltage output corresponding to bias voltage, postpone a timingBetween after corresponding described source follower circuit disconnect.
Further improvement is that the size of the driving current of described second bias-voltage generating circuit meets makes each described public affairsTransformation period when signal or each described block signal change altogether narrows down to required value；Described first bias-voltage generating circuitDriving current is used for making the size of the described common signal or each described block signal that are input to described liquid crystal panel become twiceRequired value scope is maintained between change.
Further improvement is to adjust the drive of described first bias-voltage generating circuit by adjusting each described divider resistanceStreaming current size, the size of the driving current of described first bias-voltage generating circuit will can compensate the public of described liquid crystal panelThe leakage current producing between pole and segmentation pole.
Further improvement is that described first bias-voltage generating circuit also includes one second mos transistor switch, describedThe source-drain electrode of the second mos transistor switch is connected on the path of each described divider resistance, described second mos transistor switchGrid connects a control signal to control the turn-on and turn-off of described first bias-voltage generating circuit.
Further improvement is that described second bias-voltage generating circuit also includes a source follower control circuit, usesIn the break-make providing described clock signal to control described first mos transistor switch and the described MOS transistor source electrode of offerThe grid voltage of follower is controlling the output end voltage of described source follower circuit.
For solving above-mentioned technical problem, the bias-voltage generating circuit of the liquid crystal display drive circuit that the present invention provides includes：
First bias-voltage generating circuit, including the multiple divider resistances being series between supply voltage and ground, described pointThe cascaded structure of piezoresistance carries out partial pressure and forms multiple bias voltages to described supply voltage, and described first bias voltage producesThe outfan of each described bias voltage of circuit is respectively as a bias voltage output of whole bias-voltage generating circuit.
Driving current be more than described first bias-voltage generating circuit the second bias-voltage generating circuit, including with describedThe number identical source follower circuit of bias voltage output, the outfan of each described source follower circuit connects oneDescribed bias voltage output.
Each described source follower circuit includes more than one MOS transistor source follower and more than one firstMos transistor switch；Described source follower is controlled by the break-make that clock signal controls described first mos transistor switchBeing turned on or off of circuit.
The source voltage of each described MOS transistor source follower is as the output of corresponding described source follower circuitTerminal voltage, the voltage of outfan output during each described source follower circuit conducting and described first bias-voltage generating circuitThe voltage exporting in corresponding described bias voltage output is identical；Add in the grid of each described MOS transistor source followerGrid voltage, the gate source voltage of each described MOS transistor source follower determines institute for a threshold voltage and by this gate source voltageThe conducting electric current of corresponding described source follower circuit.
During described source follower circuit conducting, the driving current of corresponding bias voltage output is inclined by described firstPut voltage generation circuit and the driving current superposition of described second bias-voltage generating circuit is formed；Described source follower circuitDuring disconnection, the driving current of corresponding bias voltage output is true by the driving current of described first bias-voltage generating circuitFixed.
Further improvement is that the output voltage of the bias voltage output of described bias-voltage generating circuit is input to partiallyPressure control circuit, the outfan of described bias control circuit exports multiple common signals and multiple block signal, each described publicSignal and each described block signal are input to liquid crystal panel and drive described liquid crystal panel work, each described common signal or each instituteState block signal can change between the bias voltage of each bias voltage output of described bias-voltage generating circuit respectively；In each described common signal or each described block signal change, and after each described common signal or each described block signal changeThe described source follower circuit conducting corresponding to the described bias voltage output corresponding to bias voltage, postpone a timingBetween after corresponding described source follower circuit disconnect.
The bias-voltage generating circuit of the present invention includes two-way, and the first bias-voltage generating circuit is formed point by resistance stringPressure, the second bias-voltage generating circuit is formed and exported and resistance string partial pressure identical partial pressure by multiple source follower circuit,Source follower circuit can be to form big driving current, is in series with mos transistor switch on source follower circuit, leads toCross the turn-on and turn-off that mos transistor switch can control source follower circuit, the energy when the conducting of source follower circuitSo that the driving current of corresponding bias voltage output is increased, corresponding biased electrical can be made when the disconnection of source follower circuitThe driving current of pressure outfan is reduced to the level of the first bias-voltage generating circuit, so the present invention enables output voltageThe change of driving current.
When circuit of the present invention is applied to liquid crystal display drive circuit, each signal of liquid crystal display drive circuit be each common signal orThe second bias-voltage generating circuit conducting is made to be capable of switching under large-drive-current, so as to improve during block signal changeThe switching rate of each signal.And when each signal is not changed in, the second bias-voltage generating circuit disconnects, the magnitude of voltage of each signalOnly kept by the first bias-voltage generating circuit, the driving current of less first bias-voltage generating circuit can reduce drivingThe power consumption of circuit.
Brief description
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the structural representation of existing bias-voltage generating circuit；
Fig. 2 is the structural representation of embodiment of the present invention bias-voltage generating circuit；
Fig. 3 is the structural representation of the source follower circuit of present pre-ferred embodiments bias-voltage generating circuit；
Fig. 4 is the common signal of the liquid crystal display drive circuit using embodiment of the present invention circuit under timing control signalOutput waveform diagram.
Specific embodiment
As shown in Fig. 2 being the structural representation of embodiment of the present invention bias-voltage generating circuit；The embodiment of the present invention biasesVoltage generation circuit includes：
First bias-voltage generating circuit 1, including the multiple divider resistances being series between supply voltage VLCD and ground, schemesShow four divider resistances in 2 and be respectively labeled as divider resistance R0, R1, R2 and R3；The cascaded structure of described divider resistancePartial pressure is carried out to described supply voltage VLCD and forms multiple bias voltages, in Fig. 2, show four bias voltages labelling respectivelyFor bias voltage VLC0, VLC1, VLC2 and VLC3, wherein bias voltage VLC0 takes the size of supply voltage VLCD；Bias voltageVLC1, VLC2 and VLC3 are respectively the voltage at divider resistance R0, R1, R2 and R3 link position.Described first bias voltage producesThe outfan of each described bias voltage of raw circuit 1 is respectively as a bias voltage output of whole bias-voltage generating circuitEnd.
Driving current be more than described first bias-voltage generating circuit 1 the second bias-voltage generating circuit 2, including and instituteState the number identical source follower circuit 3 of bias voltage output, the outfan of each described source follower circuit 3 connectsOne described bias voltage output.
Each described source follower circuit 3 includes more than one MOS transistor source follower and more than one firstMos transistor switch；Described source follower is controlled by the break-make that clock signal controls described first mos transistor switchBeing turned on or off of circuit 3.
The voltage of outfan output during each described source follower circuit 3 conducting and described first bias voltage produce electricityThe voltage that road 1 exports in corresponding described bias voltage output is identical, the output end voltage of described source follower circuit 3 andThe grid voltage being added in the grid of described MOS transistor source follower differs a gate source voltage, and this gate source voltage is by describedThe conducting electric current of source follower circuit 3 determines.
During described source follower circuit 3 conducting, the driving current of corresponding bias voltage output is inclined by described firstPut voltage generation circuit 1 and the driving current superposition of described second bias-voltage generating circuit 2 is formed；Described source follower electricityThe driving current of corresponding bias voltage output when disconnecting in road 3 is by the driving electricity of described first bias-voltage generating circuit 1Stream determines.
As shown in figure 3, being that the structure of the source follower circuit of present pre-ferred embodiments bias-voltage generating circuit is shownIt is intended to；Each described source follower circuit 3 includes two described MOS transistor source followers and two described MOS are brilliantBody pipe switchs, and two described first mos transistor switches are respectively the first PMOS M1 and the 4th NMOS tube M4, described in twoMOS transistor source follower is respectively the 2nd NOMS pipe M2, the 3rd PMOS M3；Described first PMOS M1, described secondNOMS pipe M2, described 3rd PMOS M3 and described 4th NMOS tube M4 are connected between supply voltage VLCD and ground, and describedThe source electrode of one PMOS M1 connects described supply voltage VLCD, and the drain electrode of described first PMOS M1 connects described second NMOS tubeThe drain electrode of M2, the source electrode of described second NMOS tube M2 is connected with the source electrode of described 3rd PMOS M3 and this link position is as rightThe outfan of the described source follower circuit 3 answered；The drain electrode of described 3rd PMOS M3 and the leakage of described 4th NMOS tube M4Pole connects, the source ground of described 4th NMOS tube M4.
The first clock signal clk that the grid of described first PMOS M1 connects and the grid of described 4th NMOS tube M4 connectSecond clock signal/the CLK connecing is anti-phase each other, and the grid of described second NMOS tube M2 connects primary grid voltage VB1, and described theThe grid of three PMOS M3 connects second grid voltage VB2, by arranging described primary grid voltage VB1 and described second gridVoltage VB2 arranges the output end voltage of corresponding described source follower circuit 3.
Described second bias-voltage generating circuit 2 also includes a source follower control circuit 4, for providing described clockSignal is electric come the break-make to control described first mos transistor switch and the grid providing described MOS transistor source followerPress and to control the output end voltage of described source follower circuit 3.When described source follower circuit adopt as shown in Figure 3 relativelyDuring good embodiment, described source follower control circuit 4 is used for providing described first clock signal clk, described second clockSignal/CLK, described primary grid voltage VB1 and described second grid voltage VB2.
In the embodiment of the present invention, described bias-voltage generating circuit is used for realizing the driving to liquid crystal panel 6, and as liquidA part for brilliant drive circuit, will realize the driving to liquid crystal panel 6, also include following circuit structure：
The output voltage of the bias voltage output of described bias-voltage generating circuit is input to bias control circuit 5, instituteThe outfan stating bias control circuit 5 exports multiple common signals and multiple block signal, each described common signal and each describedBlock signal is input to liquid crystal panel 6 and drives described liquid crystal panel 6 to work；Wherein said common signal is input to described liquid crystalThe public electrode of panel 6, described block signal are input to the segmented electrode of described liquid crystal panel, the segmentation of described liquid crystal panel 6Electrode and public electrode are located at the tow sides of liquid crystal panel 6, by being powered up in described segmented electrode and described public electrodePressure difference makes the liquid crystal of respective segments light or extinguish.
Described segmented electrode and described public electrode institute making alive are with corresponding described common signal or described block signalChange and change, each described common signal or each described block signal can be each in described bias-voltage generating circuit respectivelyChange between the bias voltage of bias voltage output；In each described common signal or each described block signal change, and respectivelyCorresponding to the described bias voltage output corresponding to bias voltage after described common signal or each described block signal changeDescribed source follower circuit 3 turn on, postpone certain time after corresponding described source follower circuit 3 disconnect.
The larger electric capacity of ratio is had, when segmented electrode and public affairs between the segmented electrode of described liquid crystal panel 6 and public electrodeIf the driving current of described bias-voltage generating circuit is too little, when segmented electrode and public affairs when the current potential of common electrode needs to changeThe change of the current potential of common electrode needs longer time, and is produced by adding described second bias voltage in the embodiment of the present inventionRaw circuit 2, and make each described common signal by making the size of the driving current of described second bias-voltage generating circuit 2 meetOr transformation period during each described block signal change narrows down to required value；Namely the present invention passes through to add described second biased electricalAfter pressure produces circuit 2, transformation rate can be increased in the change of segmented electrode and the current potential of public electrode.
In addition, being not completely insulated between the segmented electrode of described liquid crystal panel 6 and public electrode, but there is oneThe larger resistance of ratio, so have certain electric leakage；Each described common signal or each described block signal namely each described segmentationAfter the completion of the change in voltage of electrode and described public electrode, if right to each described segmented electrode and the offer of described public electrodeThe driving current answered compensating the electric leakage between two electrodes, then between corresponding described segmented electrode and described public electrodeVoltage difference can reduce, thus affecting the display of liquid crystal.In the embodiment of the present invention, in each described segmented electrode and described public electrodeThe voltage maintenance stage can turn off having compared with described second bias-voltage generating circuit 2 of large-drive-current, and only with instituteStating the first bias-voltage generating circuit 1 provides driving current, in the embodiment of the present invention, described first bias-voltage generating circuit 1Driving current be used for make to be input to the described common signal of described liquid crystal panel 6 or the size of each described block signal twiceRequired value scope, namely the driving of described first bias-voltage generating circuit 1 in the embodiment of the present invention is maintained between changeElectric current is mainly used in compensating the electric leakage between each described segmented electrode and described public electrode, makes corresponding each described segmented electrodeMaintain required value with the current potential of described public electrode.It is to adjust institute by adjusting each described divider resistance in the embodiment of the present inventionState the driving current size of the first bias-voltage generating circuit 1, the driving current of described first bias-voltage generating circuit 1 bigThe little leakage current that will can compensate generation between the public pole of described liquid crystal panel 6 and segmentation pole.
Described first bias-voltage generating circuit 1 also includes one second mos transistor switch, described second MOS transistorThe source-drain electrode of switch is connected on the path of each described divider resistance, and the grid of described second mos transistor switch connects a controlSignal processed is controlling the turn-on and turn-off of described first bias-voltage generating circuit 1.Second mos transistor switch described in Fig. 2Using PMOS M0, described PMOS M0 is serially connected between supply voltage VLCD and divider resistance R0, i.e. described PMOS M0Source electrode meets described supply voltage VLCD, drain electrode connects described divider resistance R0, grid connects control signal LIPS_B；Believed by controllingNumber LIPS_B realizes to the conducting of divider resistance string and the control of disconnection.Certainly in other embodiments, described PMOS M0Can be serially connected in the other positions of divider resistance string；Or described PMOS M0 also can be replaced using NMOS tube, here just notEnumeration again.
The common electrical number of poles of described liquid crystal panel is 4, described common signal is being driven to of described liquid crystal panel when 41/4 dutycycle drives；The number of the described bias voltage output of described bias-voltage generating circuit is 4, described liquid crystal panelBe driven to 1/3 bias drive；Now with the mode of operation of liquid crystal drive for 1/3BIAS be 1/3 bias drive, 1/4DUTY is 1/4To embodiment of the present invention circuit to the described common signal being exported or described block signal as a example the pattern that dutycycle drivesChange is described as follows：
As shown in figure 4, being the common signal of the liquid crystal display drive circuit using embodiment of the present invention circuit in sequencing controOutput waveform diagram under signal；
When described control signal LIPS_B is low level, described first bias-voltage generating circuit 1 turns on and starts to provide 4Individual bias voltage, four being taken in Fig. 4 bias voltage is respectively VLC0, VLC1, VLC3 and 0；Described first clock signal clkTurn on for low level, described second clock signal/CLK second bias-voltage generating circuit 2 described in during high level, described secondBias-voltage generating circuit 2 provides stronger driving current；A common signal COM0 is listed in Fig. 4；Other common signalsBut curve phase place identical with common signal COM0 different, the change of block signal is also similar with common signal COM0, instituteOnly to illustrate it can be seen that described control signal LIPS_B is as low level in Fig. 4 taking the curve of common signal COM0 as a exampleAfterwards, described common signal COM0 produce change when when rise or fall as described in the first clock signal clk can form a fixed widthThe low level pulse of degree, and described second clock signal/CLK can form the high level pulse of one fixed width, t0 in such as Fig. 4,Shown in position corresponding to t1, t2 and t3, the rate of change so enabling to described common signal COM0 is accelerated；And work as describedAfter the change of common signal COM0 terminates, described first clock signal clk switches back into high level, described second clock signal/CLKSwitch back into low level, described second bias-voltage generating circuit 2 is closed.Described common signal COM0 only biases by described firstVoltage generation circuit 1 is powered, and can substantially reduce the power consumption of circuit.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present inventionSystem.Without departing from the principles of the present invention, those skilled in the art also can make many deformation and improve, and these also shouldIt is considered as protection scope of the present invention.