技术领域technical field
本发明是有关于一种存储器系统及偏压存储器的方法，且特别是有关于一种非易失性存储器系统及偏压非易失性存储器的方法。The present invention relates to a memory system and a method of biasing a memory, and more particularly to a nonvolatile memory system and a method of biasing a nonvolatile memory.
背景技术Background technique
非易失性存储器装置（如快闪存储器）已广泛地使用于多种电子应用中。一般而言，非易失性存储器应确保100,000次或更多的程序化及抹除周期。在多次程序化及抹除周期之后，非易失性存储器的指定区块将被穿隧氧化层的退化（Tunnel Oxide Degradation）磨耗，其产生低转导（Transconductance，gm）值的存储单元。为了抹除确定（Erase Verify）这些低转导值的存储单元至目标临界电压VT，需要更多的抹除脉冲，其导致存储单元会过分抹除（over-erased）。Non-volatile memory devices, such as flash memory, have been widely used in a variety of electronic applications. In general, a non-volatile memory should ensure 100,000 or more program and erase cycles. After multiple program and erase cycles, a given block of non-volatile memory will be worn down by Tunnel Oxide Degradation, which results in memory cells with low transconductance (gm) values. In order to erase these low transconductance memory cells to the target threshold voltage VT , more erase pulses are required, which causes the memory cells to be over-erased.
为了将过分抹除的存储单元降至最低，非易失性存储器装置可在抹除之前执行一预程序化动作，而在抹除之后执行一抹除后程序化（Post Program）动作。抹除之后的抹除后程序化动作将恢复过分抹除的存储单元到正临界电压VT范围。但是，倘若已被过分抹除的存储单元远远超出抹除后程序化能力，抹除后程序化动作则可能会失败。In order to minimize over-erased memory cells, the non-volatile memory device may perform a pre-program operation before erasing, and perform a post-erase program (Post Program) operation after erasing. A post-erase programming operation after erasing will restore over-erased memory cells to the positive threshold voltage VT range. However, if the memory cells that have been erased far exceed the post-erase programming capability, the post-erase programming operation may fail.
随着技术精简以及抹除区块的尺寸增加，逐位元（bit-by-bit，BbB）抹除后程序化动作已被引进，其容许较低的栅极电压Vg及正常漏极电压Vd。但是，即使采用逐位元（BbB）抹除后程序化动作时，如果临界电压窗过大而高位元线漏电存在的话。随着程序化及抹除周期会增加，如何改善具有不同偏压机制的抹除后程序化功能成为各方研究重点之一。With technology downsizing and erase block size increasing, bit-by-bit (BbB) post-erase programming has been introduced, which allows lower gate voltage Vg and normal drain voltage Vd . However, even when bit-by-bit (BbB) post-erase programming is used, if the threshold voltage window is too large and high bit line leakage exists. As the programming and erasing cycles will increase, how to improve the programming function after erasing with different bias mechanisms has become one of the research focuses.
发明内容Contents of the invention
本发明提供一种非易失性存储器系统，以及一种偏压非易失性存储器的方法。The present invention provides a nonvolatile memory system and a method of biasing the nonvolatile memory.
本发明的非易失性存储器系统，包括存储器单元阵列及偏压电路。存储器单元阵列包括多个位元线、多个字元线与多个耦接至位元线及字元线的储存单位。偏压电路耦接至存储器单元阵列。偏压电路包括控制器及偏压产生器。控制器控制存储器单元阵列的动作，且控制器更用以在一抹除周期后对存储器单元阵列进行一抹除确认动作。其中，当存储器单元阵列的至少一部份未通过抹除确认动作时，控制器产生一控制信号且传送控制信号至偏压产生器。偏压产生器与控制器耦接。偏压产生器提供一第一电压至存储器单元阵列，直至偏压产生器接收到从控制器传送的控制信号为止。当偏压产生器接收从控制器的控制信号时，偏压产生器根据控制信号，增加提供至存储器单元阵列的第一电压至一第二电压。The non-volatile memory system of the present invention includes a memory cell array and a bias circuit. The memory cell array includes a plurality of bit lines, a plurality of word lines and a plurality of storage units coupled to the bit lines and the word lines. The bias circuit is coupled to the memory cell array. The bias circuit includes a controller and a bias generator. The controller controls the action of the memory cell array, and the controller is further used for performing an erase confirmation action on the memory cell array after an erasing cycle. Wherein, when at least a part of the memory cell array fails to pass the erase confirmation operation, the controller generates a control signal and sends the control signal to the bias voltage generator. The bias generator is coupled to the controller. The bias voltage generator provides a first voltage to the memory cell array until the bias voltage generator receives a control signal transmitted from the controller. When the bias voltage generator receives a control signal from the controller, the bias voltage generator increases the first voltage provided to the memory cell array to a second voltage according to the control signal.
本发明的偏压包含存储器单元阵列的非易失性存储器之方法，包括下列步骤。在非易失性存储器的一抹除周期后，通过使用非易失性存储器的偏压电路中的控制器，初始化一地址计数值及一失败计数值。然后，对存储器单元阵列进行一抹除确认动作。当存储器单元阵列的至少一部份未通过抹除确认动作时，产生一控制信号且传送控制信号至偏压电路中的偏压产生器。接着，提供一第一电压至存储器单元阵列，直至偏压产生器接收到该控制信号为止。当偏压产生器接收从控制器的控制信号时，根据控制信号，增加提供至存储器单元阵列的第一电压至一第二电压。The method of biasing a nonvolatile memory comprising a memory cell array of the present invention includes the following steps. After an erase cycle of the nonvolatile memory, an address count and a fail count are initialized by using the controller in the bias circuit of the nonvolatile memory. Then, perform an erase confirmation operation on the memory cell array. When at least a part of the memory cell array fails the erase confirmation operation, a control signal is generated and sent to the bias generator in the bias circuit. Then, provide a first voltage to the memory cell array until the bias voltage generator receives the control signal. When the bias voltage generator receives a control signal from the controller, it increases the first voltage provided to the memory cell array to a second voltage according to the control signal.
基于上述，根据本发明的上述实施例，本发明之非易失性存储器系统及偏压非易失性存储器的方法采用不同偏压机制，以紧缩确认电压电平及减少位元线的漏电流，因而可避免程序化失败，且延长非易失性存储器的寿命。Based on the above, according to the above-mentioned embodiments of the present invention, the non-volatile memory system and the method of biasing the non-volatile memory of the present invention adopt different biasing mechanisms to tighten the confirmation voltage level and reduce the leakage current of the bit line , thus avoiding programming failure and prolonging the lifetime of the non-volatile memory.
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
附图说明Description of drawings
图1A为传统非易失性存储器中全新存储器单元的临界电压分布窗的示意图。FIG. 1A is a schematic diagram of a threshold voltage distribution window of a new memory cell in a conventional nonvolatile memory.
图1B为传统非易失性存储器中存储器单元经数个抹除周期后的临界电压分布窗的示意图。FIG. 1B is a schematic diagram of a threshold voltage distribution window of a memory cell in a conventional non-volatile memory after several erasing cycles.
图2为依照本发明一实施例的非易失性存储器系统的示意图。FIG. 2 is a schematic diagram of a non-volatile memory system according to an embodiment of the invention.
图3为依照本发明一实施例的非易失性存储器系统的示意图。FIG. 3 is a schematic diagram of a non-volatile memory system according to an embodiment of the invention.
图4为依照本发明一实施例的非易失性存储器系统的感测放大器的示意图。FIG. 4 is a schematic diagram of a sense amplifier of a non-volatile memory system according to an embodiment of the invention.
图5A为传统非易失性存储器中存储器单元经数个抹除周期后的临界电压分布窗的示意图。FIG. 5A is a schematic diagram of a threshold voltage distribution window of a memory cell in a conventional non-volatile memory after several erasing cycles.
图5B为依照本发明一实施例的非易失性存储器系统中存储器单元的临界电压分布窗的示意图。FIG. 5B is a schematic diagram of threshold voltage distribution windows of memory cells in a nonvolatile memory system according to an embodiment of the invention.
图6为依照本发明一实施例的偏压非易失性存储器的方法的流程图。FIG. 6 is a flowchart of a method for biasing a nonvolatile memory according to an embodiment of the invention.
其中，附图标记说明如下：Wherein, the reference signs are explained as follows:
200、300：非易失性存储器系统200, 300: Non-volatile memory systems
210：偏压电路210: Bias circuit
220：控制器220: Controller
230：偏压产生器230: Bias generator
240：存储器单元阵列240: memory cell array
311：处理器311: Processor
312：指定晶体管312: Specified Transistor
313：存储器单元313: memory unit
321：位元线偏压产生器321: Bit line bias generator
322：字元线偏压产生器322: word line bias voltage generator
400：感测放大器400: sense amplifier
410：第一负载410: first load
420：第二负载420: second load
430：主要单元430: Main Unit
440：参考单元440: Reference Unit
CTRL：控制信号CTRL: control signal
FC：失败计数值FC: Failure count value
I：主要单元电流I: main unit current
I’：参考单元电流I': reference cell current
VT：临界电压VT : critical voltage
WL：共用字元线WL: shared word line
S610～S690：偏压非易失性存储器的方法的各步骤S610-S690: each step of the method for biasing the non-volatile memory
具体实施方式Detailed ways
现将详细参考本发明之示范性实施例，在附图中说明所述示范性实施例之实例。另外，凡可能之处，在图式及实施方式中使用相同标号的元件/构件/符号代表相同或类似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In addition, wherever possible, elements/components/symbols with the same reference numerals are used in the drawings and embodiments to represent the same or similar parts.
图1A为传统非易失性存储器中全新存储器单元的临界电压分布窗的示意图。请参照图1A，横轴代表传统非易失性存储器中多个存储器单元的临界电压（ThresholdVoltage，VT），而纵轴代表存储器单元的数量。另外，虚线曲线代表于一抹除周期后存储器单元的临界电压VT分布窗（Distribution Window），实线曲线表示于一抹除周期后传统抹除后程序化动作所造成的临界电压VT分布窗，而两垂直实线代表临界电压VT分布窗之下界。图1B为传统非易失性存储器中存储器单元经数个抹除周期后的临界电压分布窗的示意图。如图1B所示，相较于图1A，由于低转导值（gm）的存储单元，经数个抹除周期后存储器单元所表示的虚线曲线已变得较宽。另外，由于传统非易失性存储器中的高位元线漏电，经数个抹除周期后的抹除后程序化时间亦变得较长。因此，倘若因栅极低电压或漏极低电压而导致抹除后程序化的功能不足的话，非易失性存储器中的存储器单元就无法达到目标临界电压VT。FIG. 1A is a schematic diagram of a threshold voltage distribution window of a new memory cell in a conventional nonvolatile memory. Referring to FIG. 1A , the horizontal axis represents the threshold voltage (ThresholdVoltage, VT ) of multiple memory cells in a conventional non-volatile memory, and the vertical axis represents the number of memory cells. In addition, the dotted curve represents the critical voltage VT distribution window (Distribution Window) of the memory cell after an erase cycle, and the solid line curve represents the critical voltage VT distribution window caused by the conventional post-erase programming operation after an erase cycle. The two vertical solid lines represent the lower bound of the threshold voltage VT distribution window. FIG. 1B is a schematic diagram of a threshold voltage distribution window of a memory cell in a conventional non-volatile memory after several erasing cycles. As shown in FIG. 1B , compared to FIG. 1A , due to the low gm value of the memory cell, the dotted curve indicated by the memory cell has become wider after several erase cycles. In addition, due to the high bit line leakage in the traditional non-volatile memory, the post-erase programming time after several erase cycles also becomes longer. Therefore, if the post-erase programming function is insufficient due to low gate voltage or low drain voltage, the memory cells in the nonvolatile memory cannot reach the target threshold voltage VT .
如图1A与图1B所示，因抹除后程序化动作后，介于图1A（全新存储单元）与图1B（循环之后）间的临界电压VT分布窗的实际下界相同，额外的寄生问题则会发生在传统非易失性存储器中。然而，相较于图1A，更多在传统非易失性存储器中的存储器单元分布于图1B的下界附近。因此，在传统非易失性存储器中，未指定存储器单元上的截止电流（OffCurrent）在循环后将会增加。当程序化非易失性存储器时，由于耦接至浮置栅极的非易失性存储器的位元线漏电的产生，截止电流被称为漏极导通电流（Drain Turn-On Current）。据此，随着抹除周期的增加，应紧缩确认电压电平，以便降低漏电流来避免抹除后程序化动作之后程序化失败，并且临界电压VT分布窗会变成接近于图1A所示的全新存储器单元状态。As shown in Figure 1A and Figure 1B, since the actual lower bound of the threshold voltage VT distribution window between Figure 1A (new memory cell) and Figure 1B (after cycling) after the post-erase programming operation is the same, the additional parasitic The problem occurs in traditional non-volatile memory. However, compared to FIG. 1A , more memory cells in a conventional nonvolatile memory are distributed near the lower boundary of FIG. 1B . Therefore, in conventional non-volatile memory, the off-current (OffCurrent) on unspecified memory cells will increase after cycling. When programming the nonvolatile memory, the off-current is called drain turn-on current (Drain Turn-On Current) due to the bit line leakage of the nonvolatile memory coupled to the floating gate. Accordingly, as the erasing cycle increases, the confirmation voltage level should be tightened to reduce the leakage current to avoid programming failure after the erasing programming operation, and the threshold voltage VT distribution window will become close to that shown in Figure 1A The new memory cell state of .
图2为依照本发明一实施例的非易失性存储器系统的示意图。请参照图2，依照本发明一实施例的非易失性存储器系统200包括偏压电路210及存储器单元阵列240。偏压电路210包括控制器220及偏压产生器230。存储器单元阵列240可包括多个位元线、多个字元线与多个耦接至位元线及字元线的非易失性储存单位。为了清楚起见，非易失性存储器系统200的其他构件，例如行/列控制电路、状态机及指令电路并未绘示于图中。在本实施例中，控制器220适用于控制存储器单元阵列240的动作。另外，控制器220用以在一抹除周期后对存储器单元阵列240进行一抹除确认动作，其中当存储器单元阵列240的至少一部份未通过抹除确认动作时，控制器220产生一控制信号CTRL且传送控制信号CTRL至偏压产生器230。偏压产生器230与控制器220耦接。偏压产生器230提供第一电压至存储器单元阵列240，直至偏压产生器230接收到从控制器220传送的控制信号CTRL接收为止。而当偏压产生器230接收到控制器220的控制信号CTRL时，偏压产生器230根据控制信号CTRL，增加提供至存储器单元阵列240的第一电压至一第二电压。FIG. 2 is a schematic diagram of a non-volatile memory system according to an embodiment of the invention. Referring to FIG. 2 , a nonvolatile memory system 200 according to an embodiment of the present invention includes a bias circuit 210 and a memory cell array 240 . The bias circuit 210 includes a controller 220 and a bias generator 230 . The memory cell array 240 may include a plurality of bit lines, a plurality of word lines, and a plurality of nonvolatile storage units coupled to the bit lines and the word lines. For the sake of clarity, other components of the nonvolatile memory system 200, such as row/column control circuits, state machines and command circuits, are not shown in the figure. In this embodiment, the controller 220 is adapted to control the actions of the memory cell array 240 . In addition, the controller 220 is used to perform an erase confirmation operation on the memory cell array 240 after an erase cycle, wherein when at least a part of the memory cell array 240 fails the erase confirmation operation, the controller 220 generates a control signal CTRL And transmit the control signal CTRL to the bias voltage generator 230 . The bias voltage generator 230 is coupled to the controller 220 . The bias voltage generator 230 provides the first voltage to the memory cell array 240 until the bias voltage generator 230 receives the control signal CTRL transmitted from the controller 220 . And when the bias voltage generator 230 receives the control signal CTRL of the controller 220, the bias voltage generator 230 increases the first voltage provided to the memory cell array 240 to a second voltage according to the control signal CTRL.
图3为依照本发明一实施例的非易失性存储器系统的示意图。请参照图3，在本实施例的非易失性存储器系统300中，控制器220可包括处理器311及储存媒体（未绘示）。处理器311可以根据储存于控制器220之储存媒体的程序码，适用于执行偏压非易失性存储器系统300的方法。另外，虽然在本发明的其他实施例中，偏压产生器230可能仅有位元线偏压产生器321或字元线偏压产生器322，但是偏压产生器230可以包括位元线偏压产生器321及字元线偏压产生器322。在本实施例中，位元线偏压产生器321与存储器单元阵列240的至少一位元线耦接。当后程序化时，位元线偏压产生器321根据控制信号CTRL，提供第二电压至存储器单元阵列240的该至少一位元线（例如，指定晶体管312）。字元线偏压产生器322与存储器单元阵列240的至少一字元线耦接。字元线偏压产生器322根据控制信号CTRL，提供第二电压至存储器单元阵列240的该至少一字元线（例如，存储器单元313）。在本发明的一实施例中，于每一周期内，存储器单元阵列240的部份未通过抹除确认动作时，控制器220中的处理器311分别增进一失败计数值（Fail Count(FC)），例如处理器311所产生的内部计数值（未绘示），且处理器311根据失败计数值FC产生控制信号CTRL。FIG. 3 is a schematic diagram of a non-volatile memory system according to an embodiment of the invention. Referring to FIG. 3 , in the nonvolatile memory system 300 of this embodiment, the controller 220 may include a processor 311 and a storage medium (not shown). The processor 311 can be adapted to execute the method of the bias nonvolatile memory system 300 according to the program code stored in the storage medium of the controller 220 . In addition, although in other embodiments of the present invention, the bias generator 230 may only have the bit line bias generator 321 or the word line bias generator 322, but the bias generator 230 may include a bit line bias generator Voltage generator 321 and word line bias generator 322. In this embodiment, the bit line bias generator 321 is coupled to at least one bit line of the memory cell array 240 . When post-programming, the bit line bias generator 321 provides a second voltage to the at least one bit line of the memory cell array 240 (eg, the designated transistor 312 ) according to the control signal CTRL. The word line bias generator 322 is coupled to at least one word line of the memory cell array 240 . The word line bias generator 322 provides a second voltage to the at least one word line (eg, the memory cell 313 ) of the memory cell array 240 according to the control signal CTRL. In one embodiment of the present invention, in each cycle, when part of the memory cell array 240 fails to pass the erase confirmation action, the processor 311 in the controller 220 increases a failure count value (Fail Count (FC) ), such as an internal count value (not shown) generated by the processor 311, and the processor 311 generates the control signal CTRL according to the failure count value FC.
图4为依照本发明一实施例的非易失性存储器系统的感测放大器的示意图。请参照图4，本实施例的感测放大器400耦接于第一负载410与第二负载420之间。其中，第一负载410与第二负载420分别与存储器单元阵列240之主要单元430及参考单元440耦接。在本实施例中，根据失败计数值FC，调整第一负载410对第二负载420的一负载比率。通过调整感测放大器400的负载，可紧缩存储器单元阵列240的确认电压电平，且可减少位元线漏电流。在一示范例子（如图4所示）中，假设在抹除后程序化确认读取动作期间，第二负载420为第一负载410的一半，而主要单元430及参考单元440将具有共用字元线WL。随着后程序化次数增加，主要单元电流I增加参考单元电流I’的一半。因此，当字元线电压增加时，主要单元430在确认读取动作期间所需的电流少于参考单元440，其造成推挤VT分布窗的下界高于全新存储器单元，绘示于图5B中。相较于图5A（其为传统非易失性存储器中存储器单元经数个抹除周期后的临界电压VT分布窗的示意图），图5B显示出临界电压VT分布窗的下界在本实施例的抹除后程序化动作后明显较高。FIG. 4 is a schematic diagram of a sense amplifier of a non-volatile memory system according to an embodiment of the invention. Referring to FIG. 4 , the sense amplifier 400 of this embodiment is coupled between the first load 410 and the second load 420 . Wherein, the first load 410 and the second load 420 are respectively coupled to the main unit 430 and the reference unit 440 of the memory cell array 240 . In this embodiment, a load ratio of the first load 410 to the second load 420 is adjusted according to the failure count value FC. By adjusting the load of the sense amplifier 400, the verification voltage level of the memory cell array 240 can be tightened, and the bit line leakage current can be reduced. In an exemplary example (as shown in FIG. 4 ), assuming that during the post-erase program verify read operation, the second load 420 is half of the first load 410, and the main cell 430 and the reference cell 440 will have a common word Element Line WL. As the number of post-programming increases, the primary cell current I increases by half of the reference cell current I'. Therefore, as the word line voltage increases, the main cell 430 requires less current than the reference cell 440 during the assert read operation, which causes the lower bound of theVT distribution window to be pushed above the fresh memory cell, as shown in FIG. 5B middle. Compared with FIG. 5A (which is a schematic diagram of the critical voltage VT distribution window of memory cells in a traditional non-volatile memory after several erasing cycles), FIG. 5B shows that the lower bound of the critical voltage VT distribution window in this embodiment The erasure of the case is significantly higher after the programmed action.
参照上述说明，可取得包含存储器单元阵列的非易失性存储器的偏压方法。图6为依照本发明一实施例的偏压非易失性存储器的方法的流程图。举例来说，图6所描述的方法可以通过绘示于图3的控制器220中的处理器311来执行。其中，实施图6的方法的程序码可储存于控制器220的储存媒体中。请参照图6，在步骤S610中，在非易失性存储器的抹除周期之后（例如，图3的非易失性存储器系统300），通过使用非易失性存储器的偏压电路中的控制器，初始化一地址计数值及一失败计数值。在步骤S630中，对存储器单元阵列进行一抹除确认动作（例如，抹除后程序化确认动作）。倘若存储器单元阵列通过步骤S630的抹除后程序化确认动作，然后判断该地址计数值是否为最大值（步骤S640）。在步骤S620中，当地址计数值不是为最大值时，增进该地址计数值且重置（Reset）失败计数值。另一方面，当地址计数值为最大值时，终止偏压非易失性存储器的方法。倘若存储器单元阵列的至少一部份未通过步骤S630的抹除确认动作，则继续进行步骤S650。亦即，于每一周期内，存储器单元阵列的部份未通过步骤S630的抹除确认动作时，分别增进失败计数值。如步骤S660至步骤S680所示，取决于失败计数值是否介于不同参数值之间（由X、Y和Z表示），偏压产生器在存储器单元阵列的字元线及/或位元线上施加不同的电压Vg，进而求得感测放大器的负载比率。存储器单元阵列之感测放大器可耦接于第一负载与第二负载之间，而第一负载及第二负载分别与存储器单元阵列的主要单元及参考单元耦接。倘若失败计数值低于第一参数值X（步骤S660），施加于存储器阵列的至少一位元线及/或字元线的电压Vg将设定为第一电压（例如，维持于一预设电压），并且在步骤S665中，调整负载比率为第一负载比率（例如，维持于一预设负载比率）。倘若失败计数值介于第一参数值X与第二参数值Y之间（步骤S670），施加于存储器阵列的至少一位元线及/或字元线的电压Vg将设定为第二电压（例如，增加该预设电压），并且在步骤S675中，调整负载比率为第二负载比率。倘若失败计数值介于第二参数值Y与第三参数值Z之间（步骤S680），施加于存储器阵列的至少一位元线及/或字元线的电压Vg将设定为第三电压（例如，增加该预设电压），并且调整负载比率为第三负载比率。需注意的是，在本实施例中，参数值X、Y、Z可根据一实际运作条件来设定，例如非易失性存储器的所需寿命。随后，根据负载比率及电压Vg，对该存储器单元阵列施加一抹除后程序化脉冲，并且返回至步骤S630。Referring to the above description, a method of biasing a non-volatile memory including a memory cell array can be obtained. FIG. 6 is a flowchart of a method for biasing a nonvolatile memory according to an embodiment of the invention. For example, the method described in FIG. 6 can be executed by the processor 311 in the controller 220 shown in FIG. 3 . Wherein, the program code for implementing the method in FIG. 6 can be stored in the storage medium of the controller 220 . Please refer to FIG. 6, in step S610, after the erasing cycle of the non-volatile memory (for example, the non-volatile memory system 300 in FIG. 3), by using the control in the bias circuit of the non-volatile memory register, and initialize an address count value and a failure count value. In step S630 , perform an erase confirmation operation on the memory cell array (for example, a program confirmation operation after erasing). If the memory cell array passes the post-erasing program confirmation action of step S630, then it is determined whether the address count value is the maximum value (step S640). In step S620 , when the address count value is not the maximum value, the address count value is incremented and the failure count value is reset (Reset). On the other hand, the method of biasing the non-volatile memory is terminated when the address count value is the maximum value. If at least a part of the memory cell array does not pass the erase confirmation action in step S630, proceed to step S650. That is, in each cycle, when part of the memory cell array fails to pass the erase confirmation operation in step S630, the failure count value is incremented respectively. As shown in steps S660 to S680, depending on whether the fail count value is between different parameter values (denoted by X, Y, and Z), the bias voltage generator on the word line and/or bit line of the memory cell array Different voltages Vg are applied on it, and then the load ratio of the sense amplifier is obtained. The sense amplifier of the memory cell array can be coupled between the first load and the second load, and the first load and the second load are respectively coupled to the main cell and the reference cell of the memory cell array. If the failure count value is lower than the first parameter value X (step S660), the voltage Vg applied to at least one bit line and/or word line of the memory array will be set to a first voltage (for example, maintained at a preset voltage), and in step S665, adjust the load ratio to the first load ratio (eg, maintain a preset load ratio). If the fail count value is between the first parameter value X and the second parameter value Y (step S670), the voltage Vg applied to at least one bit line and/or word line of the memory array will be set to the second voltage (for example, increase the preset voltage), and in step S675, adjust the load ratio to the second load ratio. If the failure count value is between the second parameter value Y and the third parameter value Z (step S680), the voltage Vg applied to at least one bit line and/or word line of the memory array will be set to a third voltage (eg, increase the preset voltage), and adjust the load ratio to the third load ratio. It should be noted that in this embodiment, the parameter values X, Y, and Z can be set according to an actual operating condition, such as the required lifetime of the non-volatile memory. Then, apply a post-erase programming pulse to the memory cell array according to the load ratio and the voltage Vg, and return to step S630.
综上所述，根据本发明的实施例，本发明的非易失性存储器系统及偏压非易失性存储器的方法采用不同偏压机制，以紧缩确认电压电平及减少位元线的漏电流，因而可避免程序化失败，且延长非易失性存储器的寿命。In summary, according to the embodiments of the present invention, the non-volatile memory system and the method for biasing the non-volatile memory of the present invention adopt different biasing mechanisms to tighten the confirmation voltage level and reduce the leakage of the bit line. current, thereby avoiding programming failures and extending the lifetime of the nonvolatile memory.
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视后附的申请专利范围所界定者为准。Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.
| Application Number | Priority Date | Filing Date | Title |
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| CN201310364202.XACN104425030B (en) | 2013-08-20 | 2013-08-20 | Non-volatile memory system and method for biasing non-volatile memory |
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| CN201310364202.XACN104425030B (en) | 2013-08-20 | 2013-08-20 | Non-volatile memory system and method for biasing non-volatile memory |
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| CN104425030A CN104425030A (en) | 2015-03-18 |
| CN104425030Btrue CN104425030B (en) | 2018-04-03 |
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| CN201310364202.XAActiveCN104425030B (en) | 2013-08-20 | 2013-08-20 | Non-volatile memory system and method for biasing non-volatile memory |
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| CN106445404B (en)* | 2015-08-13 | 2019-04-23 | 群联电子股份有限公司 | Memory programming method, memory control circuit unit and memory storage device |
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