技术领域technical field
本发明具体涉及数据采集记录系统技术领域，尤其涉及在大规模阵列大容量信号并行获取环境下需要模块扩展、高效获取有用数据和采集同步的数据采集记录系统。The invention specifically relates to the technical field of data acquisition and recording systems, and in particular to a data acquisition and recording system that requires module expansion, efficient acquisition of useful data, and acquisition synchronization in a large-scale array and large-capacity signal parallel acquisition environment.
背景技术Background technique
目前在世界范围内研发的高速采集系统，大部分采用FPGA芯片控制AD芯片实现数据采集，针对特定需求选取芯片、设计结构等。研发的采集系统主要集中在某些相关领域特定信号的采集和集成在单板上的设计。而具有特定功能或者集成于单板的采集系统，如分布式POS子IMU数据采集系统、多通道振动数据采集系统等，根据功能不同，具有特殊的结构，缺乏通用性。At present, most of the high-speed acquisition systems developed around the world use FPGA chips to control AD chips to achieve data acquisition, and select chips and design structures for specific needs. The acquisition system developed mainly focuses on the acquisition of specific signals in certain related fields and the design of integration on a single board. Acquisition systems with specific functions or integrated on a single board, such as distributed POS sub-IMU data acquisition systems, multi-channel vibration data acquisition systems, etc., have special structures according to different functions and lack versatility.
现有的大部分多通道高速同步采集记录系统均采用单板设计模式，即将实际需求的所有采集通道设计在一个电路背板上，使用单个或多个FPGA控制运算单元进行数据控制，然后通过标准接口将数据发送至存储单元存储。这样的设计通用性较差、采集通道很难扩展、采集控制和人机交互设计比较复杂。特别在需要大规模扩展的情况下，如上百路同步采集，扩展开发难度会更大，往往需要重新设计。另一方面，如果对采集到的信号数据不加以选择检验的进行存储，将会得到很多无用的信号，这会大大提高后续对存储数据再分析处理的难度和工作量。Most of the existing multi-channel high-speed synchronous acquisition and recording systems adopt the single-board design mode, that is, all the acquisition channels actually required are designed on a circuit backboard, and single or multiple FPGA control operation units are used for data control, and then through the standard The interface sends the data to the storage unit for storage. Such a design has poor versatility, the acquisition channel is difficult to expand, and the acquisition control and human-computer interaction design is relatively complicated. Especially in the case of large-scale expansion, such as simultaneous acquisition of hundreds of channels, the expansion development will be more difficult and often requires redesign. On the other hand, if the collected signal data is stored without selective inspection, many useless signals will be obtained, which will greatly increase the difficulty and workload of subsequent analysis and processing of the stored data.
发明内容Contents of the invention
为克服现有技术的不足，本发明提供一种通道可扩展的条件式触发高速同步采集记录系统，其主要包括时钟模块、采集模块、存储模块和主板控制器，各模块接口均采用国际通用标准协议，数量可以任意扩展；并在数据采集与存储之间加入了判决信号，使采集到的数据能够条件式触发存储。与现有技术相比，首先是扩展能力的提升，系统可以在主板内各模块扩展，也可以在主板间整体扩展，加之各接口的标准化，从而使得系统多通道扩展更加容易，二次开发也更加方便；其次，在采集与存储之间加入了条件式触发信号，通过对接收信号进行统计判决，不仅可以有条件的舍弃无效信号，而且能够提高对周期信号等特定信号的采样速率。In order to overcome the deficiencies in the prior art, the present invention provides a channel-extensible conditional trigger high-speed synchronous acquisition and recording system, which mainly includes a clock module, an acquisition module, a storage module and a mainboard controller, and the interfaces of each module adopt international general standards Protocol, the number can be expanded arbitrarily; and a decision signal is added between data collection and storage, so that the collected data can be conditionally triggered and stored. Compared with the existing technology, the first is the improvement of the expansion ability. The system can be expanded by each module in the main board, and can also be extended as a whole between the main boards. In addition, the standardization of each interface makes the multi-channel expansion of the system easier, and the secondary development is also easier. It is more convenient; secondly, a conditional trigger signal is added between acquisition and storage. By making a statistical judgment on the received signal, not only can the invalid signal be conditionally discarded, but also the sampling rate of specific signals such as periodic signals can be increased.
本发明对多通道电子信号进行同步采集记录，能够在键盘、外接信号、GPS时刻、条件式触发等多种触发源控制下进行单稳触发、自恢复触发、单稳再触发、自恢复再触发等多种采集方式的采集，采集通道可以大规模扩展。本发明主要包括时钟模块、采集模块、存储模块和主板控制器等，各模块接口均采用通用标准协议，可以进行主板内和主板间的采集通道扩展。本发明用于现代雷达探测、通信、传感器网络、天文学观测中的电子信号高速采集记录，尤其是多通道接收、要求同步采集记录的系统中。在条件式触发的多种采集方式下，可以获得更高效的数据，方便下一步数据再处理，为大规模阵列中并行获取到的大容量信号特性研究及算法验证提供了很大便利。The invention collects and records multi-channel electronic signals synchronously, and can perform monostable triggering, self-recovery triggering, monostable re-triggering, and self-recovery re-triggering under the control of various trigger sources such as keyboard, external signal, GPS time, and conditional triggering Acquisition of multiple acquisition methods, the acquisition channel can be expanded on a large scale. The invention mainly includes a clock module, a collection module, a storage module and a main board controller, etc., and the interface of each module adopts a general standard protocol, which can expand the collection channels in the main board and between the main boards. The invention is used for high-speed collection and recording of electronic signals in modern radar detection, communication, sensor network and astronomical observation, especially in systems requiring multi-channel reception and synchronous collection and recording. Under the multiple acquisition methods of conditional triggering, more efficient data can be obtained, which is convenient for data reprocessing in the next step, and provides great convenience for the research of large-capacity signal characteristics and algorithm verification obtained in parallel in large-scale arrays.
一种通道可扩展的条件式触发高速同步采集记录系统，包括时钟模块、采集模块、存储模块和主板控制器，时钟模块、采集模块、存储模块通过PCIE接口与主板控制器互联，时钟模块能够输出精准同步时钟信号和同步触发信号，驱动采集模块对输入模拟信号进行高速同步采集，采集到的数据在主板控制器下高速写入存储模块永久存储，其中时钟信号频率、触发信号来源可以设置，采集模块输出的判决信号接入时钟模块实现条件式触发；A channel-expandable conditional trigger high-speed synchronous acquisition and recording system, including a clock module, an acquisition module, a storage module, and a mainboard controller. The clock module, acquisition module, and storage module are interconnected with the mainboard controller through a PCIE interface, and the clock module can output Accurately synchronize the clock signal and synchronous trigger signal, drive the acquisition module to perform high-speed synchronous acquisition of the input analog signal, and the collected data is written into the storage module at high speed under the main board controller for permanent storage, in which the frequency of the clock signal and the source of the trigger signal can be set. The judgment signal output by the module is connected to the clock module to realize conditional triggering;
当系统进行主板内采集通道扩展时，采集模块、存储模块根据主板控制器上的PCIE卡槽数量进行扩充，增加采集通道数量；同时在主板控制器上增设触发选择控制器，主板控制器通过串口与触发选择控制器互联，多个采集模块的判决信号经过触发选择控制器选择之后输入时钟模块，实现条件式触发；When the system expands the acquisition channel in the motherboard, the acquisition module and the storage module are expanded according to the number of PCIE card slots on the motherboard controller to increase the number of acquisition channels; at the same time, a trigger selection controller is added on the motherboard controller, and the motherboard controller passes through the serial port. Interconnected with the trigger selection controller, the decision signals of multiple acquisition modules are selected by the trigger selection controller and input to the clock module to realize conditional triggering;
当系统进行主板间采集通道扩展时，系统增设顶层主板控制器和顶层时钟模块，顶层主板控制器通过串口与触发选择控制器互联，顶层主板控制器通过PCIE接口与顶层时钟模块互联；主板控制器连同时钟模块、采集模块、存储模块整体复制扩展为多个；各主板控制器通过IB接口在IB交换机下实现交叉互联；顶层控制器控制触发选择控制器和顶层时钟模块，触发选择控制器能够选择判决信号触发顶层时钟模块输出触发信号，触发各主板控制器时钟模块输出下一级触发信号，触发各个采集通道进行数据存储。When the system expands the collection channels between mainboards, the system adds a top-level mainboard controller and a top-level clock module. The top-level mainboard controller is connected to the trigger selection controller through a serial port, and the top-level mainboard controller is connected to the top-level clock module through a PCIE interface; the mainboard controller Together with the clock module, acquisition module, and storage module, the overall copying and expansion is multiple; each motherboard controller realizes cross-connection under the IB switch through the IB interface; the top-level controller controls the trigger selection controller and the top-level clock module, and the trigger selection controller can select The decision signal triggers the top-level clock module to output a trigger signal, triggers each motherboard controller clock module to output a next-level trigger signal, and triggers each acquisition channel to store data.
采集模块使用FPGA芯片作为控制和运算单元，其外设包括高速AD芯片、精确时钟芯片、大容量SDRAM和Flash芯片，一块FPGA芯片能够外设多路AD、多块SDRAM，同时采集板上集成有外部时钟输入、外部触发输入、判决信号输出以及PCIE接口。The acquisition module uses the FPGA chip as the control and calculation unit. Its peripherals include high-speed AD chips, precise clock chips, large-capacity SDRAM and Flash chips. One FPGA chip can be equipped with multiple ADs and multiple SDRAMs. External clock input, external trigger input, decision signal output and PCIE interface.
FPGA芯片包括数据上行模块和下行控制模块，还包括其外设的AD芯片以及PCIE数据互联模块，数据上行模块负责数据同步采集、数据同步传输、分路打包和数据缓存，数据进入FPGA芯片后，数据上行模块中的数据预处理模块对每一路采集的信号进行预处理，预处理包括增益校准、直流校准、前视缓存、统计判决量计算、数字下变频和数据打包等，在触发信号有效情况下对数据打包，然后通过路由控制进入SDRAM缓存，数据从SDRAM出来之后，与温度报警信号、溢出报警信号等数据进行帧打包，通过PCIE接口上传。下行控制模块包括片上总线和寄存器组，下行控制模块采用标准片上总线协议，合理分配控制寄存器组地址，有效响应主板控制器发送的控制指令。The FPGA chip includes a data uplink module and a downlink control module, as well as its peripheral AD chip and PCIE data interconnection module. The data uplink module is responsible for synchronous data acquisition, data synchronous transmission, split packing and data caching. After the data enters the FPGA chip, The data preprocessing module in the data uplink module preprocesses the signals collected by each channel. The preprocessing includes gain calibration, DC calibration, forward-looking buffer, statistical judgment calculation, digital down-conversion and data packaging, etc. When the trigger signal is valid The data is packaged, and then enters the SDRAM cache through routing control. After the data comes out of the SDRAM, it is packaged with the temperature alarm signal, overflow alarm signal and other data, and uploaded through the PCIE interface. The downlink control module includes an on-chip bus and a register group. The downlink control module adopts a standard on-chip bus protocol, reasonably allocates the address of the control register group, and effectively responds to the control instructions sent by the mainboard controller.
数据预处理模块的数据控制逻辑结构。主要包括AD数据接收、前视FIFO缓存、数据校准、DDC以及数据位调整模块。采集数据进入FPGA后，分两路分别进行处理：一路进行统计判决量计算，进入统计判决量计算逻辑模块，对采集数据进行可设置长度、可调整权值的加权求和，然后与大小可设置的判决阈值比较，输出判决信号得到判决信号输出，输出的判决信号通过触发选择控制器进入时钟模块，进而控制数据的采集；采集到的数据另一路进入前视FIFO，从前视FIFO出来之后经过校准、DDC、数据位调整后进行数据打包，数据打包要在同一触发信号下进行。The data control logic structure of the data preprocessing module. It mainly includes AD data receiving, forward-looking FIFO buffer, data calibration, DDC and data bit adjustment module. After the collected data enters the FPGA, it is processed in two ways: one way is used to calculate the statistical judgment amount, enter the logic module of the statistical judgment amount calculation, and perform weighted summation of the collected data with an adjustable length and adjustable weight, and then calculate the weighted sum with the adjustable size Compared with the judgment threshold value, the output judgment signal is obtained by the judgment signal output, and the output judgment signal enters the clock module through the trigger selection controller, and then controls the data collection; the collected data enters the forward-looking FIFO in another way, and is calibrated after coming out of the forward-looking FIFO , DDC, and data bits are adjusted for data packaging, and the data packaging should be performed under the same trigger signal.
FPGA内的采集触发源可以采用键盘、外接信号、GPS时刻、条件式触发等。The acquisition trigger source in FPGA can be keyboard, external signal, GPS time, conditional trigger, etc.
FPGA内的采集方式可以采用单稳触发、自恢复触发、单稳再触发和自恢复再触发。The acquisition method in the FPGA can adopt monostable trigger, self-recovery trigger, monostable retrigger and self-recovery retrigger.
本发明为解决多通道高速同步采集记录系统中的通道扩展、采集同步等问题，建立了一个采用通用接口、模块化可扩展、条件式触发的高速同步记录系统。该系统由时钟模块输出精准同步时钟信号和触发信号控制采集模块采集，数据在主板控制器下通过PCIE接口写入存储模块。在此架构下，设计了采集模块上的FPGA逻辑结构，实现了键盘、外接信号、GPS时刻、条件式触发等多种触发源触发下的单稳触发、自恢复触发、单稳再触发、自恢复再触发等多种采集方式。In order to solve the problems of channel expansion and acquisition synchronization in a multi-channel high-speed synchronous acquisition and recording system, the present invention establishes a high-speed synchronous recording system that adopts a general interface, is modular and expandable, and is triggered by conditions. In this system, the clock module outputs a precise synchronous clock signal and a trigger signal to control the collection of the acquisition module, and the data is written into the storage module through the PCIE interface under the main board controller. Under this architecture, the FPGA logic structure on the acquisition module is designed to realize monostable triggering, self-recovery triggering, monostable re-triggering, and auto- Recovery and triggering and other acquisition methods.
本发明的时钟模块输出精准同步时钟信号与触发信号控制采集模块，使得各采集通道同步采集、各路采集数据同步存储。时钟模块集成有GPS接收机，可以在设定GPS时刻输出触发信号，也可以通过键盘或外部输入信号控制输出触发信号。采集模块通过ADC芯片、时钟芯片、SDRAM、FPGA芯片等，将模拟信号模数转换、打包、缓存、发送，同时能够条件式输出判决信号，触发时钟模块，实现对周期脉冲等特定信号的高效采集，FPGA内设计的各功能通过总线进行控制。存储模块采用raid阵列，通过控制多块固态硬盘，实现数据的高速存储。主板控制器集成有INFINIBAND(IB)高速数据互联接口，用于系统整体扩展时系统间的数据共享与控制。系统工作时，外部模拟信号耦合输入采集模块，在时钟模块的精准同步时钟信号控制下，采集模块对数据进行采集，并对数据进行一定长度的加权求和运算，将统计量与阈值比较后会产生判决信号触发时钟板输出同步触发信号。当触发条件满足时，时钟模块输出的同步触发信号触发采集模块对数据进行打包、缓存与上传，主板控制器将采集模块上传的数据写入存储模块，存储模块对写入的数据进行永久存储。The clock module of the present invention outputs a precise synchronous clock signal and a trigger signal to control the acquisition module, so that each acquisition channel is acquired synchronously, and each acquisition data is stored synchronously. The clock module is integrated with a GPS receiver, which can output a trigger signal at the set GPS time, or control the output trigger signal through the keyboard or an external input signal. The acquisition module converts, packs, buffers, and sends analog signals through ADC chips, clock chips, SDRAM, and FPGA chips. At the same time, it can conditionally output judgment signals and trigger the clock module to achieve efficient acquisition of specific signals such as periodic pulses. , Each function designed in the FPGA is controlled through the bus. The storage module adopts a raid array, and realizes high-speed data storage by controlling multiple solid-state hard disks. The motherboard controller is integrated with INFINIBAND (IB) high-speed data interconnection interface, which is used for data sharing and control between systems when the overall system is expanded. When the system is working, the external analog signal is coupled to the acquisition module. Under the control of the precise synchronous clock signal of the clock module, the acquisition module collects the data, and performs a weighted summation operation on the data for a certain length, and compares the statistics with the threshold. Generate a decision signal to trigger the clock board to output a synchronous trigger signal. When the trigger condition is satisfied, the synchronous trigger signal output by the clock module triggers the acquisition module to package, buffer and upload the data, the main board controller writes the data uploaded by the acquisition module into the storage module, and the storage module permanently stores the written data.
本发明主要应用于不同领域多通道高速数据采集记录和存储。可以根据实际需要进行级联和扩展，设置不同加权系数、统计长度和判别阈值，选择键盘、外接信号、GPS时刻、条件式触发等多种触发源和单稳触发、自恢复触发、单稳再触发、自恢复再触发等不同的采集方式。选用合适芯片，能够实现多通道、百兆级采样速率的同步采集记录。The invention is mainly applied to multi-channel high-speed data collection, recording and storage in different fields. It can be cascaded and expanded according to actual needs, set different weighting coefficients, statistical lengths and discrimination thresholds, and select various trigger sources such as keyboard, external signal, GPS time, conditional trigger, monostable trigger, self-recovery trigger, monostable re-trigger, etc. Different acquisition methods such as trigger, self-recovery and re-trigger. Selecting a suitable chip can realize synchronous acquisition and recording of multi-channel and 100-megabit sampling rate.
与现有技术相比，具有通道扩展、采集同步、条件式触发、多种方式采集、二次开发方便、人机交互设计简单等优点。本发明的有益效果是：Compared with the existing technology, it has the advantages of channel expansion, acquisition synchronization, conditional trigger, multi-mode acquisition, convenient secondary development, and simple human-computer interaction design. The beneficial effects of the present invention are:
1.扩展能力的提升，系统可以以主板内各模块扩展，也可以以主板间整体扩展；1. With the improvement of expansion ability, the system can be expanded by each module in the main board, or can be extended as a whole between main boards;
2.数据预处理模块的加入，不仅可以有条件的舍弃无效信号，并且可以对特定信号进行更高频率的采集；2. The addition of the data preprocessing module can not only discard invalid signals conditionally, but also collect specific signals at a higher frequency;
3.各处理模块的分离使得各模块的二次开发更加方便。3. The separation of each processing module makes the secondary development of each module more convenient.
附图说明Description of drawings
图1为本发明的系统整体结构图；Fig. 1 is the overall structure diagram of the system of the present invention;
图2为本发明的系统主板内采集通道扩展结构图。Fig. 2 is the expansion structure diagram of the acquisition channel in the main board of the system of the present invention.
图3为本发明系统主板间采集通道扩展结构图Fig. 3 is the expansion structure diagram of acquisition channel between mainboards of the system of the present invention
图4为本发明其采集模块硬件结构图Fig. 4 is its acquisition module hardware structural diagram of the present invention
图5为本发明其FPGA逻辑结构图Fig. 5 is its FPGA logical structure diagram of the present invention
图6为本发明数据预处理模块逻辑结构图Fig. 6 is a logical structure diagram of the data preprocessing module of the present invention
图7为本发明采集方式说明图Figure 7 is an explanatory diagram of the acquisition method of the present invention
具体实施方式Detailed ways
本发明主要包括时钟模块、采集模块、存储模块和主板控制器，整体组成结构如图1所示。The present invention mainly includes a clock module, an acquisition module, a storage module and a mainboard controller, and the overall composition structure is shown in FIG. 1 .
如图1所示，时钟模块、采集模块、存储模块通过PCIE接口与主板控制器互联，时钟模块能够输出精准同步时钟信号和同步触发信号，驱动采集模块对输入模拟信号进行高速同步采集，采集到的数据在主板控制器下高速写入存储模块永久存储，其中时钟信号频率、触发信号来源可以设置，采集模块输出的判决信号接入时钟模块实现条件式触发。As shown in Figure 1, the clock module, acquisition module, and storage module are interconnected with the mainboard controller through the PCIE interface. The clock module can output accurate synchronous clock signals and synchronous trigger signals, and drive the acquisition module to perform high-speed synchronous acquisition of input analog signals. The data is written into the storage module at high speed under the main board controller for permanent storage, in which the frequency of the clock signal and the source of the trigger signal can be set, and the judgment signal output by the acquisition module is connected to the clock module to realize conditional triggering.
当系统进行主板内采集通道扩展时，其结构如图2所示。When the system expands the acquisition channel in the motherboard, its structure is shown in Figure 2.
如图2所示，主板内采集通道扩展时，采集模块、存储模块可根据主板控制器上的PCIE卡槽数量进行扩充，增加采集通道数量。在主板控制器上增设触发选择控制器，多个采集模块的判决信号经过触发选择控制器选择之后输入时钟模块，实现条件式触发。As shown in Figure 2, when the acquisition channels in the mainboard are expanded, the acquisition module and storage module can be expanded according to the number of PCIE card slots on the mainboard controller to increase the number of acquisition channels. A trigger selection controller is added to the main board controller, and the decision signals of multiple acquisition modules are selected by the trigger selection controller and input to the clock module to realize conditional triggering.
当系统进行主板间采集通道扩展时，其结构如图3所示。When the system expands the acquisition channels between mainboards, its structure is shown in Figure 3.
如图3所示，主板间采集通道扩展时，增设顶层主板控制器，其通过串口与触发选择控制器互联、通过PCIE接口与顶层时钟模块互联；主板控制器连同时钟模块、采集模块、存储模块整体复制扩展，各主板控制器通过IB接口在IB交换机下实现交叉互联；顶层控制器控制触发选择控制器和顶层时钟模块，触发选择器能够选择判决信号触发顶层时钟模块输出触发信号，触发各主板控制器时钟模块输出下一级触发信号，触发各个采集通道进行数据存储。As shown in Figure 3, when the acquisition channels between mainboards are expanded, a top-level mainboard controller is added, which is interconnected with the trigger selection controller through the serial port, and connected with the top-level clock module through the PCIE interface; the mainboard controller is connected with the clock module, acquisition module, and storage module. Overall replication and expansion, each mainboard controller realizes cross-connection under the IB switch through the IB interface; the top-level controller controls the trigger selection controller and the top-level clock module, and the trigger selector can select the judgment signal to trigger the top-level clock module to output the trigger signal and trigger each mainboard The clock module of the controller outputs the trigger signal of the next level to trigger each acquisition channel for data storage.
本发明其采集模块描述Its acquisition module description of the present invention
采集模块使用FPGA芯片作为控制和运算单元，外设包括高速AD芯片、精确时钟芯片、大容量SDRAM、Flash芯片等。一块FPGA芯片可以外设多路AD、多块SDRAM，同时采集板上集成有外部时钟输入、外部触发输入、判决信号输出、PCIE等接口。其结构如图4所示。The acquisition module uses the FPGA chip as the control and calculation unit, and the peripherals include high-speed AD chip, precise clock chip, large-capacity SDRAM, Flash chip, etc. One FPGA chip can be equipped with multiple ADs and multiple SDRAMs. At the same time, the acquisition board is integrated with external clock input, external trigger input, judgment signal output, PCIE and other interfaces. Its structure is shown in Figure 4.
如图4所示，外部输入的同步时钟信号通过精确时钟芯片分配给各路AD芯片，控制数据采集，保证同模块各路之间和不同模块之间的采集时钟同步；触发信号输入FPGA芯片，控制数据传输转存，保证同模块各路之间和不同模块之间的数据同步存储；大容量SDRAM组对数据进行缓存，缓存数据通过PCIE接口输出，上位机的控制命令也通过PCIE接口发送至FPGA芯片；Flash存储硬件程序、初始化参数、校准数据等。As shown in Figure 4, the synchronous clock signal input from the outside is distributed to each AD chip through the precise clock chip to control data acquisition and ensure the synchronization of acquisition clocks between each channel of the same module and between different modules; the trigger signal is input to the FPGA chip, Control data transmission and dumping to ensure synchronous storage of data between channels of the same module and between different modules; the large-capacity SDRAM group caches the data, and the cached data is output through the PCIE interface, and the control commands of the host computer are also sent to the FPGA chip; Flash stores hardware programs, initialization parameters, calibration data, etc.
FPGA芯片的FPGA逻辑模块设计FPGA Logic Module Design of FPGA Chip
图5所示为FPGA逻辑结构图。图中FPGA逻辑结构主要包括两大部分内容，数据上行模块和片上总线模块，此外还有外设的AD芯片以及PCIE数据互联模块等。Figure 5 shows the FPGA logic structure diagram. The FPGA logic structure in the figure mainly includes two parts, the data uplink module and the on-chip bus module, in addition to the peripheral AD chip and the PCIE data interconnection module.
图5所示，数据上行模块解决了数据同步采集、数据同步传输、分路打包、数据缓存等问题，图中“数据上行模块”虚线框中为数据上行逻辑结构。数据进入FPGA芯片后，数据预处理模块对每一路采集的信号进行预处理，包括增益校准、直流校准、前视缓存、统计判决量计算、数字下变频(DDC)、数据打包等，在触发信号有效情况下对数据打包，然后通过路由控制进入SDRAM缓存，数据从SDRAM出来之后，与温度报警信号、溢出报警信号等数据进行帧打包，通过PCIE接口上传。图中“下行控制模块”虚线框中为下行控制逻辑结构，采用标准片上总线协议，合理分配控制寄存器组地址，有效响应主板控制器发送的控制指令。As shown in Figure 5, the data uplink module solves the problems of synchronous data acquisition, data synchronous transmission, splitting and packaging, and data caching. After the data enters the FPGA chip, the data preprocessing module preprocesses the signals collected by each channel, including gain calibration, DC calibration, look-ahead buffer, statistical judgment calculation, digital down-conversion (DDC), data packaging, etc., in the trigger signal When it is effective, the data is packaged, and then enters the SDRAM cache through routing control. After the data comes out of the SDRAM, it is packaged with the temperature alarm signal, overflow alarm signal and other data, and uploaded through the PCIE interface. The dotted box of the "downlink control module" in the figure is the downlink control logic structure, which adopts the standard on-chip bus protocol, reasonably allocates the address of the control register group, and effectively responds to the control instructions sent by the main board controller.
数据预处理逻辑模块Data Preprocessing Logic Module
图6所示为数据预处理模块的数据控制逻辑结构。主要包括AD数据接收、前视FIFO缓存、数据校准、DDC、数据位调整等模块。Figure 6 shows the data control logic structure of the data preprocessing module. It mainly includes AD data receiving, forward-looking FIFO buffer, data calibration, DDC, data bit adjustment and other modules.
如图6所示，采集数据进入FPGA芯片后，分两路分别进行处理：一路进行统计判决量计算，得到判决信号输出；另一路进入前视FIFO，从前视FIFO出来之后经过校准、DDC、数据位调整后进行打包。数据打包要在同一触发信号下进行。As shown in Figure 6, after the collected data enters the FPGA chip, it is processed in two ways: one way is used to calculate the statistical judgment amount, and the judgment signal output is obtained; the other way enters the forward-looking FIFO, and after coming out of the forward-looking FIFO, it undergoes calibration, DDC, data Packing after bit adjustment. Data packing should be carried out under the same trigger signal.
在对脉冲等信号进行采集时，如果连续采集存储会存储很多无效的数据，将极大增加后续数据处理分析的难度，针对这一问题，设计了条件式触发功能。一方面，图6中所示，采集到的数据分两路，一路进入“统计判决量计算”逻辑模块，对采集数据进行可设置长度、可调整权值的加权求和，然后与大小可设置的判决阈值比较，输出判决信号，如图1、图2、图3所示，输出的判决信号通过触发选择控制器进入时钟模块，进而控制数据的采集；另一方面，由于条件式触发回路的延时性，如果从统计判决触发之后进行存储，将会丢失之前的有用信号，所以，采集到的数据另一路进入前视FIFO缓存模块，前视FIFO前视大小、数据校准等都可进行设置。When collecting signals such as pulses, if continuous collection and storage will store a lot of invalid data, it will greatly increase the difficulty of subsequent data processing and analysis. To solve this problem, a conditional trigger function is designed. On the one hand, as shown in Figure 6, the collected data is divided into two channels, one of which enters the "statistical judgment calculation" logic module, and the collected data is weighted and summed with an adjustable length and adjustable weight, and then combined with an adjustable value. Compared with the decision threshold value of , the decision signal is output, as shown in Figure 1, Figure 2, and Figure 3, the output decision signal enters the clock module through the trigger selection controller, and then controls the data collection; on the other hand, due to the conditional trigger loop Delay, if it is stored after the statistical judgment is triggered, the previous useful signal will be lost. Therefore, the collected data enters the forward-looking FIFO buffer module in another way, and the forward-looking FIFO forward-looking size, data calibration, etc. can be set .
数据采集存储触发类型描述Data Acquisition Storage Trigger Type Description
系统可以键盘、外接信号、GPS时刻、条件式触发等多种触发源触发，可以单稳触发、自恢复触发、单稳再触发、自恢复再触发等多种采集方式采集记录。四种采集方式如图7所示。The system can be triggered by various trigger sources such as keyboard, external signal, GPS time, and conditional trigger, and can collect records in various acquisition methods such as monostable trigger, self-recovery trigger, monostable re-trigger, and self-recovery re-trigger. The four collection methods are shown in Figure 7.
图7所示为四种采集方式说明图：Figure 7 shows the explanatory diagram of the four collection methods:
单稳触发时，在触发信号上升沿开始采集，采集设定的“单次采样点数”之后采集自动停止；When the monostable trigger is used, the collection starts at the rising edge of the trigger signal, and the collection stops automatically after the set "single sampling points" are collected;
单稳再触发时，在触发信号上升沿开始采集，采集设定点数之后，等待设定的“再触发最小间隔”，然后进入等待触发状态，在下个触发信号上升沿来临时重复执行上述步骤，直到强制停止；When monostable retriggering, start collecting at the rising edge of the trigger signal, after collecting the set points, wait for the set "retrigger minimum interval", then enter the waiting trigger state, and repeat the above steps when the next rising edge of the trigger signal comes, until forced to stop;
自恢复触发时，在触发信号上升沿开始周期性采集，采集一段，停止一段，“单次采样点数”、“自恢复周期次数”和“自恢复周期”可以设置，采集设定的“自恢复周期次数”之后采集自动停止。When self-recovery is triggered, periodic collection starts at the rising edge of the trigger signal, collects for one period, and stops for one period. The acquisition stops automatically after "Cycles".
自恢复再触发时，在触发信号上升沿开始周期性采集，采集一段，停止一段，“单次采样点数”、“自恢复周期次数”和“自恢复周期”可以设置，采集设定的“自恢复周期次数”之后，等待下次触发信号上升沿来临时重复执行上述步骤，直到强制停止。When retriggering from self-recovery, periodic collection starts at the rising edge of the trigger signal, collects for one period, and stops for one period. After the number of recovery cycles", wait for the rising edge of the next trigger signal to repeat the above steps until it is forced to stop.
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作各种更动与润饰，因此本发明的保护范围当视权利要求书界定的范围为准。In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410673368.4ACN104317752B (en) | 2014-11-21 | 2014-11-21 | The extendible conditional of a kind of passage triggers high speed synchronous sample register system |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410673368.4ACN104317752B (en) | 2014-11-21 | 2014-11-21 | The extendible conditional of a kind of passage triggers high speed synchronous sample register system |
| Publication Number | Publication Date |
|---|---|
| CN104317752Atrue CN104317752A (en) | 2015-01-28 |
| CN104317752B CN104317752B (en) | 2015-08-12 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410673368.4AActiveCN104317752B (en) | 2014-11-21 | 2014-11-21 | The extendible conditional of a kind of passage triggers high speed synchronous sample register system |
| Country | Link |
|---|---|
| CN (1) | CN104317752B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027192A (en)* | 2016-06-27 | 2016-10-12 | 哈尔滨明快机电科技有限公司 | Device for synchronously collecting parallel data |
| CN106290943A (en)* | 2015-10-14 | 2017-01-04 | 北京信息科技大学 | A kind of flow cytometer bus control device and method |
| CN106644492A (en)* | 2016-09-30 | 2017-05-10 | 武汉理工大学 | Marine middle-and-low-speed diesel engine cylinder pressure online monitoring system based on FPGA |
| CN107508609A (en)* | 2017-07-31 | 2017-12-22 | 成都普诺科技有限公司 | C-band signal receiver with real-time acquisition function |
| CN107702934A (en)* | 2017-09-27 | 2018-02-16 | 广州市光机电技术研究院 | Point machine working status parameter harvester and method based on FPGA |
| CN107802242A (en)* | 2017-11-30 | 2018-03-16 | 清华大学深圳研究生院 | Signal acquiring and processing apparatus and method for photoacoustic imaging |
| CN107991654A (en)* | 2016-10-27 | 2018-05-04 | 北京遥感设备研究所 | A kind of method for weather radar servo-information and intermediate-freuqncy signal synchronous acquisition |
| CN108225546A (en)* | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of airborne multi-channel Vibration Signal synchronous and method |
| CN109406315A (en)* | 2018-11-29 | 2019-03-01 | 清华大学 | Firer's shock response many reference amounts cooperative device |
| CN109413353A (en)* | 2017-08-03 | 2019-03-01 | 联发科技股份有限公司 | Reconfigurable pin-to-pin interface and method of setting the same |
| CN111060155A (en)* | 2019-12-27 | 2020-04-24 | 山东厚德测控技术股份有限公司 | Collision wall information acquisition system |
| CN111679993A (en)* | 2020-05-29 | 2020-09-18 | 湖南苍树航天科技有限公司 | Multichannel parallel synchronous bus controller |
| CN112462240A (en)* | 2020-12-04 | 2021-03-09 | 国微集团(深圳)有限公司 | Method and device for supporting synchronous trigger detection of cross-chip signals |
| CN113093628A (en)* | 2021-04-14 | 2021-07-09 | 中国矿业大学(北京) | Synchronous acquisition control method for subway tunnel potential safety hazard detection vehicle |
| CN113360444A (en)* | 2021-06-24 | 2021-09-07 | 成都能通科技有限公司 | Data synchronous generation method based on daisy chain cascade data generation system |
| CN113655740A (en)* | 2021-07-26 | 2021-11-16 | 五邑大学 | Method, device and system for data acquisition of transmission system and storage medium |
| CN114168509A (en)* | 2021-10-22 | 2022-03-11 | 中科苏州微电子产业技术研究院 | Expansion control method and system of data acquisition chip |
| CN116680221A (en)* | 2022-11-04 | 2023-09-01 | 成都立思方信息技术有限公司 | Distributed high-speed signal receiving and transmitting processing system |
| CN120034274A (en)* | 2025-03-07 | 2025-05-23 | 成都立思方信息技术有限公司 | A multi-channel signal real-time monitoring and access system with flexible scalability |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005006156A2 (en)* | 2003-07-09 | 2005-01-20 | Innova Card | Integrated circuit comprising an ordinary module and a secured module that are connected via a protected line |
| CN102521182A (en)* | 2011-11-23 | 2012-06-27 | 华南师范大学 | Extensible multichannel parallel real-time data acquisition device and method |
| CN102551810A (en)* | 2012-03-09 | 2012-07-11 | 华南师范大学 | Multichannel synchronous real-time digitalized photoacoustic imaging device and method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005006156A2 (en)* | 2003-07-09 | 2005-01-20 | Innova Card | Integrated circuit comprising an ordinary module and a secured module that are connected via a protected line |
| CN102521182A (en)* | 2011-11-23 | 2012-06-27 | 华南师范大学 | Extensible multichannel parallel real-time data acquisition device and method |
| CN102551810A (en)* | 2012-03-09 | 2012-07-11 | 华南师范大学 | Multichannel synchronous real-time digitalized photoacoustic imaging device and method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106290943A (en)* | 2015-10-14 | 2017-01-04 | 北京信息科技大学 | A kind of flow cytometer bus control device and method |
| CN106290943B (en)* | 2015-10-14 | 2018-07-27 | 北京信息科技大学 | A kind of flow cytometer bus control device and method |
| CN106027192B (en)* | 2016-06-27 | 2018-09-07 | 哈尔滨明快机电科技有限公司 | A kind of parallel data synchronous acquisition device |
| CN106027192A (en)* | 2016-06-27 | 2016-10-12 | 哈尔滨明快机电科技有限公司 | Device for synchronously collecting parallel data |
| CN106644492A (en)* | 2016-09-30 | 2017-05-10 | 武汉理工大学 | Marine middle-and-low-speed diesel engine cylinder pressure online monitoring system based on FPGA |
| CN107991654B (en)* | 2016-10-27 | 2021-05-07 | 北京遥感设备研究所 | A method for synchronous acquisition of weather radar servo information and intermediate frequency signal |
| CN107991654A (en)* | 2016-10-27 | 2018-05-04 | 北京遥感设备研究所 | A kind of method for weather radar servo-information and intermediate-freuqncy signal synchronous acquisition |
| CN108225546A (en)* | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of airborne multi-channel Vibration Signal synchronous and method |
| CN107508609A (en)* | 2017-07-31 | 2017-12-22 | 成都普诺科技有限公司 | C-band signal receiver with real-time acquisition function |
| CN109413353B (en)* | 2017-08-03 | 2021-02-09 | 联发科技股份有限公司 | Reconfigurable pin-to-pin interface and method of setting the same |
| CN109413353A (en)* | 2017-08-03 | 2019-03-01 | 联发科技股份有限公司 | Reconfigurable pin-to-pin interface and method of setting the same |
| CN107702934A (en)* | 2017-09-27 | 2018-02-16 | 广州市光机电技术研究院 | Point machine working status parameter harvester and method based on FPGA |
| CN107802242A (en)* | 2017-11-30 | 2018-03-16 | 清华大学深圳研究生院 | Signal acquiring and processing apparatus and method for photoacoustic imaging |
| CN109406315B (en)* | 2018-11-29 | 2024-10-15 | 清华大学 | Multi-parameter collaborative measurement device for pyrotechnic shock response |
| CN109406315A (en)* | 2018-11-29 | 2019-03-01 | 清华大学 | Firer's shock response many reference amounts cooperative device |
| CN111060155A (en)* | 2019-12-27 | 2020-04-24 | 山东厚德测控技术股份有限公司 | Collision wall information acquisition system |
| CN111679993A (en)* | 2020-05-29 | 2020-09-18 | 湖南苍树航天科技有限公司 | Multichannel parallel synchronous bus controller |
| CN111679993B (en)* | 2020-05-29 | 2021-08-17 | 湖南苍树航天科技有限公司 | Multichannel parallel synchronous bus controller |
| CN112462240A (en)* | 2020-12-04 | 2021-03-09 | 国微集团(深圳)有限公司 | Method and device for supporting synchronous trigger detection of cross-chip signals |
| CN113093628A (en)* | 2021-04-14 | 2021-07-09 | 中国矿业大学(北京) | Synchronous acquisition control method for subway tunnel potential safety hazard detection vehicle |
| CN113093628B (en)* | 2021-04-14 | 2023-05-23 | 中国矿业大学(北京) | Synchronous acquisition control method for subway tunnel potential safety hazard detection vehicle |
| CN113360444A (en)* | 2021-06-24 | 2021-09-07 | 成都能通科技有限公司 | Data synchronous generation method based on daisy chain cascade data generation system |
| CN113360444B (en)* | 2021-06-24 | 2023-04-11 | 成都能通科技股份有限公司 | Data synchronous generation method based on daisy chain cascade data generation system |
| CN113655740A (en)* | 2021-07-26 | 2021-11-16 | 五邑大学 | Method, device and system for data acquisition of transmission system and storage medium |
| CN113655740B (en)* | 2021-07-26 | 2022-12-13 | 五邑大学 | Method, device and system for data acquisition of transmission system and storage medium |
| CN114168509A (en)* | 2021-10-22 | 2022-03-11 | 中科苏州微电子产业技术研究院 | Expansion control method and system of data acquisition chip |
| CN116680221A (en)* | 2022-11-04 | 2023-09-01 | 成都立思方信息技术有限公司 | Distributed high-speed signal receiving and transmitting processing system |
| CN116680220A (en)* | 2022-11-04 | 2023-09-01 | 成都立思方信息技术有限公司 | Signal transceiver and signal receiving and transmitting system |
| CN116680220B (en)* | 2022-11-04 | 2023-11-28 | 成都立思方信息技术有限公司 | Signal transceiver and signal receiving and transmitting system |
| CN116680221B (en)* | 2022-11-04 | 2024-03-26 | 成都立思方信息技术有限公司 | Distributed high-speed signal receiving and transmitting processing system |
| CN120034274A (en)* | 2025-03-07 | 2025-05-23 | 成都立思方信息技术有限公司 | A multi-channel signal real-time monitoring and access system with flexible scalability |
| Publication number | Publication date |
|---|---|
| CN104317752B (en) | 2015-08-12 |
| Publication | Publication Date | Title |
|---|---|---|
| CN104317752B (en) | The extendible conditional of a kind of passage triggers high speed synchronous sample register system | |
| CN113535620B (en) | Multichannel synchronous high-speed data acquisition device | |
| CN105045763B (en) | A kind of PD Radar Signal Processing Systems and its Parallel Implementation method based on FPGA+ multi-core DSPs | |
| US10318468B2 (en) | FPGA-based interface signal remapping method | |
| CN102521182A (en) | Extensible multichannel parallel real-time data acquisition device and method | |
| US9250859B2 (en) | Deterministic FIFO buffer | |
| CN105141294B (en) | Double preset examination door-control type constant fraction discriminator discriminators and digital constant fraction discriminator discriminating method | |
| CN102495256A (en) | Method for capturing high-speed signals and imaging real-time waveform of oscilloscope | |
| CN106209341A (en) | Multichannel LVDS sequential alignment detector image acquisition method | |
| TWI604303B (en) | Inout/output expander chip and verification method therefor | |
| CN106603442B (en) | A kind of cross clock domain high-speed data communication interface circuit of network-on-chip | |
| CN103888227B (en) | Data frame receiving and analyzing device and method based on VL | |
| Nakao et al. | Data acquisition system for Belle II | |
| CN109683018B (en) | A parallel processing method for real-time multi-frame frequency domain data | |
| Branchini et al. | Front-end DAQ strategy and implementation for the KLOE-2 experiment | |
| CN204143431U (en) | The low delayed data of a kind of high speed gathers totalizer | |
| CN109443557B (en) | A single photon pulse arrival time detection device | |
| CN204631259U (en) | A kind of shake of the ore deposit based on precise clock synchronization agreement monitoring device | |
| CN118018665A (en) | A multi-channel image acquisition and processing system based on ZYNQ | |
| Xu et al. | An ATCA-based high performance compute node for trigger and data acquisition in large experiments | |
| CN117116311A (en) | Multichannel trigger readout circuit with time interval measurement function | |
| CN113206662B (en) | Multichannel coincidence counting method and device, coincidence counting equipment and storage medium | |
| Kavatsyuk et al. | Trigger-less readout electronics for the PANDA electromagnetic calorimeter | |
| Kumar et al. | Verification of asynchronous FIFO using system Verilog | |
| Tian et al. | Design and Implementation of USB3. 0 Data Transmission System based on FPGA |
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |