技术领域technical field
本发明涉及电子行业电子元器件技术领域，尤其涉及一种具有预失真功能的线性调频信号发生器。The invention relates to the technical field of electronic components in the electronics industry, in particular to a chirp signal generator with a pre-distortion function.
背景技术Background technique
线性调频信号指信号的频率与时间成线性关系，它采用相位调制和脉冲压缩技术达到降低发射机峰值功率，提高雷达作用距离。这个优点使其在合成孔径雷达领域得到广泛的应用，如何产生线性调频信号成为理论和工程研究的热点。The linear frequency modulation signal refers to the linear relationship between the frequency and time of the signal. It uses phase modulation and pulse compression technology to reduce the peak power of the transmitter and increase the radar range. This advantage makes it widely used in the field of synthetic aperture radar, and how to generate chirp signals has become a hot spot in theoretical and engineering research.
传统的线性调频信号产生方法有两种：数字波形直接合成器和数字波形存储直读法，它们的优缺点如下：There are two traditional methods for generating chirp signals: digital waveform direct synthesizer and digital waveform storage direct reading method. Their advantages and disadvantages are as follows:
1)数字波形直接合成器(Direct Digital Synthesis-DDS)能够以最小的硬件代价产生高质量的任意长度单脉冲线性调频脉冲，但是不能够对波形进行预失真；1) Digital Waveform Direct Synthesizer (Direct Digital Synthesis-DDS) can generate high-quality single-pulse chirp pulses of any length with minimal hardware cost, but cannot pre-distort the waveform;
2)基于数模转换器(Digital to Analog Convertor-DAC)的数字波形存储直读法。数字波形存储直读法预先将数字波形存储在ROM(Read OnlyMemory-ROM)中，然后在PRF(Pulse Repeat Frequency-PRF)的控制下，从ROM中读出波形，经过一系列的合成处理，得到高速的数据流，送给DAC进行转换，得到模拟基带信号。该方法的优点是可以产生任意波形，并且能够对波形进行预失真。但是缺点为：设计复杂，研制周期长。特别是当FPGA内部的存储资源无法满足产生大带宽和大脉宽信号所需要的大容量空间时，就需要扩展FIFO或者DRAM。FIFO使用简单，但是其容量小，成本高，需要扩展多片才能够满足要求；DRAM速度快、容量大，缺点是只有一个端口，控制时序很复杂。另外通过扩展存储器的方法带来了电路板的尺寸、功耗和成本的增加。2) Digital waveform storage direct reading method based on Digital to Analog Converter (DAC). The digital waveform storage direct reading method stores the digital waveform in ROM (Read Only Memory-ROM) in advance, and then reads the waveform from the ROM under the control of PRF (Pulse Repeat Frequency-PRF). After a series of synthesis processing, the obtained The high-speed data stream is sent to the DAC for conversion to obtain an analog baseband signal. The advantage of this method is that arbitrary waveforms can be generated and the waveforms can be pre-distorted. But the disadvantages are: complex design and long development cycle. Especially when the storage resources inside the FPGA cannot meet the large-capacity space required to generate large-bandwidth and large-pulse-width signals, it is necessary to expand FIFO or DRAM. FIFO is simple to use, but its capacity is small and the cost is high, and it needs to expand multiple chips to meet the requirements; DRAM has fast speed and large capacity, but the disadvantage is that there is only one port, and the control timing is very complicated. In addition, the method of expanding the memory brings about an increase in the size, power consumption and cost of the circuit board.
因此，在传统的波形存储直读法中，受限于FPGA内部有限的存储器资源，需要扩展存储器满足产生长脉冲信号的需要。扩展大容量高速DRAM带来的问题有：(1)信号质量差；(2)为了满足高速DAC的转换速度要求，需要DRAM的数量多；(3)与FPGA之间的连线多，占用大量IO资源；(4)DRAM的控制复杂，特别是需要实现双端口；(5)结构复杂、面积和功耗都比较大，由此带来的成本也很高。Therefore, in the traditional waveform storage direct reading method, limited by the limited memory resources inside the FPGA, it is necessary to expand the memory to meet the needs of generating long pulse signals. The problems caused by the expansion of large-capacity and high-speed DRAMs are: (1) poor signal quality; (2) in order to meet the conversion speed requirements of high-speed DACs, a large number of DRAMs is required; (3) there are many connections with the FPGA, which takes up a lot of IO resources; (4) the control of DRAM is complex, especially the need to implement dual ports; (5) the structure is complex, the area and power consumption are relatively large, and the cost caused by this is also high.
发明内容Contents of the invention
(一)要解决的技术问题(1) Technical problems to be solved
鉴于上述技术问题，本发明提供了一种具有预失真功能的线性调频信号发生器，以满足合成孔径雷达对基带信号源提出的小型化、能够进行预失真、能够产生大脉冲宽度线性调频信号的要求。In view of the above-mentioned technical problems, the present invention provides a chirp signal generator with a pre-distortion function to meet the needs of synthetic aperture radar for miniaturization of the baseband signal source, the ability to perform pre-distortion, and the ability to generate large-pulse-width chirp signals. Require.
(二)技术方案(2) Technical solution
本发明具有预失真功能的线性调频信号发生器包括：FPGA单元，用于根据目标线性调频信号的时宽和带宽，在外触发信号的控制下产生相位预失真的数字线性调频信号，并将其经过幅度预失真处理，幅相预失真后产生两路正交的数字线性调频信号；数模转换单元，与FPGA单元的输出端相连接，用于将幅相预失真后的两路正交的数字线性调频信号转换成为两路正交的离散模拟线性调频信号；以及滤波单元，与数模转换单元相连接，用于滤除上述两路正交的离散模拟线性调频信号中预设频率范围之外的频率成分，得到连续的两路正交的模拟线性调频信号。The chirp signal generator with predistortion function of the present invention comprises: FPGA unit, is used for according to the time width and the bandwidth of target chirp signal, the digital chirp signal of phase predistortion is produced under the control of external trigger signal, and it passes through Amplitude pre-distortion processing, after amplitude-phase pre-distortion, two-way orthogonal digital chirp signals are generated; a digital-to-analog conversion unit is connected to the output terminal of the FPGA unit, and is used to convert two-way orthogonal digital chirp signals after amplitude-phase pre-distortion The chirp signal is converted into two orthogonal discrete analog chirp signals; and the filter unit is connected with the digital-to-analog conversion unit for filtering out the preset frequency range of the above two orthogonal discrete analog chirp signals frequency components, to obtain two continuous quadrature analog chirp signals.
(三)有益效果(3) Beneficial effects
从上述技术方案可以看出，本发明具有预失真功能的线性调频信号发生器具有以下有益效果：As can be seen from the above technical solution, the chirp signal generator with predistortion function of the present invention has the following beneficial effects:
(1)能够对理想线性调频信号进行预失真；(1) It can predistort the ideal chirp signal;
通过对瞬时相位加预失真的相位数据，对瞬时幅度乘以预失真的幅度数据的方式实现对理想线性调频信号的幅相预失真，通过幅相预失真处理，能够补偿模拟电路对线性调频信号产生的非线性影响，保证最终可以得到高质量的线性调频信号。The amplitude-phase pre-distortion of the ideal chirp signal is realized by adding the pre-distorted phase data to the instantaneous phase and multiplying the pre-distorted amplitude data by the instantaneous amplitude. Through the amplitude-phase pre-distortion processing, it can compensate the analog circuit for the chirp signal. The non-linear effect generated ensures that a high-quality chirp signal can be obtained in the end.
(2)相比传统波形存储直读法，能够产生更长脉宽的信号。(2) Compared with the traditional waveform storage direct reading method, it can generate a signal with a longer pulse width.
通过采用存储一个象限的三角函数查找表和少量幅相失真数据的方案降低了对FPGA存储资源的要求。在使用相同FPGA的情况下，与传统波形存储直读法相比，本发明提供的具有预失真功能的线性调频信号发生器能够产生更长脉宽的线性调频信号。The requirements for FPGA storage resources are reduced by adopting a scheme of storing a quadrant trigonometric function lookup table and a small amount of amplitude and phase distortion data. In the case of using the same FPGA, compared with the traditional waveform storage direct reading method, the chirp signal generator with predistortion function provided by the present invention can generate a chirp signal with a longer pulse width.
(3)提高集成度，降低设计难度，结构简单，面积和功耗均较小，实现基带信号源的轻小型化和低成本。(3) The integration level is improved, the design difficulty is reduced, the structure is simple, the area and power consumption are small, and the baseband signal source is miniaturized and low-cost.
附图说明Description of drawings
图1为根据本发明实施例具有预失真功能的线性调频信号发生器的组成框图；1 is a block diagram of a chirp signal generator with a predistortion function according to an embodiment of the present invention;
图2为图1所示线性调频信号发生器中FPGA单元的结构示意图；Fig. 2 is the structural representation of the FPGA unit in the chirp signal generator shown in Fig. 1;
图3为图2所示FPGA单元中理想线性调频信号瞬时相位产生的结构示意图；Fig. 3 is the structure schematic diagram that ideal chirp signal instantaneous phase produces in the FPGA unit shown in Fig. 2;
图4示出了抽取前后相位预失真的时域波形；Figure 4 shows the time-domain waveforms of phase predistortion before and after extraction;
图5示出了抽取前后幅度预失真的时域波形；Figure 5 shows the time-domain waveforms of amplitude predistortion before and after extraction;
图6和图7分别为采用现有技术的线性调频信号发生器产生线性调频信号的频谱和时域波形；Fig. 6 and Fig. 7 are respectively the frequency spectrum and the time domain waveform that adopt the chirp signal generator of prior art to generate chirp signal;
图8和图9分别为采用本实施例线性调频信号发生器产生线性调频信号的频谱和时域波形。Fig. 8 and Fig. 9 respectively show the frequency spectrum and time domain waveform of the chirp signal generated by the chirp signal generator of this embodiment.
具体实施方式detailed description
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。需要说明的是，在附图或说明书描述中，相似或相同的部分都使用相同的图号。附图中未绘示或描述的实现方式，为所属技术领域中普通技术人员所知的形式。另外，虽然本文可提供包含特定值的参数的示范，但应了解，参数无需确切等于相应的值，而是可在可接受的误差容限或设计约束内近似于相应的值。In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be noted that, in the drawings or descriptions of the specification, similar or identical parts all use the same figure numbers. Implementations not shown or described in the accompanying drawings are forms known to those of ordinary skill in the art. Additionally, while illustrations of parameters including particular values may be provided herein, it should be understood that the parameters need not be exactly equal to the corresponding values, but rather may approximate the corresponding values within acceptable error margins or design constraints.
在本发明的一个示例性实施例中，提供了一种具有预失真功能的线性调频信号发生器。图1为根据本发明实施例具有预失真功能的线性调频信号发生器的组成框图。请参照图1，本实施例具有预失真功能的线性调频信号发生器包括：In an exemplary embodiment of the present invention, a chirp signal generator with predistortion function is provided. FIG. 1 is a block diagram of a chirp signal generator with a predistortion function according to an embodiment of the present invention. Please refer to Fig. 1, the chirp signal generator with predistortion function in this embodiment includes:
FPGA单元，用于根据目标线性调频信号的时宽和带宽，在外触发信号的控制下产生相位预失真的数字线性调频信号，并将其经过幅度预失真处理，产生两路正交的幅相预失真数字线性调频信号；The FPGA unit is used to generate a phase-predistorted digital chirp signal under the control of an external trigger signal according to the time width and bandwidth of the target chirp signal, and process it through amplitude pre-distortion to generate two quadrature amplitude-phase pre-distortion signals. Distorted digital chirp signal;
数模转换单元DAC，与FPGA单元的输出端相连接，用于将幅相预失真后的两路正交的数字线性调频信号转换成为两路正交的离散模拟线性调频信号；The digital-to-analog conversion unit DAC is connected to the output terminal of the FPGA unit, and is used to convert the two-way orthogonal digital chirp signals after amplitude-phase predistortion into two-way orthogonal discrete analog chirp signals;
低通滤波单元，与数模转换单元相连接，用于滤除上述两路正交的离散模拟线性调频信号中预设频率范围之外的频率成分，得到连续的两路正交的模拟线性调频信号。The low-pass filter unit is connected with the digital-to-analog conversion unit, and is used to filter out the frequency components outside the preset frequency range in the above-mentioned two-way orthogonal discrete analog chirp signals to obtain continuous two-way orthogonal analog chirp signals Signal.
以下分别对本实施例具有预失真功能的线性调频信号发生器的各个组成部分进行详细说明。Each component of the chirp signal generator with predistortion function in this embodiment will be described in detail below.
FPGA单元用于产生数字线性调频信号。图2为图1所示线性调频信号发生器中FPGA单元的结构示意图。请参照图2，该FPGA单元包括：The FPGA unit is used to generate the digital chirp signal. FIG. 2 is a schematic structural diagram of the FPGA unit in the chirp signal generator shown in FIG. 1 . Please refer to Figure 2, the FPGA unit includes:
瞬时相位产生模块，用于产生理想线性调频信号的瞬时相位；The instantaneous phase generation module is used to generate the instantaneous phase of the ideal chirp signal;
相位预失真处理模块，用于将瞬时相位产生模块产生的瞬时相位与自身预存的相位预失真数据相乘，得到实际瞬时相位；The phase predistortion processing module is used to multiply the instantaneous phase generated by the instantaneous phase generation module with the phase predistortion data stored in itself to obtain the actual instantaneous phase;
线性调频信号输出模块，用于将相位预失真处理模块输出的实际瞬时相位映射至笛卡尔坐标系下，在自身预存的三角函数表中查找该实际瞬时相位对应的正弦函数值和余弦函数值，得到经过相位预失真后的两路正交的线性调频信号幅度值，实现实际瞬时相位到幅度的转换；The chirp signal output module is used to map the actual instantaneous phase output by the phase predistortion processing module to the Cartesian coordinate system, and search the sine function value and cosine function value corresponding to the actual instantaneous phase in the trigonometric function table stored in itself, Obtain the amplitude values of two orthogonal chirp signals after phase predistortion, and realize the actual instantaneous phase-to-amplitude conversion;
幅度预失真处理模块，用于将线性调频信号输出模块输出的两路正交的线性调频信号幅度值分别与自身预存的幅度预失真数据相乘，得到幅相预失真后的两路正交的线性调频信号幅度值。The amplitude predistortion processing module is used to multiply the amplitude values of the two orthogonal chirp signals output by the chirp signal output module with the amplitude predistortion data stored in itself respectively, to obtain the two orthogonal chirp data after the amplitude phase predistortion Chirp signal amplitude value.
FPGA内部全部功能的实现都采用同步时序逻辑实现，所需时钟的频率为数模转换器转换时钟的频率，或者为该时钟的整数倍分频。The realization of all the functions inside the FPGA is realized by synchronous sequential logic, and the frequency of the required clock is the frequency of the conversion clock of the digital-to-analog converter, or the frequency division of the integer multiple of the clock.
图3为图2所示FPGA单元中瞬时相位产生模块的结构示意图。如图3所示，该瞬时相位产生模块包括：FIG. 3 is a schematic structural diagram of the instantaneous phase generation module in the FPGA unit shown in FIG. 2 . As shown in Figure 3, the instantaneous phase generation module includes:
第一级电路，包括：第一锁存器reg1，其输入端输入控制字2K(即调频斜率的2倍)；第一加法器，其第一输入端连接至第一锁存器reg1的输出端；第二锁存器reg2，其输入端连接至第一加法器的输出端，其输出端连接至第一加法器的第二输入端，并作为该第一级电路的输出端；The first-stage circuit includes: a first latch reg1, whose input terminal inputs a control word 2K (that is, twice the frequency modulation slope); a first adder, whose first input terminal is connected to the output of the first latch reg1 terminal; the second latch reg2, its input terminal is connected to the output terminal of the first adder, its output terminal is connected to the second input terminal of the first adder, and as the output terminal of the first stage circuit;
第二级电路，包括：第三锁存器reg3，其输入端输入控制字3K(即调频斜率的3倍)；第二加法器，其第一输入端连接至第三锁存器reg3的输出端，第二输入端连接至第一级电路的输出端；第四锁存器reg4，其输入端连接至第二加法器的输出端，其输出端作为第二级电路的输出端；The second-stage circuit includes: a third latch reg3, whose input terminal inputs a control word 3K (that is, 3 times the frequency modulation slope); a second adder, whose first input terminal is connected to the output of the third latch reg3 end, the second input end is connected to the output end of the first stage circuit; the fourth latch reg4, its input end is connected to the output end of the second adder, and its output end is used as the output end of the second stage circuit;
第三级电路，包括：第三加法器，其第一输入端连接至第二级电路的输出端；第五锁存器reg5，其输入端连接至第三加法器的输出端，其输出端作为第三级电路的输出端；The third stage circuit comprises: a third adder, its first input terminal is connected to the output terminal of the second stage circuit; the fifth latch reg5, its input terminal is connected to the output terminal of the third adder, and its output terminal As the output terminal of the third stage circuit;
第四级电路，包括：第六锁存器reg6，其输入端输入控制字K(即调频斜率)；第七锁存器reg7，其输入端连接至第六锁存器reg6的输出端；第四加法器，其第一输入端连接至第七锁存器reg7的输出端，其第二输入端连接至第三级电路的输出端；第八锁存器reg8，其输入端连接至第四加法器的输出端，其输出端作为第四级电路的输出端，同样为该瞬时相位产生模块的输出端。The fourth stage circuit includes: the sixth latch reg6, whose input terminal inputs the control word K (ie, the frequency modulation slope); the seventh latch reg7, whose input terminal is connected to the output terminal of the sixth latch reg6; Four adders, its first input terminal is connected to the output terminal of the seventh latch reg7, its second input terminal is connected to the output terminal of the third stage circuit; the eighth latch reg8, its input terminal is connected to the fourth The output terminal of the adder, which is used as the output terminal of the fourth stage circuit, is also the output terminal of the instantaneous phase generating module.
其中，第一锁存器reg1、第二锁存器reg2、第三锁存器reg3、第四锁存器reg4、第五锁存器reg5、第六锁存器reg6、第七锁存器reg7、第八锁存器reg8的时钟输入端均连接至系统时钟CLK，其频率等于数模转换单元DAC的转换频率；K表示调频斜率，单位为：Hz/s，它能够根据需要设置不同的值。调频斜率K由下式确定：Among them, the first latch reg1, the second latch reg2, the third latch reg3, the fourth latch reg4, the fifth latch reg5, the sixth latch reg6, and the seventh latch reg7 , The clock input terminals of the eighth latch reg8 are connected to the system clock CLK, whose frequency is equal to the conversion frequency of the digital-to-analog conversion unit DAC; K represents the frequency modulation slope, the unit is: Hz/s, and it can be set to different values according to needs . The frequency modulation slope K is determined by the following formula:
K＝B/T (1)K=B/T (1)
其中，B为目标线性调频信号的带宽，T为目标线性调频信号的时宽。Wherein, B is the bandwidth of the target chirp signal, and T is the time width of the target chirp signal.
对于每一锁存器而言，其输出信号相对于输入信号而言延时了一个时钟周期。For each latch, the output signal is delayed by one clock cycle relative to the input signal.
P1、P2和P3是三个中间状态。Phi表示理想线性调频信号的瞬时相位，它和K之间的关系为：P1, P2 and P3 are three intermediate states. Phi represents the instantaneous phase of the ideal chirp signal, and the relationship between it and K is:
Phi＝π·K·n2 (2)Phi＝π·K·n2 (2)
式中：n表示时钟的序号。In the formula: n represents the serial number of the clock.
由于π是一个固定的常数，所以将其从上式中省掉，剩下的部分作为瞬时相位，简化后的瞬时相位为：Since π is a fixed constant, it is omitted from the above formula, and the remaining part is used as the instantaneous phase. The simplified instantaneous phase is:
Phi＝K·n2 (3)Phi=K n2 (3)
为了便于观察图3的工作原理，将相关的信号在各个时钟的状态列成表格，如表1所示。In order to facilitate the observation of the working principle of FIG. 3 , the states of the relevant signals in each clock are listed in a table, as shown in Table 1.
表1 线性调频信号瞬时相位与时钟的关系Table 1 The relationship between the instantaneous phase of the chirp signal and the clock
从表可以清晰看到：Phi和n满足式(2)所示的关系。不同的地方是：Phi相对于n有两个时钟周期的延时，这是由于锁存器造成的，它对最后线性调频信号的产生不会带来影响，只不过实际的线性调频信号相对于理想线性调频信号整体上有两个周期的延时。It can be clearly seen from the table that Phi and n satisfy the relationship shown in formula (2). The difference is: Phi has a delay of two clock cycles relative to n, which is caused by the latch. It will not affect the generation of the final chirp signal, but the actual chirp signal is relative to An ideal chirp signal has an overall delay of two cycles.
然而，由该瞬时相位产生模块所产生信号的较差，并不适合直接输入线性调频信号输出模块。为提高信号质量，需要对瞬时相位产生模块所缠身的信号进行预失真处理，该预失真处理包括两个方面：相位预失真处理和幅度预失真。相位预失真处理在前，幅度预失真处理在后。However, the signal generated by the instantaneous phase generating module is poor and is not suitable for direct input into the linear frequency modulation signal output module. In order to improve the signal quality, it is necessary to perform pre-distortion processing on the signal involved in the instantaneous phase generation module. The pre-distortion processing includes two aspects: phase pre-distortion processing and amplitude pre-distortion processing. The phase pre-distortion processing comes first, and the amplitude pre-distortion processing follows.
在相位预失真处理模块中，相位预失真数据预存于FPGA单元内部的RAM中。预存在FPGA内部RAM的相位预失真数据的产生过程为：利用示波器采集到的预失真前的线性调频信号，在保证抽取后的采样率满足奈奎斯特采样定理的前提下，抽取出其中的相位预失真曲线构成相位预失真数据。其中，该预失真前的线性调频信号为理想的数字线性调频信号经由数模转换器和低通滤波单元后所输出的模拟线性调频信号。In the phase predistortion processing module, the phase predistortion data is pre-stored in the RAM inside the FPGA unit. The process of generating the phase predistortion data pre-stored in FPGA internal RAM is as follows: using the chirp signal before predistortion collected by the oscilloscope, under the premise that the extracted sampling rate satisfies the Nyquist sampling theorem, extract the The phase predistortion curves constitute phase predistortion data. Wherein, the chirp signal before pre-distortion is an analog chirp signal output from an ideal digital chirp signal after passing through a digital-to-analog converter and a low-pass filter unit.
图4示出了相位预失真的时域波形。其中，左边图是抽取前的相位预失真曲线，右边图是经过1000倍抽取后的相位预失真曲线。从图4可以看出，相位预失真曲线的带宽很窄，而数模转换单元(DAC)的转换率很高，所以，相位预失真曲线中存在大量的信息冗余。可以对相位预失真曲线进行抽取，只要保证抽取后的采样率满足奈奎斯特采样定理，就能够保证抽取后的相位预失真曲线能够恢复原始信号，即保留了所关心的主要的信息成分。本发明中，对相位预失真数据抽取的倍数可以限定为200～5000倍。经过抽取处理，相位预失真曲线所对应的数据量得到了1000倍的压缩，极大降低对FPGA内部RAM资源的要求。Figure 4 shows the time-domain waveforms of the phase predistortion. Among them, the left figure is the phase pre-distortion curve before extraction, and the right figure is the phase pre-distortion curve after 1000 times extraction. It can be seen from FIG. 4 that the bandwidth of the phase predistortion curve is very narrow, and the conversion rate of the digital-to-analog conversion unit (DAC) is very high, so there is a large amount of information redundancy in the phase predistortion curve. The phase predistortion curve can be extracted. As long as the extracted sampling rate satisfies the Nyquist sampling theorem, it can be guaranteed that the extracted phase predistortion curve can restore the original signal, that is, the main information components concerned are retained. In the present invention, the multiple of phase predistortion data extraction can be limited to 200-5000 times. After extraction processing, the amount of data corresponding to the phase predistortion curve has been compressed by 1000 times, which greatly reduces the requirements for FPGA internal RAM resources.
在相位预失真处理模块中，相乘的过程为：在高频时钟的作用下，FPGA从内部RAM中读出相位预失真数据，然后将其与图3所示的瞬时相位产生模块所产生的瞬时相位相乘，得到相位预失真的瞬时相位。In the phase predistortion processing module, the process of multiplication is: under the action of the high-frequency clock, the FPGA reads the phase predistortion data from the internal RAM, and then compares it with the instantaneous phase generation module shown in Figure 3. The instantaneous phases are multiplied to obtain the instantaneous phase of the phase predistortion.
在线性调频信号输出模块中，预存有三角函数表。以预失真瞬时相位作为三角函数表的地址，其输出的两个三角函数值为经过相位预失真的三角函数值。该三角函数表是一个查找表，预存在FPGA内部RAM中，它实现第一个象限的相位到幅度的转换。并且，三角函数表中每一个幅度值的位宽W等于数模转换器的转换位数S，其数据个数D的取值满足：D＝2s。A trigonometric function table is pre-stored in the linear frequency modulation signal output module. The predistortion instantaneous phase is used as the address of the trigonometric function table, and the two trigonometric function values outputted are the trigonometric function values after phase predistortion. The trigonometric function table is a look-up table, which is pre-stored in FPGA internal RAM, and it realizes the phase-to-magnitude conversion of the first quadrant. Moreover, the bit width W of each amplitude value in the trigonometric function table is equal to the conversion bit S of the digital-to-analog converter, and the value of the data number D satisfies: D=2s .
为了降低存储空间，利用三角函数关系式，将第二、三、四象限相位的三角函数值映射到第一象限相位对应的三角函数值，此时三角函数表只需要存储第一象限相位对应三角函数值即可，将存储空间降低到原来的1/4。In order to reduce the storage space, the trigonometric function values of the second, third, and fourth quadrant phases are mapped to the trigonometric function values corresponding to the first quadrant phase by using the trigonometric function relational expressions. At this time, the trigonometric function table only needs to store the trigonometric function values corresponding to the first quadrant phase The function value is enough, and the storage space is reduced to 1/4 of the original.
在幅度预失真处理模块中，幅度预失真数据预存在FPGA的内部RAM中。预存在FPGA内部的幅度预失真数据的产生过程为：利用示波器采集到的预失真前的线性调频信号，在保证抽样后的采样率满足奈奎斯特采样定律的前提下，抽取出其中的幅度预失真曲线，如图5所示。其中，该预失真前的线性调频信号为理想的数字线性调频信号经由数模转换器和低通滤波单元后所输出的模拟线性调频信号。需要说明的是，此处的，产生幅度预失真数据的线性调频信号与产生相位预失真数据的线性调频信号的获取过程相同，甚至，两者本来就是同一组信号。In the amplitude pre-distortion processing module, the amplitude pre-distortion data is pre-stored in the internal RAM of the FPGA. The process of generating the amplitude predistortion data pre-stored in the FPGA is: using the linear frequency modulation signal collected by the oscilloscope before predistortion, and under the premise that the sampling rate after sampling satisfies the Nyquist sampling law, extract the amplitude The predistortion curve is shown in Figure 5. Wherein, the chirp signal before pre-distortion is an analog chirp signal output from an ideal digital chirp signal after passing through a digital-to-analog converter and a low-pass filter unit. It should be noted that, here, the acquisition process of the chirp signal generating the amplitude predistortion data is the same as that of the chirp signal generating phase predistortion data, and even the two are originally the same group of signals.
图5示出了经过预失真后线性调频信号的频谱图。图5的左边图是抽取前的幅度预失真曲线，右边图是经过1000倍抽取后的幅度预失真曲线。从图5可以看出，幅度预失真曲线的带宽很窄，而DAC的转换率很高，所以，幅度预失真曲线中存在大量的信息冗余。可以对幅度预失真曲线进行抽取，只要保证抽取后的采样率满足奈奎斯特采样定理，就能够保证抽取后的幅度预失真曲线能够恢复原始信号，即保留了所关心的主要的信息成分。本发明中，对幅度预失真数据抽取的倍数可以限定为200～5000倍。经过抽取处理，幅度预失真曲线所对应的数据量得到了1000倍的压缩，极大降低对FPGA内部RAM资源的要求。Fig. 5 shows a spectrum diagram of a chirp signal after predistortion. The left figure of Fig. 5 is the amplitude predistortion curve before extraction, and the right figure is the amplitude predistortion curve after 1000 times extraction. It can be seen from Fig. 5 that the bandwidth of the amplitude predistortion curve is very narrow, and the conversion rate of the DAC is very high, so there is a large amount of information redundancy in the amplitude predistortion curve. The amplitude predistortion curve can be extracted. As long as the extracted sampling rate satisfies the Nyquist sampling theorem, it can be guaranteed that the extracted amplitude predistortion curve can restore the original signal, that is, the main information components concerned are retained. In the present invention, the multiple of amplitude predistortion data extraction can be limited to 200-5000 times. After extraction processing, the amount of data corresponding to the amplitude predistortion curve has been compressed by 1000 times, which greatly reduces the requirements for FPGA internal RAM resources.
在幅度预失真处理模块中，相乘的过程为：在高频时钟的作用下，从FPGA内部RAM中读出幅度预失真数据，然后将其与线性调频信号输出模块输出的相位预失真后的线性调频信号幅度值相乘，得到幅相预失真的线性调频信号幅度值。In the amplitude predistortion processing module, the multiplication process is: under the action of the high-frequency clock, read the amplitude predistortion data from the FPGA internal RAM, and then combine it with the phase predistortion output from the chirp signal output module The amplitude values of the linear frequency modulation signals are multiplied to obtain the amplitude value of the linear frequency modulation signal with amplitude and phase predistortion.
本实施例中，预存于FPGA的RAM中的相位预失真数据和幅度预失真数据的数量取决于幅相失真的带宽。实测结果表明：幅相失真为低频窄带信号，对幅相预失真数据进行大幅抽取，然后再将它们预存在FPGA内部RAM中，这种方法在不丢失信息的前提下，将数据存储量降低到原数据量的1/64甚至更低，直接降低了对FPGA内部宝贵的RAM资源的要求。In this embodiment, the quantity of the phase predistortion data and the amplitude predistortion data prestored in the RAM of the FPGA depends on the bandwidth of the amplitude and phase distortion. The actual measurement results show that the amplitude-phase distortion is a low-frequency narrow-band signal, and the amplitude-phase predistortion data is largely extracted, and then they are pre-stored in the internal RAM of the FPGA. This method reduces the amount of data storage to 1/64 of the original data volume is even lower, which directly reduces the requirements for the precious RAM resources inside the FPGA.
基于上述说明，本发明线性调频信号发生器产生过程如下：Based on the above description, the generation process of the chirp signal generator of the present invention is as follows:
步骤A：根据线性调频信号的时宽和带宽计算调频斜率K，其中：Step A: Calculate the frequency modulation slope K according to the time width and bandwidth of the linear frequency modulation signal, where:
K＝B/T，其中，B为目标线性调频信号的带宽，T为目标线性调频信号的时宽。K=B/T, where B is the bandwidth of the target chirp signal, and T is the time width of the target chirp signal.
步骤B：在外触发信号的控制下，第一个加法器对二倍的调频率进行累加，得到P1；Step B: Under the control of the external trigger signal, the first adder accumulates twice the modulation frequency to obtain P1;
步骤C：第二个加法器实现P1与调频率的求和，得到P2；Step C: The second adder implements the sum of P1 and modulation frequency to obtain P2;
步骤D：第三个加法器对P2进行累加，得到P3；Step D: The third adder accumulates P2 to obtain P3;
步骤E：第四个加法器实现P3与调频率的求和，得到理想线性调频信号的瞬时相位；Step E: the fourth adder implements the summation of P3 and frequency modulation to obtain the instantaneous phase of the ideal linear frequency modulation signal;
步骤F：瞬时相位与预存在FPGA内部RAM中的相位预失真数据相乘，得到实际的瞬时相位；Step F: Multiply the instantaneous phase with the phase predistortion data pre-stored in the FPGA internal RAM to obtain the actual instantaneous phase;
步骤G：将实际的瞬时相位映射到笛卡儿坐标系的第一个象限，通过查找三角函数表，得到映射相位对应的三角函数值，得到相位预失真后的两路正交的线性调频信号幅度值，完成相位到幅度的转换；Step G: Map the actual instantaneous phase to the first quadrant of the Cartesian coordinate system, obtain the trigonometric function value corresponding to the mapped phase by looking up the trigonometric function table, and obtain two orthogonal chirp signals after phase predistortion Amplitude value, complete the conversion from phase to amplitude;
步骤H：根据映射关系，得到相位预失真的线性调频信号幅度值；Step H: Obtain the amplitude value of the phase predistorted chirp signal according to the mapping relationship;
步骤I：将线性调频信号输出模块输出的两路正交的线性调频信号幅度值分别与自身预存的幅度预失真数据相乘，得到幅相预失真后的两路正交的线性调频信号幅度值。Step I: Multiply the two-way orthogonal chirp signal amplitude values output by the chirp signal output module with the amplitude pre-distortion data stored in itself respectively, to obtain the two-way orthogonal chirp signal amplitude values after the amplitude-phase pre-distortion .
本实施例中，目标线性调频信号的带宽为600MHz，时宽为100μs；据此，数模转换单元DAC的转换频率为2GHz。低通滤波单元，与数模转换单元相连接，用于滤除离散模拟线性调频信号中预设频率范围0～700MHz之外的频率成分，得到连续的模拟线性调频信号。两路经过预失真处理的数字线性调频信号经过数模转换单元转换，然后低通滤波，即可得到两路正交的线性调频信号I和Q。In this embodiment, the bandwidth of the target chirp signal is 600 MHz, and the duration is 100 μs; accordingly, the conversion frequency of the digital-to-analog conversion unit DAC is 2 GHz. The low-pass filter unit is connected with the digital-to-analog conversion unit, and is used for filtering frequency components outside the preset frequency range of 0-700 MHz in the discrete analog chirp signal to obtain a continuous analog chirp signal. The two pre-distorted digital chirp signals are converted by a digital-to-analog conversion unit, and then low-pass filtered to obtain two orthogonal chirp signals I and Q.
为了验证本实施例的实际效果，用两根同轴射频线缆将示波器的两个输入端连接在线性调频信号发生器的两个模拟输出端。示波器的采样率设置为10GSPS。用示波器将采集下来的两路信号I和Q保存下来，复制到计算机中，用计算机软件进行分析。由于信号I和Q具有相同的特性，所以在分析中，只考虑其中的一路信号I，另外一路信号Q采用与此相同的方法。In order to verify the actual effect of this embodiment, two coaxial radio frequency cables are used to connect the two input terminals of the oscilloscope to the two analog output terminals of the chirp signal generator. The sampling rate of the oscilloscope is set to 10GSPS. Use an oscilloscope to save the two signals I and Q collected, copy them to the computer, and use computer software for analysis. Since the signals I and Q have the same characteristics, only one signal I is considered in the analysis, and the other signal Q uses the same method.
图6和图7分别为采用现有技术的线性调频信号发生器产生线性调频信号的频谱和时域波形。在现有技术的线性调频信号发生器中，将该瞬时相位产生模块输出的瞬时相位直接作为三角函数表的输入地址由线性调频信号输出模块的输入端输入，并将线性调频信号输出模块的输出端连接至数模转换单元，经过低通滤波处理后，用频谱仪采集到信号的频谱图如图6所示。从图中可以看出信号的带内平坦度为3dB。用示波器采集到的基带信号I和Q绘制在Matlab窗口中，如图7所示。由于受到DAC器件和模拟电路的影响，图6和图7所示信号的质量难以满足实际系统的要求，所以需要对送给DAC转换的数字信号进行预失真处理，控制信号的带内平坦度，提高其线性度。Fig. 6 and Fig. 7 respectively show the frequency spectrum and time domain waveform of the chirp signal generated by the chirp signal generator in the prior art. In the chirp signal generator of the prior art, the instantaneous phase output by the instantaneous phase generation module is directly used as the input address of the trigonometric function table by the input terminal of the chirp signal output module, and the output of the chirp signal output module The terminal is connected to the digital-to-analog conversion unit, and after low-pass filtering, the frequency spectrum of the signal collected by the spectrum analyzer is shown in Figure 6. It can be seen from the figure that the in-band flatness of the signal is 3dB. The baseband signals I and Q collected by the oscilloscope are plotted in the Matlab window, as shown in Figure 7. Due to the influence of DAC devices and analog circuits, the quality of the signals shown in Figure 6 and Figure 7 is difficult to meet the requirements of the actual system, so it is necessary to perform pre-distortion processing on the digital signal sent to the DAC conversion to control the in-band flatness of the signal. improve its linearity.
图8和图9分别为采用本实施例线性调频信号发生器产生线性调频信号的频谱和时域波形。从图8中可以看出信号的带内平坦度为1dB。用示波器采集到的基带信号I和Q绘制在Matlab窗口中，如图9所示。比较图9和图5，可以看出：经过预失真处理后，产生的线性调频信号质量得到明显提高。FIG. 8 and FIG. 9 respectively show the frequency spectrum and time domain waveform of the chirp signal generated by the chirp signal generator of this embodiment. It can be seen from Figure 8 that the in-band flatness of the signal is 1dB. The baseband signals I and Q collected by the oscilloscope are plotted in the Matlab window, as shown in Figure 9. Comparing Fig. 9 and Fig. 5, it can be seen that after pre-distortion processing, the quality of the generated chirp signal is significantly improved.
至此，已经结合附图对本实施例进行了详细描述。依据以上描述，本领域技术人员应当对本发明具有预失真功能的线性调频信号发生器有了清楚的认识。So far, the present embodiment has been described in detail with reference to the drawings. Based on the above description, those skilled in the art should have a clear understanding of the chirp signal generator with predistortion function of the present invention.
此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换，例如：(1)瞬时相位产生模块还可以DDS形式产生；(2)数模转换单元的转换频率、信号的带宽、信号的时宽以及低通滤波器的通带频率等具体参数可以根据实际场景的需要进行调整，而不限于上述实施例中所给出的具体值。In addition, the above-mentioned definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and those skilled in the art can easily modify or replace them, for example: (1) Instantaneous phase The generation module can also be generated in the form of DDS; (2) specific parameters such as the conversion frequency of the digital-to-analog conversion unit, the bandwidth of the signal, the time width of the signal, and the passband frequency of the low-pass filter can be adjusted according to the needs of the actual scene, instead of Limited to the specific values given in the above examples.
综上所述，本发明提供的具有预失真功能的线性调频信号发生器通过采用预存一个象限的三角函数查找表和少量的幅相失真数据的方案，在产生长脉冲信号时候充分利用FPGA内部的存储资源，无需扩展外部DRAM，整个结构变成了一片FPGA加数模转换器的模式，提高了系统的集成度，实现了线性调频信号发生器的轻小型化和低成本。In summary, the chirp signal generator with pre-distortion function provided by the present invention makes full use of the FPGA internal There is no need to expand the external DRAM for storage resources, and the whole structure becomes a mode of an FPGA plus a digital-to-analog converter, which improves the integration of the system and realizes the miniaturization and low cost of the chirp signal generator.
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
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| CN1236110A (en)* | 1998-05-14 | 1999-11-24 | 中国科学院电子学研究所 | Linear frequency modulation signal source |
| CN101799534A (en)* | 2009-02-11 | 2010-08-11 | 中国科学院电子学研究所 | Radar intermediate-frequency signal generator |
| CN102185636A (en)* | 2011-03-16 | 2011-09-14 | 杭州华韵天略电子科技有限公司 | Method and system for modulating and demodulating sound wave by using linear frequency modulation signal |
| CN102749957A (en)* | 2012-06-20 | 2012-10-24 | 中国科学院空间科学与应用研究中心 | Linear frequency modulation signal generation device for satellite borne equipment |
| CN103675767A (en)* | 2013-09-02 | 2014-03-26 | 中国科学院电子学研究所 | An ultra wide band low power radiofrequency signal generator and a method thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
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| US4107679A (en)* | 1976-03-12 | 1978-08-15 | Telecommunications Radioelectriques Et Telephoniques T.R.T. | Frequency modulator for high-precision range measurements |
| CN1236110A (en)* | 1998-05-14 | 1999-11-24 | 中国科学院电子学研究所 | Linear frequency modulation signal source |
| CN101799534A (en)* | 2009-02-11 | 2010-08-11 | 中国科学院电子学研究所 | Radar intermediate-frequency signal generator |
| CN102185636A (en)* | 2011-03-16 | 2011-09-14 | 杭州华韵天略电子科技有限公司 | Method and system for modulating and demodulating sound wave by using linear frequency modulation signal |
| CN102749957A (en)* | 2012-06-20 | 2012-10-24 | 中国科学院空间科学与应用研究中心 | Linear frequency modulation signal generation device for satellite borne equipment |
| CN103675767A (en)* | 2013-09-02 | 2014-03-26 | 中国科学院电子学研究所 | An ultra wide band low power radiofrequency signal generator and a method thereof |
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